diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-05-24 19:54:22 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-05-24 19:54:22 +0000 |
| commit | 7c05d2806c7283a1849d8336b08c869bd6ad8b20 (patch) | |
| tree | 8e8267495604d4a9d346229cffce4fd0188f7054 /c/src/lib/libcpu/mips/tx39/include/tx3904.h | |
| parent | 2000-05-24 Joel Sherrill <joel@OARcorp.com> (diff) | |
| download | rtems-7c05d2806c7283a1849d8336b08c869bd6ad8b20.tar.bz2 | |
2000-05-24 Joel Sherrill <joel@OARcorp.com>
* mongoosev/include/mongoose-v.h, mongoosev/vectorisrs/vectorisrs.c,
r46xx/vectorisrs/vectorisrs.c, tx39/vectorisrs/vectorisrs.c,
tx39/include/tx3904.h: All exceptions were given low numbers and thus
can be now be installed and processed in a uniform manner just like interrupts.
Variances between various MIPS ISA levels are not accounted for at this time.
* mongoosev/vectorisrs/Makefile.am, mongoosev/vectorisrs/maxvectors.c,
r46xx/vectorisrs/Makefile.am, r46xx/vectorisrs/maxvectors.c,
tx39/vectorisrs/Makefile.am, tx39/vectorisrs/maxvectors.c,
shared/interrupts/maxvectors.c, shared/interrupts/Makefile.am: Split the
shared maxvectors.c into a variety of CPU model specific versions to simplify
the build process and reduce depdencies. Deleted shared/interrupts/maxvectors.c
and created various CPU model versions.
Diffstat (limited to 'c/src/lib/libcpu/mips/tx39/include/tx3904.h')
| -rw-r--r-- | c/src/lib/libcpu/mips/tx39/include/tx3904.h | 39 |
1 files changed, 20 insertions, 19 deletions
diff --git a/c/src/lib/libcpu/mips/tx39/include/tx3904.h b/c/src/lib/libcpu/mips/tx39/include/tx3904.h index ac0efae1f6..eb8f60a36e 100644 --- a/c/src/lib/libcpu/mips/tx39/include/tx3904.h +++ b/c/src/lib/libcpu/mips/tx39/include/tx3904.h @@ -40,24 +40,25 @@ * Number 16 is "1xxxx" per p. 164 of the TX3904 manual. */ -#define TX3904_IRQ_INT1 0 -#define TX3904_IRQ_INT2 1 -#define TX3904_IRQ_INT3 2 -#define TX3904_IRQ_INT4 3 -#define TX3904_IRQ_INT5 4 -#define TX3904_IRQ_INT6 5 -#define TX3904_IRQ_INT7 6 -#define TX3904_IRQ_DMAC3 7 -#define TX3904_IRQ_DMAC2 8 -#define TX3904_IRQ_DMAC1 9 -#define TX3904_IRQ_DMAC0 10 -#define TX3904_IRQ_SIO0 11 -#define TX3904_IRQ_SIO1 12 -#define TX3904_IRQ_TMR0 13 -#define TX3904_IRQ_TMR1 14 -#define TX3904_IRQ_TMR2 15 -#define TX3904_IRQ_INT0 16 -#define TX3904_IRQ_SOFTWARE_1 17 -#define TX3904_IRQ_SOFTWARE_2 18 +#define TX3904_IRQ_INT1 MIPS_INTERRUPT_BASE+0 +#define TX3904_IRQ_INT2 MIPS_INTERRUPT_BASE+1 +#define TX3904_IRQ_INT3 MIPS_INTERRUPT_BASE+2 +#define TX3904_IRQ_INT4 MIPS_INTERRUPT_BASE+3 +#define TX3904_IRQ_INT5 MIPS_INTERRUPT_BASE+4 +#define TX3904_IRQ_INT6 MIPS_INTERRUPT_BASE+5 +#define TX3904_IRQ_INT7 MIPS_INTERRUPT_BASE+6 +#define TX3904_IRQ_DMAC3 MIPS_INTERRUPT_BASE+7 +#define TX3904_IRQ_DMAC2 MIPS_INTERRUPT_BASE+8 +#define TX3904_IRQ_DMAC1 MIPS_INTERRUPT_BASE+9 +#define TX3904_IRQ_DMAC0 MIPS_INTERRUPT_BASE+10 +#define TX3904_IRQ_SIO0 MIPS_INTERRUPT_BASE+11 +#define TX3904_IRQ_SIO1 MIPS_INTERRUPT_BASE+12 +#define TX3904_IRQ_TMR0 MIPS_INTERRUPT_BASE+13 +#define TX3904_IRQ_TMR1 MIPS_INTERRUPT_BASE+14 +#define TX3904_IRQ_TMR2 MIPS_INTERRUPT_BASE+15 +#define TX3904_IRQ_INT0 MIPS_INTERRUPT_BASE+16 +#define TX3904_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+17 +#define TX3904_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+18 +#define TX3904_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+19 #endif |