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authorJoel Sherrill <joel.sherrill@OARcorp.com>2001-05-24 19:54:22 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2001-05-24 19:54:22 +0000
commit7c05d2806c7283a1849d8336b08c869bd6ad8b20 (patch)
tree8e8267495604d4a9d346229cffce4fd0188f7054 /c/src/lib/libcpu
parent6937dfd6aa6f8fab612addec7b20798f66730846 (diff)
downloadrtems-7c05d2806c7283a1849d8336b08c869bd6ad8b20.tar.bz2
2000-05-24 Joel Sherrill <joel@OARcorp.com>
* mongoosev/include/mongoose-v.h, mongoosev/vectorisrs/vectorisrs.c, r46xx/vectorisrs/vectorisrs.c, tx39/vectorisrs/vectorisrs.c, tx39/include/tx3904.h: All exceptions were given low numbers and thus can be now be installed and processed in a uniform manner just like interrupts. Variances between various MIPS ISA levels are not accounted for at this time. * mongoosev/vectorisrs/Makefile.am, mongoosev/vectorisrs/maxvectors.c, r46xx/vectorisrs/Makefile.am, r46xx/vectorisrs/maxvectors.c, tx39/vectorisrs/Makefile.am, tx39/vectorisrs/maxvectors.c, shared/interrupts/maxvectors.c, shared/interrupts/Makefile.am: Split the shared maxvectors.c into a variety of CPU model specific versions to simplify the build process and reduce depdencies. Deleted shared/interrupts/maxvectors.c and created various CPU model versions.
Diffstat (limited to 'c/src/lib/libcpu')
-rw-r--r--c/src/lib/libcpu/mips/ChangeLog15
-rw-r--r--c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h129
-rw-r--r--c/src/lib/libcpu/mips/mongoosev/vectorisrs/Makefile.am2
-rw-r--r--c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c (renamed from c/src/lib/libcpu/mips/shared/interrupts/maxvectors.c)22
-rw-r--r--c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c184
-rw-r--r--c/src/lib/libcpu/mips/r46xx/vectorisrs/Makefile.am2
-rw-r--r--c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c20
-rw-r--r--c/src/lib/libcpu/mips/r46xx/vectorisrs/vectorisrs.c36
-rw-r--r--c/src/lib/libcpu/mips/shared/interrupts/Makefile.am2
-rw-r--r--c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c115
-rw-r--r--c/src/lib/libcpu/mips/tx39/include/tx3904.h39
-rw-r--r--c/src/lib/libcpu/mips/tx39/vectorisrs/Makefile.am2
-rw-r--r--c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c30
-rw-r--r--c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c43
14 files changed, 308 insertions, 333 deletions
diff --git a/c/src/lib/libcpu/mips/ChangeLog b/c/src/lib/libcpu/mips/ChangeLog
index 9d11da20bb..7d615eb071 100644
--- a/c/src/lib/libcpu/mips/ChangeLog
+++ b/c/src/lib/libcpu/mips/ChangeLog
@@ -1,3 +1,18 @@
+2000-05-24 Joel Sherrill <joel@OARcorp.com>
+
+ * mongoosev/include/mongoose-v.h, mongoosev/vectorisrs/vectorisrs.c,
+ r46xx/vectorisrs/vectorisrs.c, tx39/vectorisrs/vectorisrs.c,
+ tx39/include/tx3904.h: All exceptions were given low numbers and thus
+ can be now be installed and processed in a uniform manner just like interrupts.
+ Variances between various MIPS ISA levels are not accounted for at this time.
+ * mongoosev/vectorisrs/Makefile.am, mongoosev/vectorisrs/maxvectors.c,
+ r46xx/vectorisrs/Makefile.am, r46xx/vectorisrs/maxvectors.c,
+ tx39/vectorisrs/Makefile.am, tx39/vectorisrs/maxvectors.c,
+ shared/interrupts/maxvectors.c, shared/interrupts/Makefile.am: Split the
+ shared maxvectors.c into a variety of CPU model specific versions to simplify
+ the build process and reduce depdencies. Deleted shared/interrupts/maxvectors.c
+ and created various CPU model versions.
+
2001-05-24 Greg Menke <gregory.menke@gsfc.nasa.gov>
* clock/clock.S: Move placement of nop.
diff --git a/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h b/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h
index 1876ee56f7..97412ecd5e 100644
--- a/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h
+++ b/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h
@@ -248,18 +248,18 @@
* per p. 5-22 of Mongoose-V manual.
*/
-#define MONGOOSEV_IRQ_INT0 0
+#define MONGOOSEV_IRQ_INT0 MIPS_INTERRUPT_BASE+0
#define MONGOOSEV_IRQ_TIMER1 MONGOOSEV_IRQ_INT0
-#define MONGOOSEV_IRQ_INT1 1
+#define MONGOOSEV_IRQ_INT1 MIPS_INTERRUPT_BASE+1
#define MONGOOSEV_IRQ_TIMER2 MONGOOSEV_IRQ_INT1
-#define MONGOOSEV_IRQ_INT2 2
-#define MONGOOSEV_IRQ_INT3 3
+#define MONGOOSEV_IRQ_INT2 MIPS_INTERRUPT_BASE+2
+#define MONGOOSEV_IRQ_INT3 MIPS_INTERRUPT_BASE+3
#define MONGOOSEV_IRQ_FPU MONGOOSEV_IRQ_INT3
-#define MONGOOSEV_IRQ_INT4 4
+#define MONGOOSEV_IRQ_INT4 MIPS_INTERRUPT_BASE+4
/* MONGOOSEV_IRQ_INT5 indicates that a peripheral caused the IRQ. */
-#define MONGOOSEV_IRQ_PERIPHERAL_BASE 5
+#define MONGOOSEV_IRQ_PERIPHERAL_BASE MIPS_INTERRUPT_BASE+5
#define MONGOOSEV_IRQ_XINT0 MONGOOSEV_IRQ_PERIPHERAL_BASE + 0
#define MONGOOSEV_IRQ_XINT1 MONGOOSEV_IRQ_PERIPHERAL_BASE + 1
#define MONGOOSEV_IRQ_XINT2 MONGOOSEV_IRQ_PERIPHERAL_BASE + 2
@@ -293,82 +293,55 @@
#define MONGOOSEV_IRQ_UNCORRECTABLE_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 30
#define MONGOOSEV_IRQ_CORRECTABLE_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 31
-#define MONGOOSEV_IRQ_SOFTWARE_1 37
-#define MONGOOSEV_IRQ_SOFTWARE_2 38
+#define MONGOOSEV_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+37
+#define MONGOOSEV_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+38
+#define MONGOOSEV_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+39
-/* gdm, 5/14. Added exception vectoring to the ISR table- these
-entries are never called by the ISR servicing, only by the exception
-servicing routine. The ISR table is used because vector setup there
-is already supported. Please note exception routines are passed 2
-parameters; one of the below vectors and a pointer to the exception's
-stack frame, the register layout of which is found in
-
-exec/score/cpu/mips/iregdef.h
-
-in conjunction with
-
-exec/score/cpu/mips/cpu_asm.S
-
-*/
+/*
+ * Status Register Bits
+ */
-#define MONGOOSEV_EXCEPTION_BASE 39
-
-#define MONGOOSEV_EXCEPTION_ADEL MONGOOSEV_EXCEPTION_BASE+0
-#define MONGOOSEV_EXCEPTION_ADES MONGOOSEV_EXCEPTION_BASE+1
-#define MONGOOSEV_EXCEPTION_IBE MONGOOSEV_EXCEPTION_BASE+2
-#define MONGOOSEV_EXCEPTION_DBE MONGOOSEV_EXCEPTION_BASE+3
-#define MONGOOSEV_EXCEPTION_SYSCALL MONGOOSEV_EXCEPTION_BASE+4
-#define MONGOOSEV_EXCEPTION_BREAK MONGOOSEV_EXCEPTION_BASE+5
-#define MONGOOSEV_EXCEPTION_RI MONGOOSEV_EXCEPTION_BASE+6
-#define MONGOOSEV_EXCEPTION_CPU MONGOOSEV_EXCEPTION_BASE+7
-#define MONGOOSEV_EXCEPTION_OVERFLOW MONGOOSEV_EXCEPTION_BASE+8
-
-
-
-
-
-
-#define SR_CUMASK 0xf0000000 /* coproc usable bits */
-#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
-#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
-#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
-#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
-#define SR_BEV 0x00400000 /* use boot exception vectors */
-#define SR_TS 0x00200000 /* TLB shutdown */
-#define SR_PE 0x00100000 /* cache parity error */
-#define SR_CM 0x00080000 /* cache miss */
-#define SR_PZ 0x00040000 /* cache parity zero */
-#define SR_SWC 0x00020000 /* swap cache */
-#define SR_ISC 0x00010000 /* Isolate data cache */
-#define SR_IMASK 0x0000ff00 /* Interrupt mask */
-#define SR_IMASK8 0x00000000 /* mask level 8 */
-#define SR_IMASK7 0x00008000 /* mask level 7 */
-#define SR_IMASK6 0x0000c000 /* mask level 6 */
-#define SR_IMASK5 0x0000e000 /* mask level 5 */
-#define SR_IMASK4 0x0000f000 /* mask level 4 */
-#define SR_IMASK3 0x0000f800 /* mask level 3 */
-#define SR_IMASK2 0x0000fc00 /* mask level 2 */
-#define SR_IMASK1 0x0000fe00 /* mask level 1 */
-#define SR_IMASK0 0x0000ff00 /* mask level 0 */
-
-#define SR_IBIT8 0x00008000 /* bit level 8 */
-#define SR_IBIT7 0x00004000 /* bit level 7 */
-#define SR_IBIT6 0x00002000 /* bit level 6 */
-#define SR_IBIT5 0x00001000 /* bit level 5 */
-#define SR_IBIT4 0x00000800 /* bit level 4 */
-#define SR_IBIT3 0x00000400 /* bit level 3 */
-#define SR_IBIT2 0x00000200 /* bit level 2 */
-#define SR_IBIT1 0x00000100 /* bit level 1 */
-
-#define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */
-#define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */
-#define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */
-#define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */
-#define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */
-#define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */
+#define SR_CUMASK 0xf0000000 /* coproc usable bits */
+#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
+#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
+#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
+#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
+#define SR_BEV 0x00400000 /* use boot exception vectors */
+#define SR_TS 0x00200000 /* TLB shutdown */
+#define SR_PE 0x00100000 /* cache parity error */
+#define SR_CM 0x00080000 /* cache miss */
+#define SR_PZ 0x00040000 /* cache parity zero */
+#define SR_SWC 0x00020000 /* swap cache */
+#define SR_ISC 0x00010000 /* Isolate data cache */
+#define SR_IMASK 0x0000ff00 /* Interrupt mask */
+#define SR_IMASK8 0x00000000 /* mask level 8 */
+#define SR_IMASK7 0x00008000 /* mask level 7 */
+#define SR_IMASK6 0x0000c000 /* mask level 6 */
+#define SR_IMASK5 0x0000e000 /* mask level 5 */
+#define SR_IMASK4 0x0000f000 /* mask level 4 */
+#define SR_IMASK3 0x0000f800 /* mask level 3 */
+#define SR_IMASK2 0x0000fc00 /* mask level 2 */
+#define SR_IMASK1 0x0000fe00 /* mask level 1 */
+#define SR_IMASK0 0x0000ff00 /* mask level 0 */
+
+#define SR_IBIT8 0x00008000 /* bit level 8 */
+#define SR_IBIT7 0x00004000 /* bit level 7 */
+#define SR_IBIT6 0x00002000 /* bit level 6 */
+#define SR_IBIT5 0x00001000 /* bit level 5 */
+#define SR_IBIT4 0x00000800 /* bit level 4 */
+#define SR_IBIT3 0x00000400 /* bit level 3 */
+#define SR_IBIT2 0x00000200 /* bit level 2 */
+#define SR_IBIT1 0x00000100 /* bit level 1 */
+
+#define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */
+#define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */
+#define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */
+#define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */
+#define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */
+#define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */
#define SR_KUMSK (SR_KUO|SR_IEO|SR_KUP|SR_IEP|SR_KUC|SR_IEC)
-#define SR_IMASKSHIFT 8
+#define SR_IMASKSHIFT 8
#endif
diff --git a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/Makefile.am b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/Makefile.am
index 16c4dbef0b..761fa2914c 100644
--- a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/Makefile.am
+++ b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/Makefile.am
@@ -6,7 +6,7 @@ AUTOMAKE_OPTIONS = foreign 1.4
PGM = $(ARCH)/vectorisrs.rel
-C_FILES = vectorisrs.c
+C_FILES = maxvectors.c vectorisrs.c
vectorisrs_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) $(S_FILES:%.S=$(ARCH)/%.o)
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/maxvectors.c b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c
index f2fb9d2e17..ff9fef73a8 100644
--- a/c/src/lib/libcpu/mips/shared/interrupts/maxvectors.c
+++ b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c
@@ -12,18 +12,10 @@
* $Id$
*/
-
/*
- * The Toshiba TX3904 attaches 4 of the eight interrupt bits to an
- * on-CPU interrupt controller so that these four bits map to 16
- * unique interrupts. So you have: 2 software interrupts, an NMI,
- * and 16 others.
+ * Reserve first 32 for exceptions.
*/
-#if defined(TX39)
-#define MAX_VECTORS 19
-#endif
-
/*
* The Synova Mongoose-V attached one of the eight interrupt bits
* to a Peripheral Function Interrupt Cause Register on-CPU.
@@ -31,17 +23,11 @@
* through the IP bits, and 32 more from the PFICR. Some of
* these are reserved but for simplicity in processing, we
* reserve slots for those bits anyway.
- *
- * gdm, 5/14, added 15 more slots so exceptions can be vectored as well.
*/
-#if defined(MONGOOSEV)
-#define MAX_VECTORS (38+10)
-#endif
+#include <rtems.h>
+#include <libcpu/mongoose-v.h>
-#ifndef MAX_VECTORS
-#define MAX_VECTORS 8
-#endif
+unsigned int mips_interrupt_number_of_vectors = MONGOOSEV_MAXIMUM_VECTORS;
-unsigned int mips_interrupt_number_of_vectors = MAX_VECTORS;
diff --git a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c
index 50e1272bac..4adbdc30e8 100644
--- a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c
+++ b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c
@@ -29,11 +29,6 @@
#include <bspIo.h> /* for printk */
-
-
-
-
-
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
{
unsigned32 sr, srmaskoff;
@@ -117,12 +112,6 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
mips_set_sr( sr );
}
-
-
-
-
-
-
void mips_default_isr( int vector )
{
unsigned int sr;
@@ -131,17 +120,11 @@ void mips_default_isr( int vector )
mips_get_sr( sr );
mips_get_cause( cause );
- printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n", vector, cause, sr );
+ printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
+ vector, cause, sr );
rtems_fatal_error_occurred(1);
}
-
-
-
-
-
-
-
/* userspace routine to assert either software interrupt */
int assertSoftwareInterrupt( unsigned32 n )
@@ -159,166 +142,3 @@ int assertSoftwareInterrupt( unsigned32 n )
else return -1;
}
-
-
-
-
-
-
-
-
-
-
-/* exception vectoring, from vectorexceptions.c */
-
-/*#include <rtems.h>
-#include <stdlib.h>
-#include "iregdef.h"
-#include <bsp.h>
-#include <bspIo.h>*/
-
-
-
-
-char *cause_strings[32] =
-{
- /* 0 */ "Int",
- /* 1 */ "TLB Mods",
- /* 2 */ "TLB Load",
- /* 3 */ "TLB Store",
- /* 4 */ "Address Load",
- /* 5 */ "Address Store",
- /* 6 */ "Instruction Bus Error",
- /* 7 */ "Data Bus Error",
- /* 9 */ "Syscall",
- /* 10 */ "Breakpoint",
- /* 11 */ "Reserved Instruction",
- /* 12 */ "Coprocessor Unuseable",
- /* 13 */ "Overflow",
- /* 14 */ "Trap",
- /* 15 */ "Instruction Virtual Coherency Error",
- /* 16 */ "FP Exception",
- /* 17 */ "Reserved 17",
- /* 18 */ "Reserved 17",
- /* 19 */ "Reserved 17",
- /* 20 */ "Reserved 20",
- /* 21 */ "Reserved 21",
- /* 22 */ "Reserved 22",
- /* 23 */ "Watch",
- /* 24 */ "Reserved 24",
- /* 25 */ "Reserved 25",
- /* 26 */ "Reserved 26",
- /* 27 */ "Reserved 27",
- /* 28 */ "Reserved 28",
- /* 29 */ "Reserved 29",
- /* 30 */ "Reserved 30",
- /* 31 */ "Data Virtual Coherency Error"
-};
-
-
-
-struct regdef
-{
- int offset;
- char *name;
-};
-
-
-/*
- * this struct holds the set of registers we're going to dump on an
- * exception, the symbols are defined by iregdef.h, and they are set
- * by cpu_asm.S into the CPU_Interrupt_frame passed here by
- * ISR_Handler. Note not all registers are stored, only those used
- * by the cpu_asm.S code. Refer to cpu_asm.S
- */
-
-
-struct regdef dumpregs[]= { { R_RA, "R_RA" }, { R_V0, "R_V0" }, { R_V1, "R_V1" }, { R_A0, "R_A0" }, { R_A1, "R_A1" }, { R_A2, "R_A2" }, \
- { R_A3, "R_A3" }, { R_T0, "R_T0" }, { R_T1, "R_T1" }, { R_T2, "R_T2" }, { R_T3, "R_T3" }, { R_T4, "R_T4" }, \
- { R_T5, "R_T5" }, { R_T6, "R_T6" }, { R_T7, "R_T7" }, { R_T8, "R_T8" }, { R_MDLO, "R_MDLO" }, { R_MDHI, "R_MDHI" }, \
- { R_GP, "R_GP" }, { R_FP, "R_FP" }, { R_AT, "R_AT" }, { R_EPC,"R_EPC"}, { -1, NULL } };
-
-
-
-void mips_default_exception_code_handler( int exc, CPU_Interrupt_frame *frame )
-{
- unsigned int sr;
- unsigned int cause;
- int i, j;
-
- mips_get_sr( sr );
- mips_get_cause( cause );
-
- printk( "Unhandled exception %d\n", exc );
- printk( "sr: 0x%08x cause: 0x%08x --> %s\n", sr, cause, cause_strings[(cause >> 2) &0x1f] );
-
- for(i=0; dumpregs[i].offset > -1; i++)
- {
- printk(" %s", dumpregs[i].name);
- for(j=0; j< 7-strlen(dumpregs[i].name); j++) printk(" ");
- printk(" %08X\n", frame->regs[dumpregs[i].offset] );
- }
-
- rtems_fatal_error_occurred(1);
-}
-
-
-
-
-
-
-
-#define CALL_EXC(_vector,_frame) \
- do { \
- if( _ISR_Vector_table[_vector] ) \
- (_ISR_Vector_table[_vector])(_vector,_frame); \
- else \
- mips_default_exception_code_handler( _vector, _frame ); \
- } while(0)
-
-
-
-
-
-void mips_vector_exceptions( CPU_Interrupt_frame *frame )
-{
- unsigned32 cause;
- unsigned32 exc;
-
- mips_get_cause( cause );
- exc = (cause >> 2) & 0x1f;
-
- if( exc == 4 )
- CALL_EXC( MONGOOSEV_EXCEPTION_ADEL, frame );
-
- else if( exc == 5 )
- CALL_EXC( MONGOOSEV_EXCEPTION_ADES, frame );
-
- else if( exc == 6 )
- CALL_EXC( MONGOOSEV_EXCEPTION_IBE, frame );
-
- else if( exc == 7 )
- CALL_EXC( MONGOOSEV_EXCEPTION_DBE, frame );
-
- else if( exc == 8 )
- CALL_EXC( MONGOOSEV_EXCEPTION_SYSCALL, frame );
-
- else if( exc == 9 )
- CALL_EXC( MONGOOSEV_EXCEPTION_BREAK, frame );
-
- else if( exc == 10 )
- CALL_EXC( MONGOOSEV_EXCEPTION_RI, frame );
-
- else if( exc == 11 )
- CALL_EXC( MONGOOSEV_EXCEPTION_CPU, frame );
-
- else if( exc == 12 )
- CALL_EXC( MONGOOSEV_EXCEPTION_OVERFLOW, frame );
-
- else
- mips_default_exception_code_handler( exc, frame );
-}
-
-
-// eof
-
diff --git a/c/src/lib/libcpu/mips/r46xx/vectorisrs/Makefile.am b/c/src/lib/libcpu/mips/r46xx/vectorisrs/Makefile.am
index 16c4dbef0b..761fa2914c 100644
--- a/c/src/lib/libcpu/mips/r46xx/vectorisrs/Makefile.am
+++ b/c/src/lib/libcpu/mips/r46xx/vectorisrs/Makefile.am
@@ -6,7 +6,7 @@ AUTOMAKE_OPTIONS = foreign 1.4
PGM = $(ARCH)/vectorisrs.rel
-C_FILES = vectorisrs.c
+C_FILES = maxvectors.c vectorisrs.c
vectorisrs_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) $(S_FILES:%.S=$(ARCH)/%.o)
diff --git a/c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c
new file mode 100644
index 0000000000..96feea267a
--- /dev/null
+++ b/c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c
@@ -0,0 +1,20 @@
+/*
+ * This file contains the maximum number of vectors. This can not
+ * be determined without knowing the RTEMS CPU model.
+ *
+ * COPYRIGHT (c) 1989-2000.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * $Id$
+ */
+
+/*
+ * Reserve first 32 for exceptions.
+ */
+
+unsigned int mips_interrupt_number_of_vectors = 32 + 8;
+
diff --git a/c/src/lib/libcpu/mips/r46xx/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/r46xx/vectorisrs/vectorisrs.c
index 31059e7d57..79e52409a7 100644
--- a/c/src/lib/libcpu/mips/r46xx/vectorisrs/vectorisrs.c
+++ b/c/src/lib/libcpu/mips/r46xx/vectorisrs/vectorisrs.c
@@ -5,26 +5,20 @@
#include <rtems.h>
#include <stdlib.h>
-#define mips_get_cause( _cause ) \
- do { \
- asm volatile( "mfc0 %0, $13; nop" : "=r" (_cause) : ); \
- } while (0)
-#define CALL_ISR(_vector) \
+void mips_default_isr( int vector );
+
+#define CALL_ISR(_vector,_frame) \
do { \
if ( _ISR_Vector_table[_vector] ) \
- (_ISR_Vector_table[_vector])(_vector); \
+ (_ISR_Vector_table[_vector])(_vector,_frame); \
else \
- mips_default_exception(_vector); \
+ mips_default_isr(_vector); \
} while (0)
-void mips_default_exception( int vector )
-{
- printk( "Unhandled exception %d\n", vector );
- rtems_fatal_error_occurred(1);
-}
+#include <bspIo.h> /* for printk */
-void mips_vector_isr_handlers( void )
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
{
unsigned int sr;
unsigned int cause;
@@ -41,6 +35,20 @@ void mips_vector_isr_handlers( void )
for ( i=1, mask=0x80 ; i<=8 ; i++, mask >>= 1 ) {
if ( cause & mask )
- CALL_ISR( 8 - i );
+ CALL_ISR( MIPS_EXCEPTION_BASE + 8 - i, frame );
}
}
+
+void mips_default_isr( int vector )
+{
+ unsigned int sr;
+ unsigned int cause;
+
+ mips_get_sr( sr );
+ mips_get_cause( cause );
+
+ printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
+ vector, cause, sr );
+ rtems_fatal_error_occurred(1);
+}
+
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/Makefile.am b/c/src/lib/libcpu/mips/shared/interrupts/Makefile.am
index c1fb455e2f..9ec510a33b 100644
--- a/c/src/lib/libcpu/mips/shared/interrupts/Makefile.am
+++ b/c/src/lib/libcpu/mips/shared/interrupts/Makefile.am
@@ -6,7 +6,7 @@ AUTOMAKE_OPTIONS = foreign 1.4
PGM = $(ARCH)/interrupts.rel
-C_FILES = installisrentries.c maxvectors.c
+C_FILES = installisrentries.c vectorexceptions.c
S_FILES = isr_entries.S
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c b/c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c
new file mode 100644
index 0000000000..f3cf25c593
--- /dev/null
+++ b/c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c
@@ -0,0 +1,115 @@
+/*
+ * Common Code for Vectoring MIPS Exceptions
+ *
+ * The actual decoding of the cause register and vector number assignment
+ * is CPU model specific.
+ *
+ * $Id$
+ */
+
+#include <rtems.h>
+#include <stdlib.h>
+#include "iregdef.h"
+#include "idtcpu.h"
+#include <bspIo.h>
+
+char *cause_strings[32] =
+{
+ /* 0 */ "Int",
+ /* 1 */ "TLB Mods",
+ /* 2 */ "TLB Load",
+ /* 3 */ "TLB Store",
+ /* 4 */ "Address Load",
+ /* 5 */ "Address Store",
+ /* 6 */ "Instruction Bus Error",
+ /* 7 */ "Data Bus Error",
+ /* 9 */ "Syscall",
+ /* 10 */ "Breakpoint",
+ /* 11 */ "Reserved Instruction",
+ /* 12 */ "Coprocessor Unuseable",
+ /* 13 */ "Overflow",
+ /* 14 */ "Trap",
+ /* 15 */ "Instruction Virtual Coherency Error",
+ /* 16 */ "FP Exception",
+ /* 17 */ "Reserved 17",
+ /* 18 */ "Reserved 17",
+ /* 19 */ "Reserved 17",
+ /* 20 */ "Reserved 20",
+ /* 21 */ "Reserved 21",
+ /* 22 */ "Reserved 22",
+ /* 23 */ "Watch",
+ /* 24 */ "Reserved 24",
+ /* 25 */ "Reserved 25",
+ /* 26 */ "Reserved 26",
+ /* 27 */ "Reserved 27",
+ /* 28 */ "Reserved 28",
+ /* 29 */ "Reserved 29",
+ /* 30 */ "Reserved 30",
+ /* 31 */ "Data Virtual Coherency Error"
+};
+
+struct regdef
+{
+ int offset;
+ char *name;
+};
+
+struct regdef dumpregs[]= {
+ { R_RA, "R_RA" }, { R_V0, "R_V0" }, { R_V1, "R_V1" },
+ { R_A0, "R_A0" }, { R_A1, "R_A1" }, { R_A2, "R_A2" },
+ { R_A3, "R_A3" }, { R_T0, "R_T0" }, { R_T1, "R_T1" },
+ { R_T2, "R_T2" }, { R_T3, "R_T3" }, { R_T4, "R_T4" },
+ { R_T5, "R_T5" }, { R_T6, "R_T6" }, { R_T7, "R_T7" },
+ { R_T8, "R_T8" }, { R_MDLO, "R_MDLO" }, { R_MDHI, "R_MDHI" },
+ { R_GP, "R_GP" }, { R_FP, "R_FP" }, { R_AT, "R_AT" },
+ { R_EPC,"R_EPC"}, { -1, NULL }
+};
+
+
+void mips_default_exception_code_handler( int exc, CPU_Interrupt_frame *frame )
+{
+ unsigned int sr;
+ unsigned int cause;
+ int i, j;
+
+ mips_get_sr( sr );
+ mips_get_cause( cause );
+
+ printk( "Unhandled exception %d\n", exc );
+ printk( "sr: 0x%08x cause: 0x%08x --> %s\n", sr, cause,
+ cause_strings[(cause >> 2) &0x1f] );
+
+ for(i=0; dumpregs[i].offset > -1; i++)
+ {
+ printk(" %s", dumpregs[i].name);
+ for(j=0; j< 7-strlen(dumpregs[i].name); j++) printk(" ");
+ printk(" %08X\n", frame->regs[dumpregs[i].offset] );
+ }
+
+ rtems_fatal_error_occurred(1);
+}
+
+#define CALL_EXC(_vector,_frame) \
+ do { \
+ if ( _ISR_Vector_table[_vector] ) \
+ (_ISR_Vector_table[_vector])(_vector,_frame); \
+ else \
+ mips_default_exception_code_handler( _vector, _frame ); \
+ } while(0)
+
+/*
+ * There are constants defined for these but they should basically
+ * all be close to the same set.
+ */
+
+void mips_vector_exceptions( CPU_Interrupt_frame *frame )
+{
+ unsigned32 cause;
+ unsigned32 exc;
+
+ mips_get_cause( cause );
+ exc = (cause >> 2) & 0x1f;
+
+ CALL_EXC( exc, frame );
+}
+
diff --git a/c/src/lib/libcpu/mips/tx39/include/tx3904.h b/c/src/lib/libcpu/mips/tx39/include/tx3904.h
index ac0efae1f6..eb8f60a36e 100644
--- a/c/src/lib/libcpu/mips/tx39/include/tx3904.h
+++ b/c/src/lib/libcpu/mips/tx39/include/tx3904.h
@@ -40,24 +40,25 @@
* Number 16 is "1xxxx" per p. 164 of the TX3904 manual.
*/
-#define TX3904_IRQ_INT1 0
-#define TX3904_IRQ_INT2 1
-#define TX3904_IRQ_INT3 2
-#define TX3904_IRQ_INT4 3
-#define TX3904_IRQ_INT5 4
-#define TX3904_IRQ_INT6 5
-#define TX3904_IRQ_INT7 6
-#define TX3904_IRQ_DMAC3 7
-#define TX3904_IRQ_DMAC2 8
-#define TX3904_IRQ_DMAC1 9
-#define TX3904_IRQ_DMAC0 10
-#define TX3904_IRQ_SIO0 11
-#define TX3904_IRQ_SIO1 12
-#define TX3904_IRQ_TMR0 13
-#define TX3904_IRQ_TMR1 14
-#define TX3904_IRQ_TMR2 15
-#define TX3904_IRQ_INT0 16
-#define TX3904_IRQ_SOFTWARE_1 17
-#define TX3904_IRQ_SOFTWARE_2 18
+#define TX3904_IRQ_INT1 MIPS_INTERRUPT_BASE+0
+#define TX3904_IRQ_INT2 MIPS_INTERRUPT_BASE+1
+#define TX3904_IRQ_INT3 MIPS_INTERRUPT_BASE+2
+#define TX3904_IRQ_INT4 MIPS_INTERRUPT_BASE+3
+#define TX3904_IRQ_INT5 MIPS_INTERRUPT_BASE+4
+#define TX3904_IRQ_INT6 MIPS_INTERRUPT_BASE+5
+#define TX3904_IRQ_INT7 MIPS_INTERRUPT_BASE+6
+#define TX3904_IRQ_DMAC3 MIPS_INTERRUPT_BASE+7
+#define TX3904_IRQ_DMAC2 MIPS_INTERRUPT_BASE+8
+#define TX3904_IRQ_DMAC1 MIPS_INTERRUPT_BASE+9
+#define TX3904_IRQ_DMAC0 MIPS_INTERRUPT_BASE+10
+#define TX3904_IRQ_SIO0 MIPS_INTERRUPT_BASE+11
+#define TX3904_IRQ_SIO1 MIPS_INTERRUPT_BASE+12
+#define TX3904_IRQ_TMR0 MIPS_INTERRUPT_BASE+13
+#define TX3904_IRQ_TMR1 MIPS_INTERRUPT_BASE+14
+#define TX3904_IRQ_TMR2 MIPS_INTERRUPT_BASE+15
+#define TX3904_IRQ_INT0 MIPS_INTERRUPT_BASE+16
+#define TX3904_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+17
+#define TX3904_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+18
+#define TX3904_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+19
#endif
diff --git a/c/src/lib/libcpu/mips/tx39/vectorisrs/Makefile.am b/c/src/lib/libcpu/mips/tx39/vectorisrs/Makefile.am
index 16c4dbef0b..761fa2914c 100644
--- a/c/src/lib/libcpu/mips/tx39/vectorisrs/Makefile.am
+++ b/c/src/lib/libcpu/mips/tx39/vectorisrs/Makefile.am
@@ -6,7 +6,7 @@ AUTOMAKE_OPTIONS = foreign 1.4
PGM = $(ARCH)/vectorisrs.rel
-C_FILES = vectorisrs.c
+C_FILES = maxvectors.c vectorisrs.c
vectorisrs_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) $(S_FILES:%.S=$(ARCH)/%.o)
diff --git a/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c
new file mode 100644
index 0000000000..0f1b649e33
--- /dev/null
+++ b/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c
@@ -0,0 +1,30 @@
+/*
+ * This file contains the maximum number of vectors. This can not
+ * be determined without knowing the RTEMS CPU model.
+ *
+ * COPYRIGHT (c) 1989-2000.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * $Id$
+ */
+
+/*
+ * Reserve first 32 for exceptions.
+ */
+
+/*
+ * The Toshiba TX3904 attaches 4 of the eight interrupt bits to an
+ * on-CPU interrupt controller so that these four bits map to 16
+ * unique interrupts. So you have: 2 software interrupts, an NMI,
+ * and 16 others.
+ */
+
+#include <rtems.h>
+#include <libcpu/tx3904.h>
+
+unsigned int mips_interrupt_number_of_vectors = TX3904_MAXIMUM_VECTORS;
+
diff --git a/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c
index 71b4bb9804..997e7736b6 100644
--- a/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c
+++ b/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c
@@ -1,4 +1,6 @@
/*
+ * TX3904 Interrupt Vectoring
+ *
* $Id$
*/
@@ -6,28 +8,19 @@
#include <stdlib.h>
#include <libcpu/tx3904.h>
-#define mips_get_cause( _cause ) \
- do { \
- asm volatile( "mfc0 %0, $13; nop" : "=r" (_cause) : ); \
- } while (0)
+void mips_default_isr( int vector );
-#define CALL_ISR(_vector) \
+#define CALL_ISR(_vector,_frame) \
do { \
if ( _ISR_Vector_table[_vector] ) \
- (_ISR_Vector_table[_vector])(_vector); \
+ (_ISR_Vector_table[_vector])(_vector,_frame); \
else \
- mips_default_exception(_vector); \
+ mips_default_isr(_vector); \
} while (0)
#include <bspIo.h> /* for printk */
-void mips_default_exception( int vector )
-{
- printk( "Unhandled exception %d\n", vector );
- rtems_fatal_error_occurred(1);
-}
-
-void mips_vector_isr_handlers( void )
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
{
unsigned int sr;
unsigned int cause;
@@ -39,16 +32,30 @@ void mips_vector_isr_handlers( void )
cause >>= CAUSE_IPSHIFT;
if ( cause & 0x80 ) /* IP[5] ==> INT0 */
- CALL_ISR( TX3904_IRQ_INT0 );
+ CALL_ISR( TX3904_IRQ_INT0, frame );
if ( cause & 0x40 ) { /* (IP[4] == 1) ==> IP[0-3] are valid */
unsigned int v = (cause >> 2) & 0x0f;
- CALL_ISR( v );
+ CALL_ISR( MIPS_INTERRUPT_BASE + v, frame );
}
if ( cause & 0x02 ) /* SW[0] */
- CALL_ISR( TX3904_IRQ_SOFTWARE_1 );
+ CALL_ISR( TX3904_IRQ_SOFTWARE_1, frame );
if ( cause & 0x01 ) /* IP[1] */
- CALL_ISR( TX3904_IRQ_SOFTWARE_2 );
+ CALL_ISR( TX3904_IRQ_SOFTWARE_2, frame );
}
+
+void mips_default_isr( int vector )
+{
+ unsigned int sr;
+ unsigned int cause;
+
+ mips_get_sr( sr );
+ mips_get_cause( cause );
+
+ printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
+ vector, cause, sr );
+ rtems_fatal_error_occurred(1);
+}
+