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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-03-09 16:45:56 +0100 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-03-13 08:05:39 +0100 |
commit | b6755affc05466a49e684c316ea6e6f00c21c370 (patch) | |
tree | 25f341de3fb53195fe8341fb9e5779eed63e1db5 /c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S | |
parent | bsps/mips: Remove Mongoose-V README (diff) | |
download | rtems-b6755affc05466a49e684c316ea6e6f00c21c370.tar.bz2 |
bsps/mips: Move libcpu content to bsps
This patch is a part of the BSP source reorganization.
Update #3285.
Diffstat (limited to 'c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S')
-rw-r--r-- | c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S | 106 |
1 files changed, 0 insertions, 106 deletions
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S deleted file mode 100644 index 2e3791cab2..0000000000 --- a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file contains the raw entry points for the exceptions. - * - * COPYRIGHT (c) 1989-2000. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <rtems/asm.h> -#include <rtems/mips/iregdef.h> -#include <rtems/mips/idtcpu.h> - -/* - * MIPS ISA Level 1 entries - */ - -#if __mips == 1 - -FRAME(exc_norm_code,sp,0,ra) - la k0, _ISR_Handler /* generic external int hndlr */ - j k0 - nop -ENDFRAME(exc_norm_code) - -FRAME(exc_dbg_code,sp,0,ra) - la k0, _DBG_Handler /* debug interrupt */ - j k0 - nop -ENDFRAME(exc_dbg_code) - -/* XXX this is dependent on IDT/SIM and needs to be addressed */ -FRAME(exc_utlb_code,sp,0,ra) - la k0, (R_VEC+((48)*8)) - j k0 - nop -ENDFRAME(exc_utlb_code) - -/* - * MIPS ISA Level 32 - * XXX Again, reliance on SIM. Not good.?????????? - */ -#elif __mips == 32 -FRAME(exc_tlb_code,sp,0,ra) - la k0, _ISR_Handler - j k0 - nop -ENDFRAME(exc_tlb_code) - -FRAME(exc_xtlb_code,sp,0,ra) - la k0, _ISR_Handler - j k0 - nop - -ENDFRAME(exc_xtlb_code) - -FRAME(exc_cache_code,sp,0,ra) - la k0, _ISR_Handler - j k0 - nop -ENDFRAME(exc_cache_code) - -FRAME(exc_norm_code,sp,0,ra) - la k0, _ISR_Handler /* generic external int hndlr */ - j k0 - nop -ENDFRAME(exc_norm_code) - -/* - * MIPS ISA Level 3 - * XXX Again, reliance on SIM. Not good. - */ -#elif __mips == 3 - -FRAME(exc_tlb_code,sp,0,ra) - la k0, (R_VEC+((112)*8)) /* R4000 Sim location */ - j k0 - nop -ENDFRAME(exc_tlb_code) - -FRAME(exc_xtlb_code,sp,0,ra) - la k0, (R_VEC+((112)*8)) /* R4000 Sim location */ - j k0 - nop - -ENDFRAME(exc_xtlb_code) - -FRAME(exc_cache_code,sp,0,ra) - la k0, (R_VEC+((112)*8)) /* R4000 Sim location */ - j k0 - nop -ENDFRAME(exc_cache_code) - -FRAME(exc_norm_code,sp,0,ra) - la k0, _ISR_Handler /* generic external int hndlr */ - j k0 - nop -ENDFRAME(exc_norm_code) - -#else - -#error "isr_entries.S: ISA support problem" - -#endif |