bsps/mips: Move libcpu content to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

3 files changed, 0 insertions, 155 deletions

diff --git a/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c b/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c
deleted file mode 100644
index 9380a26f37..0000000000
--- a/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c
+++ /dev/null
@@ -1,29 +0,0 @@
-#include <rtems.h>
-#include <rtems/mips/idtcpu.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include <libcpu/isr_entries.h>
-
-void mips_install_isr_entries( void )
-{
-#if __mips == 1
-  memcpy( (void *)UT_VEC, exc_utlb_code, 40 );  /* utlbmiss vector */
-  memcpy( (void *)DB_VEC, exc_dbg_code, 40 );
-  memcpy( (void *)E_VEC, exc_norm_code, 40 );   /* exception vevtor */
-
-#elif __mips == 32
-  memcpy( (void *)T_VEC, exc_tlb_code, 40 );    /* tlbmiss vector */
-  memcpy( (void *)X_VEC, exc_xtlb_code, 40 );   /* xtlbmiss vector */
-  memcpy( (void *)C_VEC, exc_cache_code, 40 );  /* cache error vector */
-  memcpy( (void *)E_VEC, exc_norm_code, 40 );   /* exception vector */
-
-#elif __mips == 3
-  memcpy( (void *)T_VEC, exc_tlb_code, 40 );    /* tlbmiss vector */
-  memcpy( (void *)X_VEC, exc_xtlb_code, 40 );   /* xtlbmiss vector */
-  memcpy( (void *)C_VEC, exc_cache_code, 40 );  /* cache error vector */
-  memcpy( (void *)E_VEC, exc_norm_code, 40 );   /* exception vector */
-#endif
-
-  rtems_cache_flush_entire_data();
-}
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/interruptmask.c b/c/src/lib/libcpu/mips/shared/interrupts/interruptmask.c
deleted file mode 100644
index 9f2b679a77..0000000000
--- a/c/src/lib/libcpu/mips/shared/interrupts/interruptmask.c
+++ /dev/null
@@ -1,20 +0,0 @@
-#include <rtems.h>
-
-/*
- *  This function returns a mask value which is used to select the bits
- *  in the processor status register that can be set to enable interrupts.
- *  The mask value should not include the 2 software interrupt enable bits.
- */
-
-uint32_t mips_interrupt_mask( void )
-{
-	uint32_t interrupt_mask;
-
-#ifdef TX49
-	interrupt_mask = 0x00000400;			/* Toshiba TX49 processors have a non-standard interrupt mask */
-#else
-	interrupt_mask = 0x0000fc00;
-#endif
-
-	return(interrupt_mask);
-}
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S
deleted file mode 100644
index 2e3791cab2..0000000000
--- a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- *  This file contains the raw entry points for the exceptions.
- *
- *  COPYRIGHT (c) 1989-2000.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#include <rtems/asm.h>
-#include <rtems/mips/iregdef.h>
-#include <rtems/mips/idtcpu.h>
-
-/*
- *  MIPS ISA Level 1 entries
- */
-
-#if __mips == 1
-
-FRAME(exc_norm_code,sp,0,ra)
-	la	k0, _ISR_Handler /* generic external int hndlr */
-	j	k0
-	nop
-ENDFRAME(exc_norm_code)
-
-FRAME(exc_dbg_code,sp,0,ra)
-        la      k0, _DBG_Handler /* debug interrupt */
-        j       k0
-	nop
-ENDFRAME(exc_dbg_code)
-
-/* XXX this is dependent on IDT/SIM and needs to be addressed */
-FRAME(exc_utlb_code,sp,0,ra)
-        la      k0, (R_VEC+((48)*8))
-        j       k0
-	nop
-ENDFRAME(exc_utlb_code)
-
-/*
- * MIPS ISA Level 32
- * XXX Again, reliance on SIM. Not good.??????????
- */
-#elif __mips == 32
-FRAME(exc_tlb_code,sp,0,ra)
-        la      k0, _ISR_Handler
-        j       k0
-	nop
-ENDFRAME(exc_tlb_code)
-
-FRAME(exc_xtlb_code,sp,0,ra)
-        la      k0, _ISR_Handler
-        j       k0
-	nop
-
-ENDFRAME(exc_xtlb_code)
-
-FRAME(exc_cache_code,sp,0,ra)
-        la      k0, _ISR_Handler
-        j       k0
-	nop
-ENDFRAME(exc_cache_code)
-
-FRAME(exc_norm_code,sp,0,ra)
-	la	k0, _ISR_Handler /* generic external int hndlr */
-	j	k0
-	nop
-ENDFRAME(exc_norm_code)
-
-/*
- * MIPS ISA Level 3
- * XXX Again, reliance on SIM. Not good.
- */
-#elif __mips == 3
-
-FRAME(exc_tlb_code,sp,0,ra)
-        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
-        j       k0
-	nop
-ENDFRAME(exc_tlb_code)
-
-FRAME(exc_xtlb_code,sp,0,ra)
-        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
-        j       k0
-	nop
-
-ENDFRAME(exc_xtlb_code)
-
-FRAME(exc_cache_code,sp,0,ra)
-        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
-        j       k0
-	nop
-ENDFRAME(exc_cache_code)
-
-FRAME(exc_norm_code,sp,0,ra)
-	la	k0, _ISR_Handler /* generic external int hndlr */
-	j	k0
-	nop
-ENDFRAME(exc_norm_code)
-
-#else
-
-#error "isr_entries.S: ISA support problem"
-
-#endif