Whitespace removal.

6 files changed, 106 insertions, 106 deletions

diff --git a/c/src/lib/libcpu/i386/cpu.h b/c/src/lib/libcpu/i386/cpu.h
index ba524ab941..ec15f952da 100644
--- a/c/src/lib/libcpu/i386/cpu.h
+++ b/c/src/lib/libcpu/i386/cpu.h
@@ -1,5 +1,5 @@
 /*
- * cpu.h  - This file contains definitions for data structure related 
+ * cpu.h  - This file contains definitions for data structure related
  *          to Intel system programming. More information can be found
  *	    on Intel site and more precisely in the following book :
  *
@@ -147,7 +147,7 @@ do { register unsigned short __port  = _port; \
    } while (0)
 
 /*
- * Type definition for raw interrupts. 
+ * Type definition for raw interrupts.
  */
 
 typedef unsigned char  rtems_vector_offset;
@@ -167,16 +167,16 @@ typedef struct __rtems_raw_irq_connect_data__{
    * libcpu library, this library should have no knowledge of
    * board specific hardware to manage interrupts and thus the
    * "on" routine must enable the irq both at device and PIC level.
-   * 
+   *
    */
-    rtems_raw_irq_enable	on;	
+    rtems_raw_irq_enable	on;
   /*
    * function for disabling raw interrupts. In order to be consistent
    * with the fact that the raw connexion can defined in the
    * libcpu library, this library should have no knowledge of
    * board specific hardware to manage interrupts and thus the
    * "on" routine must disable the irq both at device and PIC level.
-   * 
+   *
    */
   rtems_raw_irq_disable		off;
   /*
@@ -204,7 +204,7 @@ typedef struct {
 
 /*
  * C callable function enabling to get handler currently connected to a vector
- * 
+ *
  */
 rtems_raw_irq_hdl get_hdl_from_vector(rtems_vector_offset);
 
@@ -335,7 +335,7 @@ typedef union {
   page_table_bits	bits;
   unsigned int		table_entry;
 } page_table_entry;
- 
+
 /*
  * definitions related to page table entry
  */
@@ -371,12 +371,12 @@ extern void 	_CPU_disable_cache();
 extern void 	_CPU_enable_cache();
 extern int 	_CPU_map_phys_address
                       (void **mappedAddress, void *physAddress,
-		       int size, int flag); 
-extern int 	_CPU_unmap_virt_address (void *mappedAddress, int size); 
+		       int size, int flag);
+extern int 	_CPU_unmap_virt_address (void *mappedAddress, int size);
 extern int 	_CPU_change_memory_mapping_attribute
                          (void **newAddress, void *mappedAddress,
 			  unsigned int size, unsigned int flag);
-extern int  	_CPU_display_memory_attribute(); 
+extern int  	_CPU_display_memory_attribute();
 
 # endif /* ASM */
 
diff --git a/c/src/lib/libcpu/i386/cpuModel.S b/c/src/lib/libcpu/i386/cpuModel.S
index 74fffd31d2..263f824004 100644
--- a/c/src/lib/libcpu/i386/cpuModel.S
+++ b/c/src/lib/libcpu/i386/cpuModel.S
@@ -5,15 +5,15 @@
  *
  *  Intel also provides public similar code in the book
  *  called :
- *	
+ *
  *	Pentium Processor Family
  *		Developer Family
  *	Volume  3 :	Architecture and Programming Manual
  *
  * At the following place :
- *	
+ *
  *	Chapter 5 :	Feature determination
- *	Chapter 25:	CPUID instruction	
+ *	Chapter 25:	CPUID instruction
  *
  *  COPYRIGHT (c) 1998 valette@crf.canon.fr
  *
@@ -28,100 +28,100 @@
 #include <rtems/score/registers.h>
 
 BEGIN_CODE
-	PUBLIC(checkCPUtypeSetCr0); 
-/* 
- * check Processor type: 386, 486, 6x86(L) or CPUID capable processor 
+	PUBLIC(checkCPUtypeSetCr0);
+/*
+ * check Processor type: 386, 486, 6x86(L) or CPUID capable processor
  */
 
 SYM (checkCPUtypeSetCr0):
 	/*
-	 *  Assume 386 for now 
+	 *  Assume 386 for now
 	 */
-	movl $3, SYM (x86) 
+	movl $3, SYM (x86)
 	/*
 	 * Start using the EFLAGS AC bit determination method described in
 	 * the book mentioned above page 5.1. If this bit can be set we
 	 * have a 486 or above.
 	 */
 	pushfl				/* save EFLAGS			*/
-	
+
 	pushfl				/* Get EFLAGS in EAX		*/
 	popl eax
-	
+
 	movl eax,ecx			/* save original EFLAGS in ECX	*/
 	xorl $EFLAGS_ALIGN_CHECK,eax	/* flip AC bit in EAX		*/
 	pushl eax			/* set EAX as EFLAGS		*/
-	popfl			
+	popfl
 	pushfl				/* Get new EFLAGS in EAX	*/
 	popl eax
-	
+
 	xorl ecx,eax			/* check if AC bit changed	*/
-	andl $EFLAGS_ALIGN_CHECK,eax	
+	andl $EFLAGS_ALIGN_CHECK,eax
 	je is386			/* If not : we have a 386	*/
 	/*
-	 *  Assume 486 for now 
+	 *  Assume 486 for now
 	 */
 	movl $4,SYM (x86)
 	movl ecx,eax			/* Restore orig EFLAGS in EAX	*/
 	xorl $EFLAGS_ID,eax		/* flip  ID flag		*/
 	pushl eax			/* set EAX as EFLAGS		*/
-	popfl				
+	popfl
 	pushfl				/* Get new EFLAGS in EAX	*/
-	popl eax	
-			
+	popl eax
+
 	xorl ecx,eax			/* check if ID bit changed	*/
 	andl $EFLAGS_ID,eax
 
-	/* 
+	/*
 	 * if we are on a straight 486DX,
 	 * SX, or 487SX we can't change it
-	 * OTOH 6x86MXs and MIIs check OK 
+	 * OTOH 6x86MXs and MIIs check OK
 	 * Also if we are on a Cyrix 6x86(L)
 	 */
 	je is486x
 
-isnew:	
+isnew:
 	/*
 	 * restore original EFLAGS
 	 */
 	popfl
 	incl SYM(have_cpuid)	/* we have CPUID instruction */
 
-	/* use it to get :	
+	/* use it to get :
 	 *	processor type,
 	 *	processor model,
 	 *	processor mask,
 	 * by using it with EAX = 1
 	 */
-	movl $1, eax		
-	cpuid			
+	movl $1, eax
+	cpuid
 	movl ecx,SYM(x86_capability_x) /* store ecx feature flags */
 
 	movb al, cl		/* save reg for future use */
-	
+
 	andb $0x0f,ah		/* mask processor family   */
 	movb ah,SYM (x86)	/* put result in x86 var   */
-	
+
 	andb $0xf0, al		/* get model		   */
 	shrb $4, al
 	movb al,SYM (x86_model) /* store it in x86_model   */
-	
+
 	andb $0x0f, cl		/* get mask revision	   */
 	movb cl,SYM (x86_mask)  /* store it in x86_mask	   */
-	
+
 	movl edx,SYM(x86_capability)	/* store feature flags in x86_capability */
-	
+
 	/* get vendor info by using CPUID with EXA = 0 */
-	xorl eax, eax		
+	xorl eax, eax
 	cpuid
 
 	/*
 	 * store results contained in ebx, edx, ecx in
 	 * x86_vendor_id variable.
 	 */
-	movl ebx,SYM(x86_vendor_id)	
-	movl edx,SYM(x86_vendor_id)+4	
-	movl ecx,SYM(x86_vendor_id)+8	
+	movl ebx,SYM(x86_vendor_id)
+	movl edx,SYM(x86_vendor_id)+4
+	movl ecx,SYM(x86_vendor_id)+8
 
 	movl cr0,eax		/* 486+ */
 	andl $(CR0_PAGING | CR0_PROTECTION_ENABLE | CR0_EXTENSION_TYPE), eax
@@ -180,7 +180,7 @@ is486x:	xor ax,ax
 
         getCx86($0xfe)          /* DIR0 : let's check this is a 6x86(L) */
         andb $0xf0,al		/* should be 3xh */
-	cmpb $0x30,al		
+	cmpb $0x30,al
 	jne n6x86
         getCx86($0xe9)          /* CCR5 : we reset the SLOP bit */
         andb $0xfd,al		/* so that udelay calculation */
@@ -206,7 +206,7 @@ is386:				/* restore original EFLAGS */
 2:	movl eax,cr0
 	call check_x87
 	ret
-	
+
 
 /*
  * We depend on ET to be correct. This checks for 287/387.
@@ -228,7 +228,7 @@ check_x87:
 	ret
 
 END_CODE
-	
+
 BEGIN_DATA
 	PUBLIC(x86)
 	PUBLIC(have_cpuid)
@@ -239,20 +239,20 @@ BEGIN_DATA
 	PUBLIC(x86_vendor_id)
 	PUBLIC(hard_math)
 
-SYM(x86):	
+SYM(x86):
 	.byte 0
-SYM(have_cpuid):	
+SYM(have_cpuid):
 	.long 0
-SYM(x86_model):	
+SYM(x86_model):
 	.byte 0
-SYM(x86_mask):	
+SYM(x86_mask):
 	.byte 0
-SYM(x86_capability):	
-	.long 0		
-SYM(x86_capability_x):	
-	.long 0		
-SYM(x86_vendor_id):	
+SYM(x86_capability):
+	.long 0
+SYM(x86_capability_x):
+	.long 0
+SYM(x86_vendor_id):
 	.zero 13
-SYM(hard_math):	
+SYM(hard_math):
 	.byte 0
 END_DATA
diff --git a/c/src/lib/libcpu/i386/cpuModel.h b/c/src/lib/libcpu/i386/cpuModel.h
index cb4a4daea4..f11062a341 100644
--- a/c/src/lib/libcpu/i386/cpuModel.h
+++ b/c/src/lib/libcpu/i386/cpuModel.h
@@ -27,7 +27,7 @@ extern char x86_mask;
 extern int x86_capability;      /* cpuid:EDX */
 extern int x86_capability_x;    /* cpuid:ECX */
 extern char x86_vendor_id[13];
-extern int have_cpuid;  
+extern int have_cpuid;
 extern unsigned char Cx86_step; /* cyrix processor identification */
 
 extern void printCpuInfo(); /* Display this information on console in ascii form */
diff --git a/c/src/lib/libcpu/i386/displayCpu.c b/c/src/lib/libcpu/i386/displayCpu.c
index 97ca5ddb8b..b0f88c9312 100644
--- a/c/src/lib/libcpu/i386/displayCpu.c
+++ b/c/src/lib/libcpu/i386/displayCpu.c
@@ -134,7 +134,7 @@ static const char * AMDmodel(void)
 {
 	const char *p=NULL;
 	int i;
-	
+
 	if (x86_model < 16)
 		for (i=0; i<sizeof(amd_models)/sizeof(struct cpu_model_info); i++)
 			if (amd_models[i].x86 == x86) {
@@ -187,14 +187,14 @@ void printCpuInfo(void)
 	"16",  "17", "18", "19", "20", "21", "22", "23"
 	"24",  "25", "26", "27", "28", "29", "30", "31"
   };
-         
-  printk("cpu         : %c86\n", x86+'0'); 
+
+  printk("cpu         : %c86\n", x86+'0');
   printk("model       : %s\n",
 	 have_cpuid ? getmodel(x86, x86_model) : "unknown");
   if (x86_vendor_id [0] == '\0')
     strcpy(x86_vendor_id, "unknown");
   printk("vendor_id   : %s\n", x86_vendor_id);
-        
+
   if (x86_mask)
     if (strncmp(x86_vendor_id, "Cyrix", 5) != 0) {
       printk("stepping    : %d\n", x86_mask);
@@ -204,7 +204,7 @@ void printCpuInfo(void)
     }
   else
     printk("stepping    : unknown\n");
-        
+
   printk("fpu         : %s\n", (hard_math ? "yes" : "no"));
   printk("cpuid       : %s\n", (have_cpuid ? "yes" : "no"));
   printk("flags       :");
diff --git a/c/src/lib/libcpu/i386/idtr.S b/c/src/lib/libcpu/i386/idtr.S
index 09a1121765..125b545b96 100644
--- a/c/src/lib/libcpu/i386/idtr.S
+++ b/c/src/lib/libcpu/i386/idtr.S
@@ -26,7 +26,7 @@ PUBLIC (i386_get_info_from_IDTR)
 PUBLIC (i386_set_IDTR)
 PUBLIC (i386_get_info_from_GDTR)
 PUBLIC (i386_set_GDTR)
-		
+
 SYM (i386_get_info_from_IDTR):
 	movl	4(esp), ecx	    /* get location where table address */
                                     /*    must be stored */
@@ -52,7 +52,7 @@ SYM (i386_get_info_from_IDTR):
 extern void i386_set_IDTR (interrupt_gate_descriptor* table,
 		           unsigned limit);
  */
-SYM (i386_set_IDTR):			
+SYM (i386_set_IDTR):
 
 	leal	4(esp), edx	    /* load in edx address of input */
                                     /*    parameter "table" */
@@ -73,8 +73,8 @@ SYM (i386_set_IDTR):
 extern void i386_get_info_from_GDTR (segment_descriptors** table,
 				     unsigned* limit);
  */
-	
-SYM (i386_get_info_from_GDTR):	
+
+SYM (i386_get_info_from_GDTR):
 	movl	4(esp), ecx	    /* get location where table address */
                                     /*    must be stored */
 	movl	8(esp), edx	    /* get location table size must be stored */
@@ -97,7 +97,7 @@ SYM (i386_get_info_from_GDTR):
  * Must be called with interrupts masked at processor level!!!.
  *   extern void i386_set_GDTR (segment_descriptors*, unsigned limit);
  */
-SYM (i386_set_GDTR):			
+SYM (i386_set_GDTR):
 
 	leal	4(esp), edx	    /* load in edx address of input */
                                     /*   parameter "table" */
@@ -111,7 +111,7 @@ SYM (i386_set_GDTR):
 	lgdt	(edx)
 
 	ret
-		
+
 END_CODE
 
 END
diff --git a/c/src/lib/libcpu/i386/page.c b/c/src/lib/libcpu/i386/page.c
index b27dc2b920..45d9aaadd2 100644
--- a/c/src/lib/libcpu/i386/page.c
+++ b/c/src/lib/libcpu/i386/page.c
@@ -80,22 +80,22 @@ int init_paging(void)
   page_table *pageTable;
   unsigned int physPage;
   int nbTables=0;
-  
+
   /*
    * rtemsFreeMemStart is the last valid 32-bits address
    * so the size is rtemsFreeMemStart + 4
    */
   memorySize = rtemsFreeMemStart + 4;
-  
+
   nbPages = ( (memorySize - 1) / PG_SIZE ) + 1;
   nbTables = ( (memorySize - 1) / FOUR_MB ) + 2;
 
   /* allocate 1 page more to page alignement */
-  Tables = (char *)malloc( (nbTables + 1)*sizeof(page_table) ); 
+  Tables = (char *)malloc( (nbTables + 1)*sizeof(page_table) );
   if ( Tables == NULL ){
     return -1; /*unable to allocate memory */
   }
-  
+
   /* 4K-page alignement */
   Tables += (PG_SIZE - (int)Tables) & 0xFFF;
 
@@ -139,7 +139,7 @@ int init_paging(void)
       directoryEntry ++;
       pageTable ++;
     }
-      
+
     nbInitPages++;
   }
 
@@ -149,8 +149,8 @@ int init_paging(void)
 
   i386_set_cr3( regCr3.i );
 
-  _CPU_enable_cache();  
-  _CPU_enable_paging();  
+  _CPU_enable_cache();
+  _CPU_enable_paging();
 
   return 0;
 }
@@ -189,13 +189,13 @@ int _CPU_map_phys_address(
   int    size,
   int    flag
 )
-{ 
+{
   page_table *localPageTable;
   unsigned int lastAddress, countAddress;
   char *Tables;
   linear_address virtualAddress;
   unsigned char pagingWasEnabled;
-  
+
   pagingWasEnabled = 0;
 
   if (_CPU_is_paging_enabled()){
@@ -215,7 +215,7 @@ int _CPU_map_phys_address(
     /* Need to allocate a new page table */
     if (pageDirectory->pageDirEntry[directoryEntry].bits.page_frame_address == 0){
       /* We allocate 2 pages to perform 4k-page alignement */
-      Tables = (char *)malloc(2*sizeof(page_table)); 
+      Tables = (char *)malloc(2*sizeof(page_table));
       if ( Tables == NULL ){
 	if (pagingWasEnabled)
 	  _CPU_enable_paging();
@@ -225,7 +225,7 @@ int _CPU_map_phys_address(
       Tables += (PG_SIZE - (int)Tables) & 0xFFF;
 
       /* Reset Table */
-      memset( Tables, 0, sizeof(page_table) );      
+      memset( Tables, 0, sizeof(page_table) );
       pageDirectory->pageDirEntry[directoryEntry].bits.page_frame_address =
 	(unsigned int)Tables >> 12;
       pageDirectory->pageDirEntry[directoryEntry].bits.available      = 0;
@@ -237,7 +237,7 @@ int _CPU_map_phys_address(
       pageDirectory->pageDirEntry[directoryEntry].bits.writable       = 1;
       pageDirectory->pageDirEntry[directoryEntry].bits.present        = 1;
     }
-      
+
 
     localPageTable = (page_table *)(pageDirectory->
 				    pageDirEntry[directoryEntry].bits.
@@ -264,7 +264,7 @@ int _CPU_map_phys_address(
 
     countAddress += PG_SIZE;
     tableEntry++;
-    if (tableEntry >= MAX_ENTRY){      
+    if (tableEntry >= MAX_ENTRY){
       tableEntry = 0;
       directoryEntry++;
     }
@@ -285,7 +285,7 @@ static void Paging_Table_Compress(void)
 {
   unsigned int dirCount, pageCount;
   page_table *localPageTable;
-  
+
   if (tableEntry == 0){
     dirCount  = directoryEntry - 1;
     pageCount = MAX_ENTRY - 1;
@@ -294,7 +294,7 @@ static void Paging_Table_Compress(void)
     dirCount  = directoryEntry;
     pageCount = tableEntry - 1;
   }
-    
+
   while (1){
 
     localPageTable = (page_table *)(pageDirectory->
@@ -303,7 +303,7 @@ static void Paging_Table_Compress(void)
 
     if (localPageTable->pageTableEntry[pageCount].bits.present == 1){
       pageCount++;
-      if (pageCount >= MAX_ENTRY){      
+      if (pageCount >= MAX_ENTRY){
 	pageCount = 0;
 	dirCount++;
       }
@@ -312,13 +312,13 @@ static void Paging_Table_Compress(void)
 
 
     if (pageCount == 0) {
-      if (dirCount == 0){	
+      if (dirCount == 0){
 	break;
       }
       else {
 	pageCount = MAX_ENTRY - 1;
 	dirCount-- ;
-      }	
+      }
     }
     else
       pageCount-- ;
@@ -327,8 +327,8 @@ static void Paging_Table_Compress(void)
   directoryEntry = dirCount;
   tableEntry = pageCount;
 }
-      
-  
+
+
 /*
  * Unmap the virtual address from the tables
  * (we do not deallocate the table already allocated)
@@ -338,14 +338,14 @@ int _CPU_unmap_virt_address(
   void *mappedAddress,
   int   size
 )
-{ 
+{
 
   linear_address linearAddr;
   page_table *localPageTable;
   unsigned int lastAddr ;
   unsigned int dirCount ;
   unsigned char pagingWasEnabled;
-  
+
   pagingWasEnabled = 0;
 
   if (_CPU_is_paging_enabled()){
@@ -371,15 +371,15 @@ int _CPU_unmap_virt_address(
     localPageTable = (page_table *)(pageDirectory->
 				    pageDirEntry[linearAddr.bits.directory].bits.
 				    page_frame_address << 12);
-    
+
     if (localPageTable->pageTableEntry[linearAddr.bits.page].bits.present == 0){
       if (pagingWasEnabled)
 	_CPU_enable_paging();
       return -1;
     }
-  
-    localPageTable->pageTableEntry[linearAddr.bits.page].bits.present = 0;    
-    
+
+    localPageTable->pageTableEntry[linearAddr.bits.page].bits.present = 0;
+
     linearAddr.address += PG_SIZE ;
   }
   Paging_Table_Compress();
@@ -390,7 +390,7 @@ int _CPU_unmap_virt_address(
 }
 
 /*
- * Modify the flags PRESENT, WRITABLE, USER, WRITE_TROUGH, CACHE_DISABLE 
+ * Modify the flags PRESENT, WRITABLE, USER, WRITE_TROUGH, CACHE_DISABLE
  * of the page's descriptor.
  */
 
@@ -400,20 +400,20 @@ int _CPU_change_memory_mapping_attribute(
   unsigned int   size,
   unsigned int   flag
 )
-{ 
+{
 
   linear_address linearAddr;
   page_table *localPageTable;
   unsigned int lastAddr ;
   unsigned char pagingWasEnabled;
-  
+
   pagingWasEnabled = 0;
 
   if (_CPU_is_paging_enabled()){
     pagingWasEnabled = 1;
     _CPU_disable_paging();
   }
-  
+
   linearAddr.address  = (unsigned int)mappedAddress;
   lastAddr = (unsigned int)mappedAddress + (size - 1);
 
@@ -430,18 +430,18 @@ int _CPU_change_memory_mapping_attribute(
     localPageTable = (page_table *)(pageDirectory->
 				    pageDirEntry[linearAddr.bits.directory].bits.
 				    page_frame_address << 12);
-    
+
     if (localPageTable->pageTableEntry[linearAddr.bits.page].bits.present == 0){
       if (pagingWasEnabled)
 	_CPU_enable_paging();
       return -1;
     }
-  
+
     localPageTable->pageTableEntry[linearAddr.bits.page].table_entry &= ~MASK_FLAGS ;
     localPageTable->pageTableEntry[linearAddr.bits.page].table_entry |= flag ;
-    
+
     linearAddr.address += PG_SIZE ;
-  }  
+  }
 
   if (newAddress != NULL)
     *newAddress = mappedAddress ;
@@ -460,7 +460,7 @@ int _CPU_change_memory_mapping_attribute(
 #include <rtems/bspIo.h>
 
 int  _CPU_display_memory_attribute(void)
-{ 
+{
   unsigned int dirCount, pageCount;
   cr0 regCr0;
   page_table *localPageTable;
@@ -468,9 +468,9 @@ int  _CPU_display_memory_attribute(void)
   unsigned int prevPresent;
   unsigned int maxPage;
   unsigned char pagingWasEnabled;
-  
+
   regCr0.i = i386_get_cr0();
-  
+
   printk("\n\n********* MEMORY CACHE CONFIGURATION *****\n");
 
   printk("CR0 -> paging           : %s\n",(regCr0.cr0.paging ? "ENABLE ":"DISABLE"));
@@ -478,10 +478,10 @@ int  _CPU_display_memory_attribute(void)
 
   if (regCr0.cr0.paging == 0)
     return 0;
-  
+
   prevPresent = 0;
   prevCache   = 1;
-  
+
   pagingWasEnabled = 0;
 
   if (_CPU_is_paging_enabled()){