Patch from John Cotton <john.cotton@nrc.ca>, Charles-Antoine Gauthier

<charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart
<Darlene.Stewart@nrc.ca> to add support for a number of very
significant things:

  + BSPs for many variations on the Motorola MBX8xx board series
  + Cache Manager including initial support for m68040
    and PowerPC
  + Rework of mpc8xx libcpu code so all mpc8xx CPUs now use
    same code base.
  + Rework of eth_comm BSP to utiltize above.

John reports this works on the 821 and 860

1 files changed, 2 insertions, 28 deletions

diff --git a/c/src/lib/libcpu/i386/page.c b/c/src/lib/libcpu/i386/page.c
index fc28b7687a..e5cceeed23 100644
--- a/c/src/lib/libcpu/i386/page.c
+++ b/c/src/lib/libcpu/i386/page.c
@@ -45,7 +45,7 @@ extern rtems_unsigned32 rtemsFreeMemStart;
 void _CPU_disable_paging() {
   cr0 regCr0;
 
-  flush_cache();
+  rtems_flush_entire_data_cache();
   regCr0.i = i386_get_cr0();
   regCr0.cr0.paging = 0;
   i386_set_cr0( regCr0.i );
@@ -60,7 +60,7 @@ void _CPU_enable_paging() {
   regCr0.i = i386_get_cr0();
   regCr0.cr0.paging = 1;
   i386_set_cr0( regCr0.i );
-  flush_cache();
+  rtems_flush_entire_data_cache();
 }
 
 
@@ -154,32 +154,6 @@ int init_paging() {
 }
 
 /*
- * Disable the entire cache
- */
-void _CPU_disable_cache() {
-  cr0 regCr0;
-
-  regCr0.i = i386_get_cr0();
-  regCr0.cr0.page_level_cache_disable = 1;
-  regCr0.cr0.no_write_through = 1;
-  i386_set_cr0( regCr0.i );
-  flush_cache();
-}
-
-/*
- * Disable the entire cache
- */
-void _CPU_enable_cache() {
-  cr0 regCr0;
-
-  regCr0.i = i386_get_cr0();
-  regCr0.cr0.page_level_cache_disable = 0;
-  regCr0.cr0.no_write_through = 0;
-  i386_set_cr0( regCr0.i );
-  /*flush_cache();*/
-}
-
-/*
  * Is cache enable
  */
 int  _CPU_is_cache_enabled() {