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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-06-12 19:57:02 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-06-12 19:57:02 +0000 |
commit | 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52 (patch) | |
tree | 9253f150814c99167239f7c2cc850cdd9d92c003 /c/src/lib/libcpu/i386 | |
parent | Ensure that when -msoft-float is specified for multilib builds, that (diff) | |
download | rtems-8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52.tar.bz2 |
Patch from John Cotton <john.cotton@nrc.ca>, Charles-Antoine Gauthier
<charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart
<Darlene.Stewart@nrc.ca> to add support for a number of very
significant things:
+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040
and PowerPC
+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use
same code base.
+ Rework of eth_comm BSP to utiltize above.
John reports this works on the 821 and 860
Diffstat (limited to 'c/src/lib/libcpu/i386')
-rw-r--r-- | c/src/lib/libcpu/i386/cpu.h | 47 | ||||
-rw-r--r-- | c/src/lib/libcpu/i386/page.c | 30 |
2 files changed, 2 insertions, 75 deletions
diff --git a/c/src/lib/libcpu/i386/cpu.h b/c/src/lib/libcpu/i386/cpu.h index 27e5f1cb88..791173f15b 100644 --- a/c/src/lib/libcpu/i386/cpu.h +++ b/c/src/lib/libcpu/i386/cpu.h @@ -133,47 +133,6 @@ static inline unsigned short i386_get_gs() } /* - * Added for pagination management - */ - -static inline unsigned int i386_get_cr0() -{ - register unsigned int segment = 0; - - asm volatile ( "movl %%cr0,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static inline void i386_set_cr0(unsigned int segment) -{ - asm volatile ( "movl %0,%%cr0" : "=r" (segment) : "0" (segment) ); -} - -static inline unsigned int i386_get_cr2() -{ - register unsigned int segment = 0; - - asm volatile ( "movl %%cr2,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static inline unsigned int i386_get_cr3() -{ - register unsigned int segment = 0; - - asm volatile ( "movl %%cr3,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static inline void i386_set_cr3(unsigned int segment) -{ - asm volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) ); -} - -/* * IO Port Access Routines */ @@ -479,12 +438,6 @@ typedef struct { page_table_entry pageTableEntry[MAX_ENTRY]; } page_table; -static inline void flush_cache() -{ - /* Would this be better as a macro? */ - asm ("wbinvd"); /* gcc did not like a volatile being on this */ -} - /* C declaration for paging management */ diff --git a/c/src/lib/libcpu/i386/page.c b/c/src/lib/libcpu/i386/page.c index fc28b7687a..e5cceeed23 100644 --- a/c/src/lib/libcpu/i386/page.c +++ b/c/src/lib/libcpu/i386/page.c @@ -45,7 +45,7 @@ extern rtems_unsigned32 rtemsFreeMemStart; void _CPU_disable_paging() { cr0 regCr0; - flush_cache(); + rtems_flush_entire_data_cache(); regCr0.i = i386_get_cr0(); regCr0.cr0.paging = 0; i386_set_cr0( regCr0.i ); @@ -60,7 +60,7 @@ void _CPU_enable_paging() { regCr0.i = i386_get_cr0(); regCr0.cr0.paging = 1; i386_set_cr0( regCr0.i ); - flush_cache(); + rtems_flush_entire_data_cache(); } @@ -154,32 +154,6 @@ int init_paging() { } /* - * Disable the entire cache - */ -void _CPU_disable_cache() { - cr0 regCr0; - - regCr0.i = i386_get_cr0(); - regCr0.cr0.page_level_cache_disable = 1; - regCr0.cr0.no_write_through = 1; - i386_set_cr0( regCr0.i ); - flush_cache(); -} - -/* - * Disable the entire cache - */ -void _CPU_enable_cache() { - cr0 regCr0; - - regCr0.i = i386_get_cr0(); - regCr0.cr0.page_level_cache_disable = 0; - regCr0.cr0.no_write_through = 0; - i386_set_cr0( regCr0.i ); - /*flush_cache();*/ -} - -/* * Is cache enable */ int _CPU_is_cache_enabled() { |