summaryrefslogtreecommitdiffstats
path: root/c/src/lib/libcpu/README
diff options
context:
space:
mode:
authorJoel Sherrill <joel.sherrill@OARcorp.com>2004-09-29 20:11:54 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2004-09-29 20:11:54 +0000
commit0418016acf6bf74f3edfd364654981920fcb6cb0 (patch)
tree78d7436926386f4dc1cf0c99d53d5d73c6f57293 /c/src/lib/libcpu/README
parent2004-09-29 Joel Sherrill <joel@OARcorp.com> (diff)
downloadrtems-0418016acf6bf74f3edfd364654981920fcb6cb0.tar.bz2
2004-09-29 Joel Sherrill <joel@OARcorp.com>
* README: i960 obsoleted. * i960/.cvsignore, i960/ChangeLog, i960/Makefile.am, i960/configure.ac, i960/i960ca/.cvsignore, i960/i960ca/Makefile.am, i960/i960ca/cpu_install_intr_stack.c, i960/i960ca/cpu_install_raw_isr.c, i960/i960ka/.cvsignore, i960/i960ka/Makefile.am, i960/i960ka/cpu_install_intr_stack.c, i960/i960ka/cpu_install_raw_isr.c, i960/i960rp/.cvsignore, i960/i960rp/Makefile.am, i960/i960rp/cpu_install_intr_stack.c, i960/i960rp/cpu_install_raw_isr.c, i960/include/i960CA.h, i960/include/i960HA.h, i960/include/i960JX_RP_common.h, i960/include/i960KA.h, i960/include/i960RP.h: Removed.
Diffstat (limited to 'c/src/lib/libcpu/README')
-rw-r--r--c/src/lib/libcpu/README9
1 files changed, 5 insertions, 4 deletions
diff --git a/c/src/lib/libcpu/README b/c/src/lib/libcpu/README
index e7e293660c..21d0dee7cb 100644
--- a/c/src/lib/libcpu/README
+++ b/c/src/lib/libcpu/README
@@ -5,10 +5,11 @@
This is the README file for libcpu.
This directory contains reusable libraries which are CPU dependent but not
-target board dependent. For example, the HPPA has an on chip interval timer
-which may be used by all HPPA bsp's.
+target board dependent. For example, the PowerPC has an on CPU decrementer
+register which may be used by all PowerPC BSP's for the Clock and Timer
+Drivers.
-Another example might be the Intel i960CA has on-chip DMA which could be
-supported in a library and placed in lib/libcpu/i960. This level of support
+Other examples include the caching support for the m68k CPU models and
+MIPS CPU model exception vectoring routines. This level of support
will make it easier for others developing embedded applications on a given
CPU.