various changes to gen83xx BSP and others

8 files changed, 76 insertions, 20 deletions

diff --git a/c/src/lib/libbsp/bfin/acinclude.m4 b/c/src/lib/libbsp/bfin/acinclude.m4
index 9c730bd99c..ebab950593 100644
--- a/c/src/lib/libbsp/bfin/acinclude.m4
+++ b/c/src/lib/libbsp/bfin/acinclude.m4
@@ -2,8 +2,6 @@
 AC_DEFUN([RTEMS_CHECK_BSPDIR],
 [
   case "$1" in
-  bf537Stamp )
-    AC_CONFIG_SUBDIRS([bf537Stamp]);;
   eZKit533 )
     AC_CONFIG_SUBDIRS([eZKit533]);;
   *)
diff --git a/c/src/lib/libbsp/m68k/acinclude.m4 b/c/src/lib/libbsp/m68k/acinclude.m4
index 4bd15a6adb..8c7650d4ec 100644
--- a/c/src/lib/libbsp/m68k/acinclude.m4
+++ b/c/src/lib/libbsp/m68k/acinclude.m4
@@ -18,12 +18,8 @@ AC_DEFUN([RTEMS_CHECK_BSPDIR],
     AC_CONFIG_SUBDIRS([idp]);;
   mcf5206elite )
     AC_CONFIG_SUBDIRS([mcf5206elite]);;
-  mcf52235 )
-    AC_CONFIG_SUBDIRS([mcf52235]);;
   mcf5235 )
     AC_CONFIG_SUBDIRS([mcf5235]);;
-  mcf5329 )
-    AC_CONFIG_SUBDIRS([mcf5329]);;
   mrm332 )
     AC_CONFIG_SUBDIRS([mrm332]);;
   mvme136 )
diff --git a/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog b/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog
index c7e67ee8f9..f159a7d8a4 100644
--- a/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog
@@ -1,3 +1,10 @@
+2008-08-26	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+	
+	* include/hwreg_vals.h: added some settings for HSC_CM01
+	* network/network.c: changed initialization code for HSC_CM01
+	* startup/cpuinit.c: changed initialization code for HSC_CM01
+	* startup/linkcmds.hsc_cm01: adapted memory map to HSC_CM01
+
 2008-08-21	Joel Sherrill <joel.sherrill@oarcorp.com>
 
 	* Makefile.am: Added bspclean.c and use shared bsppretaskinghook.c.
diff --git a/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h
index 887670a99f..aaeff4c6ba 100644
--- a/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h
+++ b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h
@@ -21,7 +21,7 @@
 #define __GEN83xx_HWREG_VALS_h
 
 #include <mpc83xx/mpc83xx.h>
-
+#include <bsp.h>
 /*
  * distinguish board characteristics
  */
@@ -92,8 +92,8 @@
 
 #define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |	\
 			  RCWHR_PCI_32       |	\
-			  RCWHR_PCI1ARB_EN   |	\
-			  RCWHR_PCI2ARB_EN   |	\
+			  RCWHR_PCI1ARB_DIS  |	\
+			  RCWHR_PCI2ARB_DIS  |	\
 			  RCWHR_CORE_EN      |	\
 			  RCWHR_BMS_LOW      |	\
 			  RCWHR_BOOTSEQ_NONE |	\
@@ -102,8 +102,8 @@
 			  RCWHR_TSEC1M_RGMII |	\
 			  RCWHR_TSEC2M_GMII  |	\
 			  RCWHR_ENDIAN_BIG   |	\
-			  RCWHR_LALE_NORM    |	\
-			  RCWHR_LDP_PAR)
+			  RCWHR_LALE_EARLY   |	\
+			  RCWHR_LDP_SPC)
 
 #elif defined( HAS_UBOOT)
 
@@ -175,10 +175,30 @@
  * for JPK HSC_CM01
  */
 
+/* fpga BCSR register */
+#define FPGA_START 0xF8000000
+#define FPGA_SIZE  0x8000
+#define FPGA_END   (FPGA_START+FPGA_SIZE-1)
+
 /*
  * working values for various registers, used in start/start.S
  */
 
+/* fpga config 16 MB size */
+#define FPGA_CONFIG_START       0xF8000000
+#define FPGA_CONFIG_SIZE        0x01000000
+/* fpga register 8 MB size */
+#define FPGA_REGISTER_START     0xF9000000
+#define FPGA_REGISTER_SIZE      0x00800000
+/* fpga fifo 8 MB size */
+#define FPGA_FIFO_START         0xF9800000
+#define FPGA_FIFO_SIZE          0x00800000
+
+#define FPGA_START (FPGA_CONFIG_START)
+// fpga window size 32 MByte
+#define FPGA_SIZE  (0x02000000)
+#define FPGA_END   (FPGA_START+FPGA_SIZE-1)
+
 /*
  * Local Access Windows
  * FIXME: decode bit settings 
@@ -186,7 +206,7 @@
 
 #define LBLAWBAR0_VAL  bsp_rom_start
 #define LBLAWAR0_VAL   0x80000018
-#define LBLAWBAR1_VAL  0xF8000000
+#define LBLAWBAR1_VAL  (FPGA_CONFIG_START)
 #define LBLAWAR1_VAL   0x80000015
 #define DDRLAWBAR0_VAL bsp_ram_start
 #define DDRLAWAR0_VAL  0x8000001B
@@ -196,13 +216,25 @@
  */
 #define BR0_VAL 0xFE001001
 #define OR0_VAL 0xFE000E54
-#define BR3_VAL 0xF8001881
-#define OR3_VAL 0xFFC01100
+// fpga config access range (UPM_A) (32 kByte)
+#define BR2_VAL (FPGA_CONFIG_START | 0x01881)
+#define OR2_VAL 0xFFF80100
+
+// fpga register access range (UPM_B) (8 MByte)
+#define BR3_VAL (FPGA_REGISTER_START | 0x018A1)
+#define OR3_VAL 0xFF800100
+
+// fpga fifo access range (UPM_B) (8 MByte)
+#define BR4_VAL (FPGA_FIFO_START | 0x018A1)
+#define OR4_VAL 0xFF800100
+
 /*
- * Local (memory) bus divider
- * FIXME: decode bit settings 
+ * SDRAM registers
  */
-#define LCRR_VAL  0x00010004
+#define MRPTR_VAL 0x20000000
+#define LSRT_VAL  0x32000000
+#define LSDMR_VAL 0x4062D733
+#define LCRR_VAL  0x80010004
 
 /*
  * DDR-SDRAM registers
diff --git a/c/src/lib/libbsp/powerpc/gen83xx/network/network.c b/c/src/lib/libbsp/powerpc/gen83xx/network/network.c
index a3b80dac3f..2d5f59d88f 100644
--- a/c/src/lib/libbsp/powerpc/gen83xx/network/network.c
+++ b/c/src/lib/libbsp/powerpc/gen83xx/network/network.c
@@ -77,6 +77,14 @@ int BSP_tsec_attach
   }
   if (attaching) {
 #if (TSEC_IFMODE==TSEC_IFMODE_GMII)
+#if !defined(HSC_CM01)
+
+      /*
+       * do not change system I/O configuration registers on HSC board
+       * because should initialize from RCW
+       */
+
+
     if (unitNumber == 1) {
       /*
        * init system I/O configuration registers 
@@ -101,6 +109,7 @@ int BSP_tsec_attach
       mpc83xx.gpio[0].gpdir = ((mpc83xx.gpio[0].gpdir & ~0x000FFFFF)
 			       |                         0x00087881);
     }
+#endif /* !defined(HSC_CM01) */
 #endif
 #if (TSEC_IFMODE==TSEC_IFMODE_RGMII)
 
diff --git a/c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c b/c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c
index 95a84e197c..ff75a34adc 100644
--- a/c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c
+++ b/c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c
@@ -259,6 +259,20 @@ void cpu_init( void)
   );
   SET_DBAT( 2, dbat.batu, dbat.batl);
 
+#if defined(HSC_CM01)
+  calc_dbat_regvals(
+    &dbat,
+    FPGA_START,
+    FPGA_SIZE,
+    true,
+    true,
+    true,
+    false,
+    BPP_RW
+  );
+  SET_DBAT(3,dbat.batu,dbat.batl);
+#endif
+
 #ifdef MPC8313ERDB
   /* Enhanced Local Bus Controller (eLBC) */
   calc_dbat_regvals(
diff --git a/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01 b/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01
index 4e944dfa2c..bbbf2ddbbd 100644
--- a/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01
+++ b/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01
@@ -7,7 +7,7 @@
 MEMORY {
 	RAM : ORIGIN = 0x0, LENGTH = 256M
 	ROM : ORIGIN = 0xfe000000, LENGTH = 8M
-	MPC83XX_REGS : ORIGIN = 0xe0000000, LENGTH = 256k
+	MPC83XX_REGS : ORIGIN = 0xe0000000, LENGTH = 1M
 	NIRVANA : ORIGIN = 0x0, LENGTH = 0
 }
 
diff --git a/c/src/lib/libbsp/powerpc/mvme3100/preinstall.am b/c/src/lib/libbsp/powerpc/mvme3100/preinstall.am
index 4c65291961..48f2f4f8a7 100644
--- a/c/src/lib/libbsp/powerpc/mvme3100/preinstall.am
+++ b/c/src/lib/libbsp/powerpc/mvme3100/preinstall.am
@@ -73,7 +73,7 @@ $(PROJECT_INCLUDE)/bsp/uart.h: ../../powerpc/shared/console/uart.h $(PROJECT_INC
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart.h
 
-$(PROJECT_INCLUDE)/bsp/irq.h: ./irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+$(PROJECT_INCLUDE)/bsp/irq.h: irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
 
@@ -97,7 +97,7 @@ $(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bsps
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h
 
-$(PROJECT_INCLUDE)/bsp/VMEConfig.h: ./vme/VMEConfig.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+$(PROJECT_INCLUDE)/bsp/VMEConfig.h: vme/VMEConfig.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VMEConfig.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VMEConfig.h