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| author | Joel Sherrill <joel.sherrill@oarcorp.com> | 2012-06-11 13:37:29 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@oarcorp.com> | 2012-06-11 13:37:29 -0500 |
| commit | 2d7ae960bbdbc82f795814ee6c600e93200ddf4d (patch) | |
| tree | ad12bf1ac7f551a70f004a897a7246cf0b9ea716 /c/src/lib/libbsp/v850/gdbv850sim/start/start.S | |
| parent | powerpc/cpu.h: Define CPU_SIMPLE_VECTORED_INTERRUPTS and remove _CPU_ISR_Init... (diff) | |
| download | rtems-2d7ae960bbdbc82f795814ee6c600e93200ddf4d.tar.bz2 | |
v850 port: Initial addition with BSP for simulator in GDB
Port
+ v850 does not have appear to have any optimized bit scan instructions
+ v850 does have single instructions for wap u16 and u32
+ Code path optimization preferences set
+ Add BSP variants for each GCC CPU model flag and a README
- v850e1 variant does not work (fails during BSP initialization)
BSP for GDB v850 Simulator
+ linkcmds matches defaults in GDB simulator with RTEMS mods
+ crt1.c added from v850 newlib port for __main()
+ BSP exits cleanly
+ printk and console I/O work
+ uses clock tick from IDLE task
+ Tests not requiring real clock ISR work
Documentation
+ CPU Supplment chapter for v850 added
Diffstat (limited to 'c/src/lib/libbsp/v850/gdbv850sim/start/start.S')
| -rw-r--r-- | c/src/lib/libbsp/v850/gdbv850sim/start/start.S | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/start/start.S b/c/src/lib/libbsp/v850/gdbv850sim/start/start.S new file mode 100644 index 0000000000..419e635393 --- /dev/null +++ b/c/src/lib/libbsp/v850/gdbv850sim/start/start.S @@ -0,0 +1,78 @@ +# NEC V850 startup code + + .section .text + .global _start + +_start: + +#if defined(__v850e__) || defined(__v850e2__) || defined(__v850e2v3__) + + movea 255, r0, r20 + mov 65535, r21 + mov hilo(_stack), sp + mov hilo(__ep), ep + mov hilo(__gp), gp + mov hilo(__ctbp), r6 + ldsr r6, ctbp + mov hilo(_edata), r6 + mov hilo(_end), r7 +.L0: + st.w r0, 0[r6] + addi 4, r6, r6 + cmp r7, r6 + bl .L0 +.L1: + jarl ___main, r31 + addi -16, sp, sp + mov 0, r6 + mov 0, r7 + mov 0, r8 + /* jarl _main, r31 */ + jarl _boot_card, r31 + mov r10, r6 + jarl _exit, r31 + +# else + movea 255, r0, r20 + mov r0, r21 + ori 65535, r0, r21 + movhi hi(_stack), r0, sp + movea lo(_stack), sp, sp + movhi hi(__ep), r0, ep + movea lo(__ep), ep, ep + movhi hi(__gp), r0, gp + movea lo(__gp), gp, gp + + movhi hi(_edata), r0, r6 + movea lo(_edata), r6, r6 + movhi hi(_end), r0, r7 + movea lo(_end), r7, r7 +.L0: + st.b r0, 0[r6] + addi 1, r6, r6 + cmp r7, r6 + bl .L0 +.L1: + /* jarl ___main, r31 */ + addi -16, sp, sp + mov 0, r6 + mov 0, r7 + mov 0, r8 + /* jarl _main, r31 */ + jarl _boot_card, r31 + mov r10, r6 +.L2: + br .L2 + /* jarl _exit, r31 */ +# endif + +#if 0 + .section .stack +_stack: .long 1 +#endif + + .section .data + .global ___dso_handle + .weak ___dso_handle +___dso_handle: + .long 0 |