Remove stray white spaces.

12 files changed, 125 insertions, 125 deletions

diff --git a/c/src/lib/libbsp/sparc/erc32/clock/ckinit.c b/c/src/lib/libbsp/sparc/erc32/clock/ckinit.c
index c6c2d8c687..da962c41d6 100644
--- a/c/src/lib/libbsp/sparc/erc32/clock/ckinit.c
+++ b/c/src/lib/libbsp/sparc/erc32/clock/ckinit.c
@@ -15,10 +15,10 @@
  *  http://www.rtems.com/license/LICENSE.
  *
  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
- *  Research Corporation (OAR) under contract to the European Space 
+ *  Research Corporation (OAR) under contract to the European Space
  *  Agency (ESA).
  *
- *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
+ *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
  *  European Space Agency.
  *
  *  $Id$
@@ -53,11 +53,11 @@ extern uint32_t         CPU_SPARC_CLICKS_PER_TICK;
 rtems_isr_entry  Old_ticker;
 
 void Clock_exit( void );
- 
+
 /*
  * These are set by clock driver during its init
  */
- 
+
 rtems_device_major_number rtems_clock_major = ~0;
 rtems_device_minor_number rtems_clock_minor;
 
@@ -88,7 +88,7 @@ rtems_isr Clock_isr(
 #if SIMSPARC_FAST_IDLE
   ERC32_MEC.Real_Time_Clock_Counter = CPU_SPARC_CLICKS_PER_TICK;
   ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
-    ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING | 
+    ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING |
       ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER
   );
 #endif
@@ -135,14 +135,14 @@ void Install_clock(
   ERC32_MEC.Real_Time_Clock_Counter = CPU_SPARC_CLICKS_PER_TICK;
 
   ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
-    ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING | 
-      ERC32_MEC_TIMER_COUNTER_LOAD_SCALER | 
-      ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER 
+    ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING |
+      ERC32_MEC_TIMER_COUNTER_LOAD_SCALER |
+      ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER
   );
- 
+
   ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
     ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING |
-      ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO 
+      ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO
   );
 
   atexit( Clock_exit );
@@ -167,12 +167,12 @@ void Clock_exit( void )
   ERC32_Mask_interrupt( ERC32_INTERRUPT_REAL_TIME_CLOCK );
 
   ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
-    ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING 
+    ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING
   );
 
   /* do not restore old vector */
 }
- 
+
 /*
  *  Clock_initialize
  *
@@ -196,17 +196,17 @@ rtems_device_driver Clock_initialize(
 )
 {
   Install_clock( Clock_isr );
- 
+
   /*
    * make major/minor avail to others such as shared memory driver
    */
- 
+
   rtems_clock_major = major;
   rtems_clock_minor = minor;
- 
+
   return RTEMS_SUCCESSFUL;
 }
- 
+
 /*
  *  Clock_control
  *
@@ -231,15 +231,15 @@ rtems_device_driver Clock_control(
 {
     uint32_t         isrlevel;
     rtems_libio_ioctl_args_t *args = pargp;
- 
+
     if (args == 0)
         goto done;
- 
+
     /*
      * This is hokey, but until we get a defined interface
      * to do this, it will just be this simple...
      */
- 
+
     if (args->command == rtems_build_name('I', 'S', 'R', ' '))
     {
         Clock_isr(CLOCK_VECTOR);
@@ -250,7 +250,7 @@ rtems_device_driver Clock_control(
        (void) set_vector( args->buffer, CLOCK_VECTOR, 1 );
       rtems_interrupt_enable( isrlevel );
     }
- 
+
 done:
     return RTEMS_SUCCESSFUL;
 }
diff --git a/c/src/lib/libbsp/sparc/erc32/console/console.c b/c/src/lib/libbsp/sparc/erc32/console/console.c
index 90102fbc1e..c7ec8a366a 100644
--- a/c/src/lib/libbsp/sparc/erc32/console/console.c
+++ b/c/src/lib/libbsp/sparc/erc32/console/console.c
@@ -20,7 +20,7 @@
 
 /*
  *  Should we use a polled or interrupt drived console?
- *  
+ *
  *  NOTE: This is defined in the custom/erc32.cfg file.
  *
  *  WARNING:  In sis 1.6, it did not appear that the UART interrupts
@@ -28,7 +28,7 @@
  *            a character into the TX buffer, an interrupt was generated.
  *            This did not allow enough time for the program to put more
  *            characters in the buffer.  So every character resulted in
- *            "priming" the transmitter.   This effectively results in 
+ *            "priming" the transmitter.   This effectively results in
  *            in a polled console with a useless interrupt per character
  *            on output.  It is reasonable to assume that input does not
  *            share this problem although it was not investigated.
@@ -49,7 +49,7 @@ void console_outbyte_polled(
 /* body is in debugputs.c */
 
 /*
- *  console_inbyte_nonblocking 
+ *  console_inbyte_nonblocking
  *
  *  This routine polls for a character.
  */
@@ -69,10 +69,10 @@ int console_inbyte_nonblocking( int port );
  */
 
 #include <rtems/ringbuf.h>
- 
+
 Ring_buffer_t  TX_Buffer[ 2 ];
 boolean        Is_TX_active[ 2 ];
- 
+
 void *console_termios_data[ 2 ];
 
 /*
@@ -81,7 +81,7 @@ void *console_termios_data[ 2 ];
  *  This routine is the console interrupt handler for Channel A.
  *
  *  Input parameters:
- *    vector - vector number 
+ *    vector - vector number
  *
  *  Output parameters: NONE
  *
@@ -91,10 +91,10 @@ void *console_termios_data[ 2 ];
 rtems_isr console_isr_a(
   rtems_vector_number vector
 )
-{ 
+{
   char ch;
   int UStat;
- 
+
   if ( (UStat = ERC32_MEC.UART_Status) & ERC32_MEC_UART_STATUS_DRA ) {
     if (UStat & ERC32_MEC_UART_STATUS_ERRA) {
       ERC32_MEC.UART_Status = ERC32_MEC_UART_STATUS_CLRA;
@@ -104,7 +104,7 @@ rtems_isr console_isr_a(
 
     rtems_termios_enqueue_raw_characters( console_termios_data[ 0 ], &ch, 1 );
   }
- 
+
   if ( ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEA ) {
     if ( !Ring_buffer_Is_empty( &TX_Buffer[ 0 ] ) ) {
       Ring_buffer_Remove_character( &TX_Buffer[ 0 ], ch );
@@ -112,7 +112,7 @@ rtems_isr console_isr_a(
     } else
      Is_TX_active[ 0 ] = FALSE;
   }
- 
+
   ERC32_Clear_interrupt( ERC32_INTERRUPT_UART_A_RX_TX );
 }
 
@@ -122,13 +122,13 @@ rtems_isr console_isr_a(
  *  This routine is the console interrupt handler for Channel B.
  *
  *  Input parameters:
- *    vector - vector number 
+ *    vector - vector number
  *
  *  Output parameters: NONE
  *
  *  Return values:     NONE
  */
- 
+
 rtems_isr console_isr_b(
   rtems_vector_number vector
 )
@@ -194,11 +194,11 @@ void console_exit()
    *  Now wait for all the data to actually get out ... the send register
    *  should be empty.
    */
- 
-  while ( (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEA) != 
+
+  while ( (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEA) !=
           ERC32_MEC_UART_STATUS_THEA );
 
-  while ( (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEB) != 
+  while ( (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEB) !=
           ERC32_MEC_UART_STATUS_THEB );
 
 }
@@ -253,7 +253,7 @@ void console_initialize_interrupts( void )
  *
  *  Return values:      NONE
  */
- 
+
 void console_outbyte_interrupt(
   int   port,
   char  ch
@@ -300,7 +300,7 @@ int console_write_support (int minor, const char *buf, int len)
  *  Console Device Driver Entry Points
  *
  */
- 
+
 rtems_device_driver console_initialize(
   rtems_device_major_number  major,
   rtems_device_minor_number  minor,
@@ -326,7 +326,7 @@ rtems_device_driver console_initialize(
   /*
    *  Initialize Hardware
    */
- 
+
 #if (CONSOLE_USE_INTERRUPTS)
   console_initialize_interrupts();
 #endif
@@ -369,7 +369,7 @@ rtems_device_driver console_open(
   assert( minor <= 1 );
   if ( minor > 2 )
     return RTEMS_INVALID_NUMBER;
- 
+
 #if (CONSOLE_USE_INTERRUPTS)
   sc = rtems_termios_open (major, minor, arg, &intrCallbacks);
 
@@ -380,7 +380,7 @@ rtems_device_driver console_open(
 
   return RTEMS_SUCCESSFUL;
 }
- 
+
 rtems_device_driver console_close(
   rtems_device_major_number major,
   rtems_device_minor_number minor,
@@ -389,7 +389,7 @@ rtems_device_driver console_close(
 {
   return rtems_termios_close (arg);
 }
- 
+
 rtems_device_driver console_read(
   rtems_device_major_number major,
   rtems_device_minor_number minor,
@@ -398,7 +398,7 @@ rtems_device_driver console_read(
 {
   return rtems_termios_read (arg);
 }
- 
+
 rtems_device_driver console_write(
   rtems_device_major_number major,
   rtems_device_minor_number minor,
@@ -407,7 +407,7 @@ rtems_device_driver console_write(
 {
   return rtems_termios_write (arg);
 }
- 
+
 rtems_device_driver console_control(
   rtems_device_major_number major,
   rtems_device_minor_number minor,
diff --git a/c/src/lib/libbsp/sparc/erc32/console/debugputs.c b/c/src/lib/libbsp/sparc/erc32/console/debugputs.c
index c55dab64c4..a836174df5 100644
--- a/c/src/lib/libbsp/sparc/erc32/console/debugputs.c
+++ b/c/src/lib/libbsp/sparc/erc32/console/debugputs.c
@@ -40,7 +40,7 @@ void console_outbyte_polled(
 }
 
 /*
- *  console_inbyte_nonblocking 
+ *  console_inbyte_nonblocking
  *
  *  This routine polls for a character.
  */
@@ -104,7 +104,7 @@ void DEBUG_puts(
   uint32_t   old_level;
 
   ERC32_Disable_interrupt( ERC32_INTERRUPT_UART_A_RX_TX, old_level );
-    for ( s = string ; *s ; s++ ) 
+    for ( s = string ; *s ; s++ )
       console_outbyte_polled( 0, *s );
 
     console_outbyte_polled( 0, '\r' );
diff --git a/c/src/lib/libbsp/sparc/erc32/erc32sonic/erc32sonic.c b/c/src/lib/libbsp/sparc/erc32/erc32sonic/erc32sonic.c
index 2619f33f49..55313646c3 100644
--- a/c/src/lib/libbsp/sparc/erc32/erc32sonic/erc32sonic.c
+++ b/c/src/lib/libbsp/sparc/erc32/erc32sonic/erc32sonic.c
@@ -87,8 +87,8 @@ uint32_t   erc32_sonic_read_register(
 #define SONIC_VECTOR 0x1E
 
 sonic_configuration_t erc32_sonic_configuration = {
-  SONIC_BASE_ADDRESS,        /* base address */ 
-  SONIC_VECTOR,              /* vector number */ 
+  SONIC_BASE_ADDRESS,        /* base address */
+  SONIC_VECTOR,              /* vector number */
   SONIC_DCR,                 /* DCR register value */
   SONIC_DC2,                 /* DC2 register value */
   TDA_COUNT,                 /* number of transmit descriptors */
@@ -105,5 +105,5 @@ int rtems_erc32_sonic_driver_attach(struct rtems_bsdnet_ifconfig *config)
   ERC32_MEC.Control |= 0x10000; 		/* Enable DMA */
   ERC32_MEC.Interrupt_Mask &= ~(1 << (SONIC_VECTOR - 0x10));
   return(rtems_sonic_driver_attach( config, &erc32_sonic_configuration ));
-  
+
 }
diff --git a/c/src/lib/libbsp/sparc/erc32/include/bsp.h b/c/src/lib/libbsp/sparc/erc32/include/bsp.h
index 90cef02065..1e936df29b 100644
--- a/c/src/lib/libbsp/sparc/erc32/include/bsp.h
+++ b/c/src/lib/libbsp/sparc/erc32/include/bsp.h
@@ -10,10 +10,10 @@
  *  http://www.rtems.com/license/LICENSE.
  *
  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
- *  Research Corporation (OAR) under contract to the European Space 
+ *  Research Corporation (OAR) under contract to the European Space
  *  Agency (ESA).
  *
- *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
+ *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
  *  European Space Agency.
  *
  *  $Id$
@@ -90,9 +90,9 @@ extern int rtems_erc32_sonic_driver_attach (struct rtems_bsdnet_ifconfig *config
 #define Cause_tm27_intr() \
   asm volatile( "ta 0x10; nop " );
 
-#define Clear_tm27_intr()  
+#define Clear_tm27_intr()
 
-#define Lower_tm27_intr() 
+#define Lower_tm27_intr()
 
 /*
  *  The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
@@ -104,13 +104,13 @@ extern int rtems_erc32_sonic_driver_attach (struct rtems_bsdnet_ifconfig *config
 #define TEST_INTERRUPT_SOURCE2 (ERC32_INTERRUPT_EXTERNAL_1+1)
 #define TEST_VECTOR ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE )
 #define TEST_VECTOR2 ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 )
- 
+
 #define MUST_WAIT_FOR_INTERRUPT 1
- 
+
 #define Install_tm27_vector( handler ) \
   set_vector( (handler), TEST_VECTOR, 1 ); \
   set_vector( (handler), TEST_VECTOR2, 1 );
- 
+
 #define Cause_tm27_intr() \
   do { \
     ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1) ); \
@@ -118,10 +118,10 @@ extern int rtems_erc32_sonic_driver_attach (struct rtems_bsdnet_ifconfig *config
     nop(); \
     nop(); \
   } while (0)
- 
+
 #define Clear_tm27_intr() \
   ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE )
- 
+
 #define Lower_tm27_intr()
 
 #endif
@@ -144,28 +144,28 @@ extern void Clock_delay(uint32_t         microseconds);
 extern int   RAM_START;
 extern int   RAM_END;
 extern int   RAM_SIZE;
- 
+
 extern int   PROM_START;
 extern int   PROM_END;
 extern int   PROM_SIZE;
 
 extern int   CLOCK_SPEED;
- 
+
 extern int   end;        /* last address in the program */
 
 /*
  *  Device Driver Table Entries
  */
- 
+
 /*
  * NOTE: Use the standard Console driver entry
  */
- 
+
 /*
  * NOTE: Use the standard Clock driver entry
  */
- 
- 
+
+
 /* miscellaneous stuff assumed to exist */
 
 void bsp_cleanup( void );
diff --git a/c/src/lib/libbsp/sparc/erc32/include/coverhd.h b/c/src/lib/libbsp/sparc/erc32/include/coverhd.h
index eea7cc91ca..1d50a4ff7a 100644
--- a/c/src/lib/libbsp/sparc/erc32/include/coverhd.h
+++ b/c/src/lib/libbsp/sparc/erc32/include/coverhd.h
@@ -11,10 +11,10 @@
  *  http://www.rtems.com/license/LICENSE.
  *
  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
- *  Research Corporation (OAR) under contract to the European Space 
+ *  Research Corporation (OAR) under contract to the European Space
  *  Agency (ESA).
  *
- *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
+ *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
  *  European Space Agency.
  *
  *  $Id$
diff --git a/c/src/lib/libbsp/sparc/erc32/include/erc32.h b/c/src/lib/libbsp/sparc/erc32/include/erc32.h
index 3d214ee10f..959b4ba527 100644
--- a/c/src/lib/libbsp/sparc/erc32/include/erc32.h
+++ b/c/src/lib/libbsp/sparc/erc32/include/erc32.h
@@ -5,9 +5,9 @@
  *  601/602 chipset.  This CPU has a number of on-board peripherals and
  *  was developed by the European Space Agency to target space applications.
  *
- *  NOTE:  Other than where absolutely required, this version currently 
- *         supports only the peripherals and bits used by the basic board 
- *         support package. This includes at least significant pieces of 
+ *  NOTE:  Other than where absolutely required, this version currently
+ *         supports only the peripherals and bits used by the basic board
+ *         support package. This includes at least significant pieces of
  *         the following items:
  *
  *           + UART Channels A and B
@@ -26,20 +26,20 @@
  *  http://www.rtems.com/license/LICENSE.
  *
  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
- *  Research Corporation (OAR) under contract to the European Space 
+ *  Research Corporation (OAR) under contract to the European Space
  *  Agency (ESA).
  *
- *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
+ *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
  *  European Space Agency.
  *
  *  $Id$
  */
- 
+
 #ifndef _INCLUDE_ERC32_h
 #define _INCLUDE_ERC32_h
 
 #include <rtems/score/sparc.h>
- 
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -47,7 +47,7 @@ extern "C" {
 /*
  *  Interrupt Sources
  *
- *  The interrupt source numbers directly map to the trap type and to 
+ *  The interrupt source numbers directly map to the trap type and to
  *  the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
  *  and the Interrupt Pending Registers.
  */
@@ -75,7 +75,7 @@ extern "C" {
  *
  *  Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
  *
- *  NOTE: The priority level for each source corresponds to the least 
+ *  NOTE: The priority level for each source corresponds to the least
  *        significant nibble of the trap type.
  */
 
@@ -88,12 +88,12 @@ extern "C" {
     (_trap) <= ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ) )
 
 /*
- *  Structure for ERC32 memory mapped registers.  
+ *  Structure for ERC32 memory mapped registers.
  *
  *  Source: Section 3.25.2 - Register Address Map
  *
- *  NOTE:  There is only one of these structures per CPU, its base address 
- *         is 0x01f80000, and the variable MEC is placed there by the 
+ *  NOTE:  There is only one of these structures per CPU, its base address
+ *         is 0x01f80000, and the variable MEC is placed there by the
  *         linkcmds file.
  */
 
@@ -116,7 +116,7 @@ typedef struct {
   volatile uint32_t    Interrupt_Force;                      /* offset 0x54 */
   volatile uint32_t    Unimplemented_3[ 2 ];                 /* offset 0x58 */
                                                              /* offset 0x60 */
-  volatile uint32_t    Watchdog_Program_and_Timeout_Acknowledge; 
+  volatile uint32_t    Watchdog_Program_and_Timeout_Acknowledge;
   volatile uint32_t    Watchdog_Trap_Door_Set;               /* offset 0x64 */
   volatile uint32_t    Unimplemented_4[ 6 ];                 /* offset 0x68 */
   volatile uint32_t    Real_Time_Clock_Counter;              /* offset 0x80 */
@@ -249,7 +249,7 @@ typedef struct {
 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M  ( 5 << 18 )
 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M  ( 6 << 18 )
 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M  ( 7 << 18 )
- 
+
 /*
  *  The following defines the bits in the Timer Control Register.
  */
@@ -277,8 +277,8 @@ typedef struct {
  *
  */
 
-#define ERC32_MEC_UART_CONTROL_RTD  0x000000FF /* RX/TX data */ 
- 
+#define ERC32_MEC_UART_CONTROL_RTD  0x000000FF /* RX/TX data */
+
 /*
  *  The following defines the bits in the MEC UART Control Registers.
  */
@@ -324,7 +324,7 @@ typedef struct {
  */
 
 extern ERC32_Register_Map ERC32_MEC;
- 
+
 /*
  *  Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
  *  and the Interrupt Pending Registers.
@@ -349,13 +349,13 @@ extern ERC32_Register_Map ERC32_MEC;
     ERC32_MEC.Interrupt_Force = (1 << (_source)); \
     sparc_enable_interrupts( _level ); \
   } while (0)
- 
+
 #define ERC32_Is_interrupt_pending( _source ) \
   (ERC32_MEC.Interrupt_Pending & (1 << (_source)))
- 
+
 #define ERC32_Is_interrupt_masked( _source ) \
   (ERC32_MEC.Interrupt_Masked & (1 << (_source)))
- 
+
 #define ERC32_Mask_interrupt( _source ) \
   do { \
     uint32_t   _level; \
@@ -364,7 +364,7 @@ extern ERC32_Register_Map ERC32_MEC;
       ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \
     sparc_enable_interrupts( _level ); \
   } while (0)
- 
+
 #define ERC32_Unmask_interrupt( _source ) \
   do { \
     uint32_t   _level; \
@@ -385,7 +385,7 @@ extern ERC32_Register_Map ERC32_MEC;
     sparc_enable_interrupts( _level ); \
     (_previous) &= _mask; \
   } while (0)
- 
+
 #define ERC32_Restore_interrupt( _source, _previous ) \
   do { \
     uint32_t   _level; \
@@ -405,9 +405,9 @@ extern ERC32_Register_Map ERC32_MEC;
  *  and status of the other timer.
  *
  *  This code promotes the view that the two timers are completely independent.
- *  By exclusively using the routines below to access the Timer Control 
+ *  By exclusively using the routines below to access the Timer Control
  *  Register, the application can view the system as having a General Purpose
- *  Timer Control Register and a Real Time Clock Timer Control Register 
+ *  Timer Control Register and a Real Time Clock Timer Control Register
  *  rather than the single shared value.
  *
  *  Each logical timer control register is organized as follows:
@@ -451,7 +451,7 @@ extern ERC32_Register_Map ERC32_MEC;
 extern uint32_t   _ERC32_MEC_Timer_Control_Mirror;
 
 /*
- *  This macros manipulate the General Purpose Timer portion of the 
+ *  This macros manipulate the General Purpose Timer portion of the
  *  Timer Control register and promote the view that there are actually
  *  two independent Timer Control Registers.
  */
@@ -480,11 +480,11 @@ extern uint32_t   _ERC32_MEC_Timer_Control_Mirror;
   } while ( 0 )
 
 /*
- *  This macros manipulate the Real Timer Clock Timer portion of the 
+ *  This macros manipulate the Real Timer Clock Timer portion of the
  *  Timer Control register and promote the view that there are actually
  *  two independent Timer Control Registers.
  */
- 
+
 #define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \
   do { \
     uint32_t   _level; \
@@ -502,7 +502,7 @@ extern uint32_t   _ERC32_MEC_Timer_Control_Mirror;
       ERC32_MEC.Timer_Control = _control; \
     sparc_enable_interrupts( _level ); \
   } while ( 0 )
- 
+
 #define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \
   do { \
     (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
@@ -514,6 +514,6 @@ extern uint32_t   _ERC32_MEC_Timer_Control_Mirror;
 #ifdef __cplusplus
 }
 #endif
- 
+
 #endif /* !_INCLUDE_ERC32_h */
 /* end of include file */
diff --git a/c/src/lib/libbsp/sparc/erc32/startup/boardinit.S b/c/src/lib/libbsp/sparc/erc32/startup/boardinit.S
index 7866c4700a..acdda46cc2 100644
--- a/c/src/lib/libbsp/sparc/erc32/startup/boardinit.S
+++ b/c/src/lib/libbsp/sparc/erc32/startup/boardinit.S
@@ -19,11 +19,11 @@ __bsp_board_init:
 */
 
         set     SYM(ERC32_MEC), %g3  ! g3 = base address of peripherals
-	ld	[%g3], %g2		
+	ld	[%g3], %g2
 	set	0xfe080000, %g1
 	andcc	%g1, %g2, %g0
  	bne	2f
- 
+
  /* Stop the watchdog */
 
 	st	%g0, [%g3 + SYM(ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET)]
@@ -33,8 +33,8 @@ __bsp_board_init:
 	st	%g0, [%g3 + SYM(ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET)]
 
  /* Set the correct memory size in MEC memory config register */
- 
- 	set	SYM(PROM_SIZE), %l0	
+
+ 	set	SYM(PROM_SIZE), %l0
  	set	0, %l1
  	srl	%l0, 18, %l0
 1:
@@ -43,8 +43,8 @@ __bsp_board_init:
  	bne,a	1b
  	inc	%l1
  	sll	%l1, 8, %l1
- 
- 	set	SYM(RAM_SIZE), %l0	
+
+ 	set	SYM(RAM_SIZE), %l0
  	srl	%l0, 19, %l0
 1:
  	tst	%l0
@@ -52,10 +52,10 @@ __bsp_board_init:
  	bne,a	1b
  	inc	%l1
  	sll	%l1, 10, %l1
- 
+
                                            ! set the Memory Configuration
         st     %l1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ]
-          
+
  	set	SYM(RAM_START), %l1  ! Cannot use RAM_END due to bug in linker
  	set	SYM(RAM_SIZE), %l2
  	add	%l1, %l2, %sp
diff --git a/c/src/lib/libbsp/sparc/erc32/startup/erc32mec.c b/c/src/lib/libbsp/sparc/erc32/startup/erc32mec.c
index a49662831b..f3d4e3fbc5 100644
--- a/c/src/lib/libbsp/sparc/erc32/startup/erc32mec.c
+++ b/c/src/lib/libbsp/sparc/erc32/startup/erc32mec.c
@@ -13,5 +13,5 @@
 
 #include <rtems.h>
 #include <bsp.h>
- 
+
 ERC32_Register_Map ERC32_MEC;
diff --git a/c/src/lib/libbsp/sparc/erc32/startup/setvec.c b/c/src/lib/libbsp/sparc/erc32/startup/setvec.c
index 2bd9ad95b6..bd6f2f65e9 100644
--- a/c/src/lib/libbsp/sparc/erc32/startup/setvec.c
+++ b/c/src/lib/libbsp/sparc/erc32/startup/setvec.c
@@ -21,10 +21,10 @@
  *  http://www.rtems.com/license/LICENSE.
  *
  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
- *  Research Corporation (OAR) under contract to the European Space 
+ *  Research Corporation (OAR) under contract to the European Space
  *  Agency (ESA).
  *
- *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
+ *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
  *  European Space Agency.
  *
  *  $Id$
@@ -44,13 +44,13 @@ rtems_isr_entry set_vector(                   /* returns old vector */
 
   if ( type )
     rtems_interrupt_catch( handler, vector, &previous_isr );
-  else 
+  else
     _CPU_ISR_install_raw_handler( vector, handler, (void *)&previous_isr );
 
   real_trap = SPARC_REAL_TRAP_NUMBER( vector );
 
   if ( ERC32_Is_MEC_Trap( real_trap ) ) {
-    
+
     source = ERC32_TRAP_SOURCE( real_trap );
 
     ERC32_Clear_interrupt( source );
diff --git a/c/src/lib/libbsp/sparc/erc32/startup/spurious.c b/c/src/lib/libbsp/sparc/erc32/startup/spurious.c
index a3d3936df0..6f4d46d37e 100644
--- a/c/src/lib/libbsp/sparc/erc32/startup/spurious.c
+++ b/c/src/lib/libbsp/sparc/erc32/startup/spurious.c
@@ -1,11 +1,11 @@
 /*
  *  ERC32 Spurious Trap Handler
  *
- *  This is just enough of a trap handler to let us know what 
+ *  This is just enough of a trap handler to let us know what
  *  the likely source of the trap was.
  *
- *  Developed as part of the port of RTEMS to the ERC32 implementation 
- *  of the SPARC by On-Line Applications Research Corporation (OAR) 
+ *  Developed as part of the port of RTEMS to the ERC32 implementation
+ *  of the SPARC by On-Line Applications Research Corporation (OAR)
  *  under contract to the European Space Agency (ESA).
  *
  *  COPYRIGHT (c) 1995. European Space Agency.
@@ -60,33 +60,33 @@ rtems_isr bsp_spurious_handler(
      *  First the ones defined by the basic architecture
      */
 
-    case 0x00: 
+    case 0x00:
       DEBUG_puts( "reset" );
       break;
-    case 0x01: 
+    case 0x01:
       DEBUG_puts( "instruction access exception" );
       break;
-    case 0x02: 
+    case 0x02:
       DEBUG_puts( "illegal instruction" );
       break;
-    case 0x03: 
+    case 0x03:
       DEBUG_puts( "privileged instruction" );
       break;
-    case 0x04: 
+    case 0x04:
       DEBUG_puts( "fp disabled" );
       break;
-    case 0x07: 
+    case 0x07:
       DEBUG_puts( "memory address not aligned" );
       break;
-    case 0x08: 
+    case 0x08:
       DEBUG_puts( "fp exception" );
       break;
-    case 0x09: 
+    case 0x09:
       strcpy(line, "data access exception at 0x        " );
       itos(ERC32_MEC.First_Failing_Address, &line[27]);
       DEBUG_puts( line );
       break;
-    case 0x0A: 
+    case 0x0A:
       DEBUG_puts( "tag overflow" );
       break;
 
@@ -178,7 +178,7 @@ void bsp_spurious_initialize()
      */
 
      if (( trap == 5 || trap == 6 ) ||
-     	(( trap >= 0x11 ) && ( trap <= 0x1f )) || 
+     	(( trap >= 0x11 ) && ( trap <= 0x1f )) ||
      	(( trap >= 0x70 ) && ( trap <= 0x83 )))
       continue;
 
diff --git a/c/src/lib/libbsp/sparc/erc32/timer/timer.c b/c/src/lib/libbsp/sparc/erc32/timer/timer.c
index 6432b84982..5903dc484d 100644
--- a/c/src/lib/libbsp/sparc/erc32/timer/timer.c
+++ b/c/src/lib/libbsp/sparc/erc32/timer/timer.c
@@ -11,10 +11,10 @@
  *  http://www.rtems.com/license/LICENSE.
  *
  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
- *  Research Corporation (OAR) under contract to the European Space 
+ *  Research Corporation (OAR) under contract to the European Space
  *  Agency (ESA).
  *
- *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
+ *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
  *  European Space Agency.
  *
  *  $Id$
@@ -43,12 +43,12 @@ void Timer_initialize()
     Timer_driver_Is_initialized = TRUE;
   }
 
-  ERC32_MEC_Set_General_Purpose_Timer_Control( 
-    ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING | 
+  ERC32_MEC_Set_General_Purpose_Timer_Control(
+    ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING |
       ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER
   );
 
-  ERC32_MEC_Set_General_Purpose_Timer_Control( 
+  ERC32_MEC_Set_General_Purpose_Timer_Control(
     ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING
   );