Remove stray white spaces.

7 files changed, 61 insertions, 61 deletions

diff --git a/c/src/lib/libbsp/sh/gensh4/console/console.c b/c/src/lib/libbsp/sh/gensh4/console/console.c
index 1c85036672..358f632e77 100644
--- a/c/src/lib/libbsp/sh/gensh4/console/console.c
+++ b/c/src/lib/libbsp/sh/gensh4/console/console.c
@@ -159,10 +159,10 @@ console_first_open(int major, int minor, void *arg)
             args->iop->data1,       /* tty */
             minor+1,                /* channel */
             (console_mode == CONSOLE_MODE_INT));
-    
+
     if (sc == RTEMS_SUCCESSFUL)
         sc = sh4uart_reset(&sh4_uarts[minor]);
-    
+
     return sc;
 }
 
@@ -182,7 +182,7 @@ console_last_close(int major, int minor, void *arg)
 {
     if (console_mode != CONSOLE_MODE_IPL)
     /* working from gdb we should not disable port operations */
-        return sh4uart_disable(&sh4_uarts[minor], 
+        return sh4uart_disable(&sh4_uarts[minor],
 	        !(boot_mode == SH4_BOOT_MODE_IPL));
     else
 	return RTEMS_SUCCESSFUL;
@@ -200,7 +200,7 @@ console_last_close(int major, int minor, void *arg)
 void
 console_reserve_resources(rtems_configuration_table *configuration)
 {
-    if ((console_mode != CONSOLE_MODE_RAW) && 
+    if ((console_mode != CONSOLE_MODE_RAW) &&
             (console_mode != CONSOLE_MODE_IPL))
         rtems_termios_reserve_resources (configuration, 2);
 }
@@ -240,7 +240,7 @@ console_initialize(rtems_device_major_number major,
     if ((console_mode != CONSOLE_MODE_RAW) &&
                     (console_mode != CONSOLE_MODE_IPL))
         rtems_termios_initialize ();
-    
+
     /*
      * Register the devices
      */
@@ -272,7 +272,7 @@ console_initialize(rtems_device_major_number major,
             sc = sh4uart_reset(&sh4_uarts[1]);
 
         return sc;
-    }                        
+    }
 
     return RTEMS_SUCCESSFUL;
 }
@@ -355,7 +355,7 @@ console_close(rtems_device_major_number major,
         return rtems_termios_close (arg);
     else
         return RTEMS_SUCCESSFUL;
-}    
+}
 
 /* console_read --
  *     Read from the console device
@@ -432,7 +432,7 @@ console_write(rtems_device_major_number major,
             char *buf = argp->buffer;
             int count = argp->count;
             int i;
-            
+
             for (i = 0; i < count; i++)
             {
                 if (*buf == '\n')
diff --git a/c/src/lib/libbsp/sh/gensh4/hw_init/hw_init.c b/c/src/lib/libbsp/sh/gensh4/hw_init/hw_init.c
index befd2c1dfd..2e7d738ad4 100644
--- a/c/src/lib/libbsp/sh/gensh4/hw_init/hw_init.c
+++ b/c/src/lib/libbsp/sh/gensh4/hw_init/hw_init.c
@@ -39,12 +39,12 @@ early_hw_init(void)
 {
     /* Explicitly turn off the MMU */
     write32(0, SH7750_MMUCR);
-    
+
     /* Disable instruction and operand caches */
     write32(0, SH7750_CCR);
-    
+
     /* Setup Clock Generator */
-    /* 
+    /*
      * Input clock frequency is 16 MHz, MD0=1,
      * CPU clock frequency already selected to 96MHz.
      * Bus clock frequency should be set to 48 MHz, therefore divider 2
@@ -57,7 +57,7 @@ early_hw_init(void)
             SH7750_WTCSR_KEY, SH7750_WTCSR);
     write16(SH7750_WTCSR_MODE_IT | SH7750_WTCSR_CKS_DIV4096 |
             SH7750_WTCSR_KEY, SH7750_WTCSR);
-    
+
     /* Turn PLL1 on */
     write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
     write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL1EN, SH7750_FRQCR);
@@ -71,7 +71,7 @@ early_hw_init(void)
     /* Turn PLL2 on */
     write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
     write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL2EN, SH7750_FRQCR);
-    
+
     /* Bus State Controller Initialization */
     /*
      * Area assignments:
@@ -93,7 +93,7 @@ early_hw_init(void)
         SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM  /* Select Area 2 SDRAM type */
         /* Area 5,6 programmed as a SRAM interface (not PCMCIA) */,
         SH7750_BCR1);
-    
+
     write16(
         (SH7750_BCR2_SZ_8 << SH7750_BCR2_A0SZ_S) |  /* These bits is read-only
                                                        and set during reset */
@@ -105,7 +105,7 @@ early_hw_init(void)
         (SH7750_BCR2_SZ_32 << SH7750_BCR2_A1SZ_S) | /* GDC is 32-bit width */
         SH7750_BCR2_PORTEN,                         /* Use D32-D51 as a port */
         SH7750_BCR2);
-    
+
     write32(
         (0 << SH7750_WCR1_DMAIW_S) |  /* 0 required for SDRAM RAS down mode */
         (7 << SH7750_WCR1_A6IW_S) |   /* Area 6 not used */
@@ -125,9 +125,9 @@ early_hw_init(void)
         (SH7750_WCR2_WS15   << SH7750_WCR2_A4W_S) | /* Area 4 not used */
         (SH7750_WCR2_WS15   << SH7750_WCR2_A3W_S) | /*Area 3 not used*/
         (SH7750_WCR2_SDRAM_CAS_LAT2 << SH7750_WCR2_A2W_S) | /* SDRAM CL = 2 */
-        (SH7750_WCR2_WS15   << SH7750_WCR2_A1W_S) | /* Area 1 (GDC) 
+        (SH7750_WCR2_WS15   << SH7750_WCR2_A1W_S) | /* Area 1 (GDC)
                                                        requirements not known*/
-        (SH7750_WCR2_WS6    << SH7750_WCR2_A0W_S) | /* 4 wait states required 
+        (SH7750_WCR2_WS6    << SH7750_WCR2_A0W_S) | /* 4 wait states required
                                                        at 48MHz for 70ns mem.,
                                                        set closest greater */
         (SH7750_WCR2_BPWS7  << SH7750_WCR2_A0B_S),  /* burst mode disabled for
@@ -171,21 +171,21 @@ early_hw_init(void)
 
     /* Clear refresh timer counter */
     write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT);
-    
+
     /* Time between auto-refresh commands is 15.6 microseconds; refresh
        timer counter frequency is 12 MHz; 1.56e-5*1.2e7= 187.2, therefore
        program the refresh timer divider to 187 */
-    write16(SH7750_RTCOR_KEY | 187, SH7750_RTCOR); 
-    
+    write16(SH7750_RTCOR_KEY | 187, SH7750_RTCOR);
+
     /* Clear refresh counter */
     write16(SH7750_RFCR_KEY | 0, SH7750_RFCR);
-    
+
     /* Select refresh counter base frequency as bus frequency/4 = 12 MHz */
     write16(SH7750_RTCSR_CKS_CKIO_DIV4 | SH7750_RTCSR_KEY, SH7750_RTCSR);
 
     /* Initialize Memory Control Register; disable refresh */
     write32((MCRDEF & ~SH7750_MCR_RFSH) | SH7750_MCR_PALL, SH7750_MCR);
-    
+
     /* SDRAM power-up initialization require 100 microseconds delay after
        stable power and clock fed; 100 microseconds corresponds to 7 refresh
        intervals */
@@ -193,10 +193,10 @@ early_hw_init(void)
 
     /* Clear refresh timer counter */
     write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT);
-    
+
     /* Clear refresh counter */
     write16(SH7750_RFCR_KEY | 0, SH7750_RFCR);
-    
+
     /* Execute Precharge All command */
     write32(0, SH7750_SDRAM_MODE_A2_32BIT(0));
 
@@ -210,27 +210,27 @@ early_hw_init(void)
     /* SDRAM data width is 32 bit (4 bytes), cache line size is 32 bytes,
        therefore burst length is 8 (32 / 4) */
     write8(0,SH7750_SDRAM_MODE_A2_32BIT(
-        SDRAM_MODE_BL_8 | 
-        SDRAM_MODE_BT_SEQ |    /* Only sequential burst mode supported 
+        SDRAM_MODE_BL_8 |
+        SDRAM_MODE_BT_SEQ |    /* Only sequential burst mode supported
                                   in SH7750 */
         SDRAM_MODE_CL_2 |      /* CAS latency is 2 */
         SDRAM_MODE_OPC_BRBW)   /* Burst read/burst write */
     );
     /* Bus State Controller initialized now */
-    
+
     /* Disable DMA controller */
     write32(0, SH7750_DMAOR);
-    
+
     /* I/O port setup */
     /* Configure all port bits as output - to fasciliate debugging */
     write32(
-        SH7750_PCTRA_PBOUT(0)  | SH7750_PCTRA_PBOUT(1) | 
+        SH7750_PCTRA_PBOUT(0)  | SH7750_PCTRA_PBOUT(1) |
         SH7750_PCTRA_PBOUT(2)  | SH7750_PCTRA_PBOUT(3) |
-        SH7750_PCTRA_PBOUT(4)  | SH7750_PCTRA_PBOUT(5) | 
+        SH7750_PCTRA_PBOUT(4)  | SH7750_PCTRA_PBOUT(5) |
         SH7750_PCTRA_PBOUT(6)  | SH7750_PCTRA_PBOUT(7) |
-        SH7750_PCTRA_PBOUT(8)  | SH7750_PCTRA_PBOUT(9) | 
+        SH7750_PCTRA_PBOUT(8)  | SH7750_PCTRA_PBOUT(9) |
         SH7750_PCTRA_PBOUT(10) | SH7750_PCTRA_PBOUT(11) |
-        SH7750_PCTRA_PBOUT(12) | SH7750_PCTRA_PBOUT(13) | 
+        SH7750_PCTRA_PBOUT(12) | SH7750_PCTRA_PBOUT(13) |
         SH7750_PCTRA_PBOUT(14) | SH7750_PCTRA_PBOUT(15),
         SH7750_PCTRA);
     write32(
@@ -240,7 +240,7 @@ early_hw_init(void)
     /* Clear data in port */
     write32(0, SH7750_PDTRA);
     write32(0, SH7750_PDTRB);
-    
+
     /* Interrupt Controller Initialization */
     write16(SH7750_ICR_IRLM, SH7750_ICR); /* IRLs serves as an independent
                                              interrupt request lines */
@@ -254,7 +254,7 @@ early_hw_init(void)
     write16(
         (0 << SH7750_IPRB_WDT_S) |
         (0 << SH7750_IPRB_REF_S) |
-        (0 << SH7750_IPRB_SCI1_S), 
+        (0 << SH7750_IPRB_SCI1_S),
         SH7750_IPRB);
     write16(
         (0 << SH7750_IPRC_GPIO_S) |
@@ -265,17 +265,17 @@ early_hw_init(void)
 
 }
 
-/* 
+/*
  * cache_on --
- *      Enable instruction and operand caches 
+ *      Enable instruction and operand caches
  */
 void bsp_cache_on(void)
 {
     switch (boot_mode)
     {
         case SH4_BOOT_MODE_FLASH:
-            write32(SH7750_CCR_ICI | SH7750_CCR_ICE | 
-                    SH7750_CCR_OCI | SH7750_CCR_CB | SH7750_CCR_OCE, 
+            write32(SH7750_CCR_ICI | SH7750_CCR_ICE |
+                    SH7750_CCR_OCI | SH7750_CCR_CB | SH7750_CCR_OCE,
                     SH7750_CCR);
             break;
         case SH4_BOOT_MODE_IPL:
diff --git a/c/src/lib/libbsp/sh/gensh4/include/bsp.h b/c/src/lib/libbsp/sh/gensh4/include/bsp.h
index 2f61c6d539..26904aa82a 100644
--- a/c/src/lib/libbsp/sh/gensh4/include/bsp.h
+++ b/c/src/lib/libbsp/sh/gensh4/include/bsp.h
@@ -14,7 +14,7 @@
  *  This program is distributed in the hope that it will be useful,
  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * 
+ *
  *
  *  COPYRIGHT (c) 1998-2001.
  *  On-Line Applications Research Corporation (OAR).
@@ -140,7 +140,7 @@ extern void *CPU_Interrupt_stack_high ;
 extern uint32_t   boot_mode;
 #define SH4_BOOT_MODE_FLASH 0
 #define SH4_BOOT_MODE_IPL   1
-  
+
 /* miscellaneous stuff assumed to exist */
 
 extern rtems_configuration_table BSP_Configuration;
@@ -159,7 +159,7 @@ extern void bsp_cleanup( void );
 #define CONSOLE_DRIVER_TABLE_ENTRY \
   { console_initialize, console_open, console_close, \
       console_read, console_write, console_control }
- 
+
 /*
  * NOTE: Use the standard Clock driver entry
  */
diff --git a/c/src/lib/libbsp/sh/gensh4/include/coverhd.h b/c/src/lib/libbsp/sh/gensh4/include/coverhd.h
index 61a20c82f8..4bbc88857d 100644
--- a/c/src/lib/libbsp/sh/gensh4/include/coverhd.h
+++ b/c/src/lib/libbsp/sh/gensh4/include/coverhd.h
@@ -15,7 +15,7 @@
  *         all calling overhead including passing of arguments.
  *
  *
- * These are the figures tmoverhd.exe reported with gcc-2.95.1 -O4 
+ * These are the figures tmoverhd.exe reported with gcc-2.95.1 -O4
  * on a Hitachi SH7045F Evaluation Board with SH7045F at 29 MHz
  *
  * These results are assumed to be applicable to most SH7045/29MHz boards
@@ -27,7 +27,7 @@
  *  This program is distributed in the hope that it will be useful,
  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * 
+ *
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
diff --git a/c/src/lib/libbsp/sh/gensh4/include/sdram.h b/c/src/lib/libbsp/sh/gensh4/include/sdram.h
index 7cda7f5cdd..abf72f94e0 100644
--- a/c/src/lib/libbsp/sh/gensh4/include/sdram.h
+++ b/c/src/lib/libbsp/sh/gensh4/include/sdram.h
@@ -8,7 +8,7 @@
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
- * 
+ *
  * @(#) $Id$
  */
 
diff --git a/c/src/lib/libbsp/sh/gensh4/start/start.S b/c/src/lib/libbsp/sh/gensh4/start/start.S
index 9290fc07c7..0aa7ec66d8 100644
--- a/c/src/lib/libbsp/sh/gensh4/start/start.S
+++ b/c/src/lib/libbsp/sh/gensh4/start/start.S
@@ -19,7 +19,7 @@
  *  TGA Technologies, Inc.
  *  100 Pinnacle Way, Suite 140
  *  Norcross, GA 30071 U.S.A.
- *  
+ *
  *
  *  This modified file may be copied and distributed in accordance
  *  the above-referenced license. It is provided for critique and
@@ -74,7 +74,7 @@ fake_func:
         movt    r9      ! r9 == ! boot_mode
         neg     r9, r9
         add     #1, r9  ! r9 == boot_mode
-        
+
         ! what is in boot_mode?
         cmp/pl  r9      ! r9 > 0  ->  T = 1
 
@@ -84,7 +84,7 @@ fake_func:
 
 #if defined(START_HW_INIT)	/* from $RTEMS_BSP.cfg */
         ! Initialize minimal hardware
-        ! to run hw_init we need to calculate its address 
+        ! to run hw_init we need to calculate its address
         ! as it is before data coping
         mov.l	hw_init_k, r0
         mov.l   copy_start_k, r1
@@ -172,7 +172,7 @@ zero_bss:
         lds     r0,fpscr
 
 
-        ! call the mainline	
+        ! call the mainline
         mov #0,r4		! argc
         mov.l main_k,r0
         jsr @r0
@@ -213,7 +213,7 @@ _vbr_base_k:
 __VBR_Saved_k:
         .long   SYM(_VBR_Saved)
 stack_k:
-        .long	SYM(stack)	
+        .long	SYM(stack)
 __bss_start_k:
         .long   __bss_start
 __bss_end_k:
diff --git a/c/src/lib/libbsp/sh/gensh4/startup/bspstart.c b/c/src/lib/libbsp/sh/gensh4/startup/bspstart.c
index 1a8a434a68..f0b9f04ff8 100644
--- a/c/src/lib/libbsp/sh/gensh4/startup/bspstart.c
+++ b/c/src/lib/libbsp/sh/gensh4/startup/bspstart.c
@@ -26,11 +26,11 @@
 
 #include <bsp.h>
 #include <rtems/libio.h>
- 
+
 #include <rtems/libcsupport.h>
- 
+
 #include <string.h>
- 
+
 /*
  *  The original table from the application and our copy of it with
  *  some changes.
@@ -49,7 +49,7 @@ char *rtems_progname;
 /*
  *  Use the shared implementations of the following routines
  */
- 
+
 void bsp_postdriver_hook(void);
 void bsp_libc_init( void *, uint32_t, int );
 
@@ -65,11 +65,11 @@ void bsp_libc_init( void *, uint32_t, int );
  *      not yet initialized.
  *
  */
- 
+
 void bsp_pretasking_hook(void)
 {
     bsp_libc_init(&HeapStart, (char *)&HeapEnd - (char *)&HeapStart, 0);
- 
+
 #ifdef RTEMS_DEBUG
     rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
 #endif
@@ -84,10 +84,10 @@ void bsp_pretasking_hook(void)
 void bsp_start(void)
 {
   /*
-     For real boards you need to setup the hardware 
+     For real boards you need to setup the hardware
      and need to copy the vector table from rom to ram.
 
-     Depending on the board this can ether be done from inside the rom 
+     Depending on the board this can ether be done from inside the rom
      startup code, rtems startup code or here.
    */
 
@@ -111,10 +111,10 @@ void bsp_start(void)
    */
 
   BSP_Configuration.work_space_start = (void *) &WorkSpaceStart ;
-  BSP_Configuration.work_space_size  = 
-    (uint32_t) &WorkSpaceEnd - 
+  BSP_Configuration.work_space_size  =
+    (uint32_t) &WorkSpaceEnd -
     (uint32_t) &WorkSpaceStart ;
-  
+
   /*
    *  initialize the CPU table for this BSP
    */
@@ -124,7 +124,7 @@ void bsp_start(void)
   _CPU_Interrupt_stack_high = &CPU_Interrupt_stack_high ;
 
   /* This isn't used anywhere */
-  Cpu_table.interrupt_stack_size = 
+  Cpu_table.interrupt_stack_size =
     (uint32_t) (&CPU_Interrupt_stack_high) -
     (uint32_t) (&CPU_Interrupt_stack_low) ;
 #endif