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authorPragnesh Patel <pragnesh.patel@sifive.com>2019-10-22 10:20:05 +0000
committerSebastian Huber <sebastian.huber@embedded-brains.de>2019-10-23 08:11:50 +0200
commita7f5e42cc5234f239a01b8f69847ebb018710948 (patch)
tree75d1abe5128bc54b678580c7d2d03b6823568e70 /c/src/lib/libbsp/riscv/riscv/Makefile.am
parentlibdebugger/arm: Clean up the building on arm variants. (diff)
downloadrtems-a7f5e42cc5234f239a01b8f69847ebb018710948.tar.bz2
riscv: add freedom E310 Arty A7 bsp
Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board. Update #3785. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Diffstat (limited to 'c/src/lib/libbsp/riscv/riscv/Makefile.am')
-rw-r--r--c/src/lib/libbsp/riscv/riscv/Makefile.am8
1 files changed, 8 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/riscv/riscv/Makefile.am b/c/src/lib/libbsp/riscv/riscv/Makefile.am
index 34bedf844f..15b0865306 100644
--- a/c/src/lib/libbsp/riscv/riscv/Makefile.am
+++ b/c/src/lib/libbsp/riscv/riscv/Makefile.am
@@ -46,7 +46,11 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspgetworkarea-defa
librtemsbsp_a_SOURCES +=../../../../../../bsps/riscv/riscv/clock/clockdrv.c
# Timer
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/btimer/btimer-cpucounter.c
+#else
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/btimer/btimer-stub.c
+#endif
# IRQ
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c
@@ -60,6 +64,10 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termio
librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/riscv/console/console-config.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/riscv/console/htif.c
+#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/riscv/console/fe310-uart.c
+#endif
+
if HAS_SMP
librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/riscv/start/bspsmp.c
endif