fix timer support, some reworks

5 files changed, 67 insertions, 50 deletions

diff --git a/c/src/lib/libbsp/powerpc/gen5200/ChangeLog b/c/src/lib/libbsp/powerpc/gen5200/ChangeLog
index 828b564a73..95a6cf4d41 100644
--- a/c/src/lib/libbsp/powerpc/gen5200/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/gen5200/ChangeLog
@@ -1,3 +1,8 @@
+2010-03-25      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* configure.ac, include/bsp.h, console/console.c, start/start.S:
+	move more configuration constants to configure.ac
+
 2010-03-16      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
 
 	* clock/*, startup/bspstart.c, Makefile.am: switch this BSP to use
diff --git a/c/src/lib/libbsp/powerpc/gen5200/configure.ac b/c/src/lib/libbsp/powerpc/gen5200/configure.ac
index 44852d60a7..6b07dcbeb4 100644
--- a/c/src/lib/libbsp/powerpc/gen5200/configure.ac
+++ b/c/src/lib/libbsp/powerpc/gen5200/configure.ac
@@ -25,25 +25,68 @@ RTEMS_BSPOPTS_HELP([INSTRUCTION_CACHE_ENABLE],
 [If defined, the instruction cache will be enabled after address translation
  is turned on.])
 
+RTEMS_BSPOPTS_SET([HAS_UBOOT],[icecube],[1])
+RTEMS_BSPOPTS_SET([HAS_UBOOT],[pm520_*],[1])
+RTEMS_BSPOPTS_HELP([HAS_UBOOT],
+[If defined, board boots via U-Boot])
+
 RTEMS_BSPOPTS_SET([BENCHMARK_IRQ_PROCESSING],[*],[0])
 RTEMS_BSPOPTS_HELP([BENCHMARK_IRQ_PROCESSING],
-[If defined, enable code to benchmark IRQ processing.])
+[If set to !0, enable code to benchmark IRQ processing.])
 
 RTEMS_BSPOPTS_SET([ALLOW_IRQ_NESTING],[icecube],[0])
 RTEMS_BSPOPTS_SET([ALLOW_IRQ_NESTING],[*],[1])
 RTEMS_BSPOPTS_HELP([ALLOW_IRQ_NESTING],
-[If defined, allow nested IRQ processing.])
+[If set to !0, allow nested IRQ processing.])
 
 RTEMS_BSPOPTS_SET([BSP_PRESS_KEY_FOR_RESET],[icecube],[1])
+RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[pm520_cr825],[1])
 RTEMS_BSPOPTS_SET([BSP_PRESS_KEY_FOR_RESET],[*],[0])
 RTEMS_BSPOPTS_HELP([BSP_PRESS_KEY_FOR_RESET],
-[If defined, print a message and wait until pressed before resetting
+[If set to !0, print a message and wait until pressed before resetting
  board when application exits.])
 
 RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[icecube],[1])
+RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[pm520_*],[1])
+RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[brs5l],[1])
 RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[*],[0])
 RTEMS_BSPOPTS_HELP([BSP_RESET_BOARD_AT_EXIT],
-[If defined, reset the board when the application exits.])
+[If set to !0, reset the board when the application exits.])
+
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[pm520_ze30],[0x337F3F77])
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[pm520_ze30],[0x01552114])
+
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[pm520_cr825],[0x330F0F77])
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[pm520_cr825],[0x01050444])
+
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[brs5l],[0xb30F0F77])
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[brs5l],[0x91050444])
+
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[icecube],[0x330F0F77])
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[icecube],[0x01050444])
+
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[*],[0x330F0F77])
+RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[*],[0x01050444])
+
+RTEMS_BSPOPTS_HELP([BSP_GPIOPCR_INITMASK],
+[defines the bits modified in the MPC5200 GPIOPCR register during init. 
+ Must match the hardware requirements])
+RTEMS_BSPOPTS_HELP([BSP_GPIOPCR_INITVAL],
+[defines the bit values written in the MPC5200 GPIOPCR register during init. 
+ Must match the hardware requirements])
+
+## on ze30, we have PSC1/4/5/6 ...
+RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[pm520_ze30],[0x39])
+## on cr825, we have PSC1/2/3
+RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[pm520_cr825],[0x07])
+## on brs5l, we have PSC1/2/3
+RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[brs5l],[0x07])
+## on icecube, we only have PSC1
+RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[icecube],[0x01])
+RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[*],[0x01])
+RTEMS_BSPOPTS_HELP([BSP_UART_AVAIL_MASK],
+[bit mask to specify the UARTS (PSCs), which should be enabled on this board. 
+ Must match the hardware requirements. PSC1 corresponds to the LSB])
 
 RTEMS_BSPOPTS_SET([PM520_ZE30],[pm520_ze30],[1])
 RTEMS_BSPOPTS_HELP([PM520_ZE30],
diff --git a/c/src/lib/libbsp/powerpc/gen5200/console/console.c b/c/src/lib/libbsp/powerpc/gen5200/console/console.c
index 84c38424e6..11543a907a 100644
--- a/c/src/lib/libbsp/powerpc/gen5200/console/console.c
+++ b/c/src/lib/libbsp/powerpc/gen5200/console/console.c
@@ -115,7 +115,7 @@
 #define PSC5_MINOR      4
 #define PSC6_MINOR      5
 
-uint32_t mpc5200_uart_avail_mask = GEN5200_UART_AVAIL_MASK;
+uint32_t mpc5200_uart_avail_mask = BSP_UART_AVAIL_MASK;
 
 #if defined(UARTS_USE_TERMIOS_INT)
   uint8_t psc_minor_to_irqname[NUM_PORTS] = {
diff --git a/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h b/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h
index 7ba3538da5..5bcae681cb 100644
--- a/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h
+++ b/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h
@@ -71,39 +71,22 @@ LINKER_SYMBOL(MBAR);
  */
 #if defined(PM520_ZE30)
 #define PM520
-#define GPIOPCR_INITMASK 0x337F3F77
-#define GPIOPCR_INITVAL  0x01552114
-/* we have PSC1/4/5/6 */
-/* #define GEN5200_UART_AVAIL_MASK 0x39 */
-#define GEN5200_UART_AVAIL_MASK 0x39
 #endif
 /*
  * for PM520 mdule on a CR825 carrier
  */
 #if defined(PM520_CR825)
 #define PM520
-#define GPIOPCR_INITMASK 0x330F0F77
-#define GPIOPCR_INITVAL  0x01050444
-/* we have PSC1/2/3*/
-#define GEN5200_UART_AVAIL_MASK 0x07
 #endif
 
 #if defined(BRS5L)
 /*
  * IMD Custom Board BRS5L
  */
-#define GPIOPCR_INITMASK 0xb30F0F77
-#define GPIOPCR_INITVAL  0x91050444
-/* we have PSC1/2/3 */
-#define GEN5200_UART_AVAIL_MASK 0x07
-
-/* we need the low level initialization in start.S*/
-#define NEED_LOW_LEVEL_INIT
 
 #define HAS_NVRAM_93CXX
-#elif defined (PM520)
 
-#define HAS_UBOOT
+#elif defined (PM520)
 
 #elif defined (icecube)
 /*
@@ -113,15 +96,6 @@ LINKER_SYMBOL(MBAR);
  *     Embedded Planet EP5200
  */
 
-#define HAS_UBOOT
-
-/* These are copied from PM520 but seem to work so OK */
-#define GPIOPCR_INITMASK 0x330F0F77
-#define GPIOPCR_INITVAL  0x01050444
-
-/* we only have PSC1 */
-#define GEN5200_UART_AVAIL_MASK 0x01
-
 #else
 #error "board type not defined"
 #endif
@@ -147,6 +121,12 @@ extern "C" {
 #include <u-boot.h>
 
 extern bd_t bsp_uboot_board_info;
+#else
+
+/* we need the low level initialization in start.S*/
+#define NEED_LOW_LEVEL_INIT
+
+
 #endif
 
 /*
diff --git a/c/src/lib/libbsp/powerpc/gen5200/start/start.S b/c/src/lib/libbsp/powerpc/gen5200/start/start.S
index a5206351f6..d68038aec5 100644
--- a/c/src/lib/libbsp/powerpc/gen5200/start/start.S
+++ b/c/src/lib/libbsp/powerpc/gen5200/start/start.S
@@ -182,10 +182,10 @@ start:
    	LWI	r31, MBAR			/* set r31 to current MBAR */
 	/* init GPIOPCR */
 	lwz	r29,GPIOPCR(r31)
-	LWI	r30, GPIOPCR_INITMASK
+	LWI	r30, BSP_GPIOPCR_INITMASK
 	not	r30,r30
 	and	r29,r29,r30
-	LWI	r30, GPIOPCR_INITVAL
+	LWI	r30, BSP_GPIOPCR_INITVAL
 	or	r29,r29,r30
 	stw	r29, GPIOPCR(r31)
 
@@ -237,7 +237,7 @@ start:
 	stw	r30, CSBOOTROM(r31)	 	/* Set CSBOOTROM */
 
 
-#endif
+#endif /* BRS5L */
 
 
 	/* FIXME: map BOOT ROM into final location with CS0 registers */
@@ -397,7 +397,7 @@ skip_ROM_start:
 
         bl      clr_mem				/* Clear onchip SRAM */
 
-#endif /* defined(BRS5L) */
+#endif /* defined(NEED_LOW_LEVEL_INIT) */
 /* clear .bss section (unique for ROM startup) */
 	LWI	r30, bsp_section_bss_start	/* get start address of bss section */
         LWI	r29, bsp_section_bss_size  	/* get size of bss section */
@@ -425,13 +425,13 @@ skip_ROM_start:
 
         bl      SYM (boot_card)			/* Call the first C routine */
 
-#if defined(BRS5L)
 twiddle:
 	b	twiddle				/* We don't expect to return from boot_card but if we do */
 						/* wait here for watchdog to kick us into hard reset     */
 
+#if defined(NEED_LOW_LEVEL_INIT)
 SDRAM_init:
-#if defined (BRS5L)
+#if defined(BRS5L)
       /* set GPIO_WKUP7 pin low for 66MHz buffering */
       /* or high for 133MHz registered buffering    */
 	LWI	r30, 0x80000000
@@ -458,17 +458,11 @@ SDRAM_init:
 	stw	r29,GPIOPCR(r31)
 
 #endif
-#if 0
-	LWI	r30, 0xC2222600			/* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
-	stw	r30, CFG1(r31)			/* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
-						/* Refr.2No-Read delay=0x06, Write latency=0x0 */
-#else
 	/* See Erratum 342/339 in MPC5200_Errata_L25R_3_June.pdf:	*/
 	/* set 5 delays to their maximum to support two banks           */
 	LWI	r30, 0xCC222600			/* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
 	stw	r30, CFG1(r31)			/* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
 						/* Refr.2No-Read delay=0x06, Write latency=0x0 */
-#endif
 
 	LWI	r30, 0xCCC70004			/* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
 	stw	r30, CFG2(r31)			/* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
@@ -559,7 +553,7 @@ copy_image_byte:
 
 copy_image_end:
 	blr
-#endif /* defined(BRS5L) */
+#endif /* defined(NEED_LOW_LEVEL_INIT) */
 
 FID_DCache:
 	mflr	r26
@@ -643,11 +637,6 @@ FPU_init:
 	SETBITS r30, r29, MSR_FP
 	mtmsr	r30				/* enable FPU and FPU exceptions */
 
-#if 0
-	LA	r29, bsp_ram_start
-	stw	r29, 0x0(r29)
-#endif
-
 	lfd 	f0, 0(r29)
 	fmr 	f1, f0
 	fmr 	f2, f0