2004-04-12 David Querbach <querbach@realtime.bc.ca>

	* .cvsignore, ChangeLog, Makefile.am, README, bsp_specs, configure.ac,
	times, clock/p_clock.c, console/console.c, include/.cvsignore,
	include/bsp.h, include/coverhd.h, irq/irq.h, startup/bspstart.c,
	startup/iss555.c, startup/linkcmds, startup/start.S,
	wrapup/.cvsignore, wrapup/Makefile.am: New files.

4 files changed, 1085 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/powerpc/ss555/startup/bspstart.c b/c/src/lib/libbsp/powerpc/ss555/startup/bspstart.c
new file mode 100644
index 0000000000..b1465298a6
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ss555/startup/bspstart.c
@@ -0,0 +1,203 @@
+/*  bspstart.c
+ *
+ *  This set of routines starts the application.  It includes application,
+ *  board, and monitor specific initialization and configuration.
+ *  The generic CPU dependent initialization has been performed
+ *  before this routine is invoked.
+ *
+ *  COPYRIGHT (c) 1989-1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  SS555 port sponsored by Defence Research and Development Canada - Suffield
+ *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
+ *
+ *  Derived from c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c:
+ *
+ *  Modifications for MBX860:
+ *  Copyright (c) 1999, National Research Council of Canada
+ *
+ *  $Id$
+ */
+
+#include <string.h>
+
+#include <rtems/libio.h>
+#include <rtems/libcsupport.h>
+#include <rtems/bspIo.h>
+
+#include <libcpu/cpuIdent.h>
+#include <libcpu/spr.h>
+
+#include <bsp/irq.h>
+#include <bsp.h>
+
+
+SPR_RW(SPRG0)
+SPR_RW(SPRG1)
+
+/*
+ *  The original table from the application (in ROM) and our copy of it with
+ *  some changes. Configuration is defined in <confdefs.h>. Make sure that
+ *  our configuration tables are uninitialized so that they get allocated in
+ *  the .bss section (RAM).
+ */
+extern rtems_configuration_table Configuration;
+extern unsigned long intrStackPtr;
+rtems_configuration_table  BSP_Configuration;
+
+rtems_cpu_table Cpu_table;
+
+char *rtems_progname;
+
+/*
+ *  Use the shared implementations of the following routines.
+ *  Look in rtems/c/src/lib/libbsp/shared/bsppost.c and
+ *  rtems/c/src/lib/libbsp/shared/bsplibc.c.
+ */
+void bsp_postdriver_hook(void);
+void bsp_libc_init( void *, unsigned32, int );
+
+void BSP_panic(char *s)
+{
+  printk("%s PANIC %s\n",_RTEMS_version, s);
+  __asm__ __volatile ("sc"); 
+}
+
+void _BSP_Fatal_error(unsigned int v)
+{
+  printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
+  __asm__ __volatile ("sc"); 
+}
+
+/*
+ *  bsp_pretasking_hook
+ *
+ *  Called when RTEMS initialization is complete but before interrupts and
+ *  tasking are enabled. Used to setup libc and install any BSP extensions.
+ *
+ *  Must not use libc (to do io) from here, since drivers are not yet
+ *  initialized.
+ *
+ *  Installed in the rtems_cpu_table defined in
+ *  rtems/c/src/exec/score/cpu/powerpc/rtems/new-exceptions/cpu.h by main()
+ *  below.  Called from rtems_initialize_executive() defined in
+ *  rtems/c/src/exec/sapi/src/init.c
+ *
+ *  Input parameters: NONE
+ *
+ *  Output parameters: NONE
+ *
+ *  Return values: NONE
+ */
+void bsp_pretasking_hook(void)
+{
+  /* 
+   *  These are assigned addresses in the linkcmds file for the BSP. This
+   *  approach is better than having these defined as manifest constants and
+   *  compiled into the kernel, but it is still not ideal when dealing with
+   *  multiprocessor configuration in which each board as a different memory
+   *  map. A better place for defining these symbols might be the makefiles.
+   *  Consideration should also be given to developing an approach in which
+   *  the kernel and the application can be linked and burned into ROM
+   *  independently of each other.
+   */
+    unsigned char *_HeapStart = 
+      (char*)BSP_Configuration.work_space_start 
+           + BSP_Configuration.work_space_size;
+    extern unsigned char _HeapEnd[];
+
+    bsp_libc_init( _HeapStart, _HeapEnd - _HeapStart, 0 );
+  
+#ifdef RTEMS_DEBUG
+  rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
+#endif
+}
+
+
+/*
+ *  bsp_start()
+ *
+ *  Board-specific initialization code. Called from the generic boot_card()
+ *  function defined in rtems/c/src/lib/libbsp/shared/main.c. That function
+ *  does some of the board independent initialization. It is called from the
+ *  SS555 entry point _start() defined in
+ *  rtems/c/src/lib/libbsp/powerpc/ss555/startup/start.S
+ *
+ *  _start() has set up a stack, has zeroed the .bss section, has set up the
+ *  .data section from contents stored in ROM, has turned off interrupts,
+ *  and placed the processor in the supervisor mode.  boot_card() has left
+ *  the processor in that state when bsp_start() was called.
+ *
+ *  Input parameters: NONE
+ *
+ *  Output parameters: NONE
+ *
+ *  Return values: NONE
+ */
+void bsp_start(void)
+{
+  extern char _WorkspaceBase[];
+  
+  ppc_cpu_id_t myCpu;
+  ppc_cpu_revision_t myCpuRevision;
+  register unsigned char* intrStack;
+  
+  /*
+   * Get CPU identification dynamically.  Note that the get_ppc_cpu_type()
+   * function stores the result in global variables so that it can be used
+   * later.
+   */
+  myCpu 	= get_ppc_cpu_type();
+  myCpuRevision = get_ppc_cpu_revision();
+
+  /*
+   * Initialize some SPRG registers related to irq handling
+   */
+  intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE);
+  _write_SPRG1((unsigned int)intrStack);
+  /* signal them that we have fixed PR288 - eventually, this should go away */
+  _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
+
+  /*
+   * Install our own set of exception vectors
+   */
+  initialize_exceptions();
+
+  /*
+   *  Allocate the memory for the RTEMS Work Space.  This can come from
+   *  a variety of places: hard coded address, malloc'ed from outside
+   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
+   *  typically done by stock BSPs) by subtracting the required amount
+   *  of work space from the last physical address on the CPU board.
+   *
+   *  In this case, the memory is not malloc'ed.  It is just
+   *  "pulled from the air".
+   */
+  BSP_Configuration.work_space_start = _WorkspaceBase;
+
+  /*
+   *  initialize the CPU table for this BSP
+   */
+  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
+  Cpu_table.postdriver_hook = bsp_postdriver_hook;
+  if( Cpu_table.interrupt_stack_size < 4 * 1024 )
+      Cpu_table.interrupt_stack_size = 4 * 1024;
+
+  Cpu_table.clicks_per_usec = BSP_CRYSTAL_HZ / 4 / 1000000;
+  Cpu_table.clock_speed = BSP_CLOCK_HZ;	/* for SCI baud rate generator */
+
+  /* 
+   * Call this in case we use TERMIOS for console I/O
+   */
+  m5xx_uart_reserve_resources( &BSP_Configuration );
+
+  /*
+   * Initalize RTEMS IRQ system
+   */
+  BSP_rtems_irq_mng_init(0);
+}
+
diff --git a/c/src/lib/libbsp/powerpc/ss555/startup/iss555.c b/c/src/lib/libbsp/powerpc/ss555/startup/iss555.c
new file mode 100644
index 0000000000..34731848d2
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ss555/startup/iss555.c
@@ -0,0 +1,149 @@
+/*
+ *  iss555.c
+ *
+ *  Intec SS555 initialization routines.
+ *
+ *  SS555 port sponsored by Defence Research and Development Canada - Suffield
+ *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
+ *
+ *  Derived from c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c:
+ *
+ *  Copyright (c) 1999, National Research Council of Canada
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp.h>
+
+SPR_RW(ICTRL);
+SPR_RW(DEC);
+SPR_RW(TBWU);
+SPR_RW(TBWL);
+SPR_RO(IMMR);
+SPR_RW(MI_GRA);
+SPR_RW(L2U_GRA);
+SPR_RW(BBCMCR);
+
+
+/*
+ *  Initialize SS555
+ */
+void _InitSS555 (void)
+{
+  register unsigned32 plprcr, msr;
+
+  /*
+   * Initialize the System Protection Control Register (SYPCR).
+   * The SYPCR can only be written once after Reset.
+   */
+  usiu.sypcr = 
+      USIU_SYPCR_SWTC(WATCHDOG_TIMEOUT)	/* set watchdog timeout */
+    | USIU_SYPCR_BMT(0xFF) 		/* set bus monitor timeout */
+    | USIU_SYPCR_BME 			/* enable bus monitor */
+    | USIU_SYPCR_SWF			/* watchdog halted in freeze */
+#if WATCHDOG_TIMEOUT != 0xFFFF
+    | USIU_SYPCR_SWE			/* enable watchdog */
+#endif
+    | USIU_SYPCR_SWRI			/* watchdog forces reset */
+    | USIU_SYPCR_SWP;			/* prescale watchdog by 2048 */
+
+  TICKLE_WATCHDOG();			/* restart watchdog timer */
+  
+  /* 
+   * Re-tune the PLL to the desired system clock frequency.
+   */
+  usiu.plprck = USIU_UNLOCK_KEY;	/* unlock PLPRCR */
+  usiu.plprcr = 
+      USIU_PLPRCR_TEXPS			/* assert TEXP always */
+    | USIU_PLPRCR_MF(BSP_CLOCK_HZ / BSP_CRYSTAL_HZ);
+  					/* PLL multiplication factor */
+  usiu.plprck = 0;			/* lock PLPRCR */
+
+  while (((plprcr = usiu.plprcr) & USIU_PLPRCR_SPLS) == 0)
+    ;					/* wait for PLL to re-lock */
+    
+  /* 
+   * Enable the timebase and decrementer, then initialize decrementer
+   * register to a large value to guarantee that a decrementer interrupt
+   * will not be generated before the kernel is fully initialized. 
+   * Initialize the timebase register to zero.
+   */
+  usiu.tbscrk = USIU_UNLOCK_KEY;
+  usiu.tbscr |= USIU_TBSCR_TBE;		/* enable time base and decrementer */
+  usiu.tbscrk = 0;
+
+  usiu.tbk = USIU_UNLOCK_KEY;
+  _write_DEC(0x7FFFFFFF);
+  _write_TBWU(0x00000000 );
+  _write_TBWL(0x00000000 );
+  usiu.tbk = 0;
+
+  /*
+   * Run the Inter-Module Bus at full speed.
+   */
+  imb.uimb.umcr &= ~UIMB_UMCR_HSPEED;
+  
+  /*
+   * Initialize Memory Controller for External RAM
+   *
+   * Initialize the Base and Option Registers (BR0-BR7 and OR0-OR7).  Note
+   * that for all chip selects, ORx should be programmed before BRx.
+   *
+   * If booting from internal flash ROM, configure the external RAM to
+   * extend the internal RAM.  If booting from external RAM, leave it at
+   * zero but set it up appropriately.
+   */
+  extern char int_ram_top[];		/* top of internal ram */
+                      
+  usiu.memc[0]._or =
+      USIU_MEMC_OR_512K			/* bank size */
+    | USIU_MEMC_OR_SCY(0)		/* wait states in first beat of burst */
+    | USIU_MEMC_OR_BSCY(0);		/* wait states in subsequent beats */
+  		       
+  usiu.memc[0]._br =
+      USIU_MEMC_BR_BA(_read_IMMR() & IMMR_FLEN 
+        ? (rtems_unsigned32)int_ram_top : 0)	/* base address */
+    | USIU_MEMC_BR_PS32			/* 32-bit data bus */
+    | USIU_MEMC_BR_TBDIP		/* toggle bdip */
+    | USIU_MEMC_BR_V;			/* base register valid */
+  
+  /*
+   * Initialize Memory Controller for External CPLD
+   *
+   * The SS555 board includes a CPLD to control on-board features and
+   * off-board devices.  (Configuration taken from Intec's hwhook.c)
+   */
+  usiu.memc[3]._or =
+      USIU_MEMC_OR_16M			/* bank size */
+    | USIU_MEMC_OR_CSNT			/* negate CS/WE early */
+    | USIU_MEMC_OR_ACS_HALF		/* assert CS half cycle after address */
+    | USIU_MEMC_OR_SCY(15)		/* wait states in first beat of burst */
+    | USIU_MEMC_OR_TRLX;		/* relaxed timing */	
+
+  usiu.memc[3]._br =
+      USIU_MEMC_BR_BA(&cpld)		/* base address */
+    | USIU_MEMC_BR_PS16			/* 16-bit data bus */
+    | USIU_MEMC_BR_BI			/* inhibit bursting */
+    | USIU_MEMC_BR_V;			/* base register valid */
+  
+  /*
+   * Disable show cycles and serialization so that burst accesses will work
+   * properly.  A different value, such as 0x0, may be more appropriate for
+   * debugging, but can be set with the debugger, if needed.
+   */
+  _write_ICTRL(0x00000007);
+	
+  /*
+   * Set up Burst Buffer Controller (BBC)
+   */
+  _write_BBCMCR(
+      BBCMCR_ETRE			/* enable exception relocation */
+    | BBCMCR_BE);			/* enable burst accesses */
+  _isync;
+
+  _CPU_MSR_GET(msr);
+  msr |= MSR_IP;		/* set prefix for exception relocation */  
+  _CPU_MSR_SET(msr);
+}
diff --git a/c/src/lib/libbsp/powerpc/ss555/startup/linkcmds b/c/src/lib/libbsp/powerpc/ss555/startup/linkcmds
new file mode 100644
index 0000000000..f316621ebc
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ss555/startup/linkcmds
@@ -0,0 +1,320 @@
+/*
+ * Linker command file for Intec SS555 board
+ *
+ * When debugging, we assume that the internal flash ROM will be replaced by
+ * the external RAM on the SS555 board.  All sections are stacked starting
+ * at address zero.  Nothing is placed in the internal RAM, since it's not
+ * contiguous with the external SRAM when the external RAM is placed at
+ * zero.
+ *
+ * For final production, we assume that the .text section will be burned
+ * into flash ROM starting at address zero.  The .data, .bss, heap, and
+ * workspace will reside in RAM, starting at the beginning of the internal
+ * RAM.  The system startup code will configure the external RAM to begin
+ * where the internal RAM ends, so as to make one large RAM block.
+ *
+ * Debugging mode is chosen when the RTEMS_DEBUG symbol is defined.  The
+ * RTEMS_DEBUG symbol is defined in the bsp_specs file whenever make(1) is
+ * invoked with VARIANT=DEBUG.
+ *
+ *  $Id$
+ */
+
+OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc", "elf32-powerpc")
+OUTPUT_ARCH(powerpc) 
+ENTRY(start)
+
+int_ram_org	= 0x003F9800;		/* base of internal RAM */
+int_ram_top	= 0x00400000;		/* top of internal RAM */
+ext_ram_size	= 0x00080000;		/* size of external RAM */
+
+
+SECTIONS
+{
+  .vectors 0x0:
+  {
+    /*
+     * For the MPC555, we use the compressed vector table format which puts
+     * all of the exception vectors before 0x100.
+     */ 
+    *(.vectors)
+  }
+
+  .text 0x100:
+  {
+    /* Read-only sections, merged into text segment: */
+    
+    text.start = .;
+
+    /* Entry point is the .entry section */
+    *(.entry)
+    *(.entry2)
+
+    /* Actual code */
+    *(.text)
+    *(.text.*)
+	     
+    /* C++ constructors/destructors */
+    *(.gnu.linkonce.t*)
+	     
+    /*  Initialization and finalization code.
+     *
+     *  Various files can provide initialization and finalization functions.
+     *  The bodies of these functions are in .init and .fini sections. We
+     *  accumulate the bodies here, and prepend function prologues from
+     *  ecrti.o and function epilogues from ecrtn.o. ecrti.o must be linked
+     *  first; ecrtn.o must be linked last. Because these are wildcards, it
+     *  doesn't matter if the user does not actually link against ecrti.o and
+     *  ecrtn.o; the linker won't look for a file to match a wildcard.  The
+     *  wildcard also means that it doesn't matter which directory ecrti.o
+     *  and ecrtn.o are in. 
+     */
+    PROVIDE (_init = .);
+    *ecrti.o(.init)
+    *(.init)
+    *ecrtn.o(.init)
+    
+    PROVIDE (_fini = .);
+    *ecrti.o(.fini)
+    *(.fini)
+    *ecrtn.o(.init)
+
+    /* 
+     *  C++ constructors and destructors for static objects.
+     *  PowerPC EABI does not use crtstuff yet, so we build "old-style"
+     *  constructor and destructor lists that begin with the list length
+     *  end terminate with a NULL entry.
+     */
+    PROVIDE (__CTOR_LIST__ = .);	     
+    /* LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) */
+    *crtbegin.o(.ctors)
+    *(.ctors)
+    *crtend.o(.ctors)
+    LONG(0)
+    PROVIDE (__CTOR_END__ = .);
+	
+    PROVIDE (__DTOR_LIST__ = .);
+    /* LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) */
+    *crtbegin.o(.dtors)
+    *(.dtors)
+    *crtend.o(.dtors)
+    LONG(0)
+    PROVIDE (__DTOR_END__ = .);
+	
+    /*
+     * Special FreeBSD sysctl sections.
+     */
+    . = ALIGN (16);
+    __start_set_sysctl_set = .;
+    *(set_sysctl_*);
+    __stop_set_sysctl_set = ABSOLUTE(.);
+    *(set_domain_*);
+    *(set_pseudo_*);
+
+    /* Exception frame info */
+    *(.eh_frame)
+
+    /* Miscellaneous read-only data */
+    _rodata_start = . ;
+    *(.gnu.linkonce.r*)
+    *(.lit)
+    *(.shdata)
+    *(.rodata*)
+    *(.rodata1)
+    *.(eh_frame)
+    *(.descriptors)
+    *(rom_ver)
+    _erodata = .;
+
+    /* Various possible names for the end of the .text section */
+    etext = ALIGN(0x10);
+    _etext = .;
+    _endtext = .;
+    text.end = .;
+    PROVIDE (etext = .);
+    PROVIDE (__etext = .);
+
+    /* 
+     * .data section contents, copied to RAM at system startup. 
+     */
+    . = ALIGN(0x20);
+    data.contents.start = .;
+  }
+  text.size = text.end - text.start;
+
+  /*
+   * If debugging, stack the read/write sections directly after the text
+   * section.  Otherwise, stack the read/write sections starting at base of
+   * internal RAM.
+   */
+  . = DEFINED(RTEMS_DEBUG) ? . : int_ram_org;
+ 
+  .data : AT (data.contents.start)
+  {
+    data.start = .;
+    
+    *(.data)
+    *(.data.*)
+    *(.data1)
+    
+    PROVIDE (__SDATA_START__ = .);
+    *(.sdata)
+    *(.gnu.linkonce.d*)
+    *(.gnu.linkonce.s.*)
+    PROVIDE (__SDATA_END__ = .);
+    
+    PROVIDE (__EXCEPT_START__ = .);
+    *(.gcc_except_table)
+    PROVIDE (__EXCEPT_END__ = .);
+    
+    PROVIDE(__GOT_START__ = .);
+    *(.got.plt) 
+    *(.got)
+    PROVIDE(__GOT_END__ = .);
+	
+    *(.got1)
+    
+    PROVIDE (__GOT2_START__ = .);
+    PROVIDE (_GOT2_START_ = .);
+    *(.got2)
+    PROVIDE (__GOT2_END__ = .);
+    PROVIDE (_GOT2_END_ = .);
+	
+    PROVIDE (__FIXUP_START__ = .);
+    PROVIDE (_FIXUP_START_ = .);
+    *(.fixup)
+    PROVIDE (_FIXUP_END_ = .);
+    PROVIDE (__FIXUP_END__ = .);
+
+    /*  We want the small data sections together, so single-instruction
+     *   offsets can access them all.
+     */
+    PROVIDE (__SDATA2_START__ = .);
+    *(.sdata2)
+    *(.gnu.linkonce.s2.*)
+    PROVIDE (__SDATA2_END__ = .);
+
+    data.end = .;
+  }
+  data.size = data.end - data.start;
+	
+  .bss :
+  {
+    bss.start = .;
+	
+    PROVIDE (__SBSS2_START__ = .);
+    *(.sbss2)
+    PROVIDE (__SBSS2_END__ = .);
+	
+    PROVIDE (__SBSS_START__ = .);
+    *(.sbss)
+    PROVIDE (__SBSS_END__ = .);
+
+    *(.bss) 
+    *(COMMON)
+
+    . = ALIGN(4);
+    bss.end = .;
+  }
+  bss.size = bss.end - bss.start;
+
+  PROVIDE(_end = bss.end);
+
+  /*
+   * Initialization stack
+   */
+  InitStack_start = ALIGN(0x10);
+  . += 0x1000;
+  initStack = .;
+  PROVIDE(initStackPtr = initStack);
+
+  /*
+   * Interrupt stack
+   */
+  IntrStack_start = ALIGN(0x10);
+  . += 0x4000;
+  intrStack = .;
+  PROVIDE(intrStackPtr = intrStack);
+
+  _WorkspaceBase = .;
+  __WorkspaceBase = .;
+	
+  /*
+   * Heap
+   *
+   * The heap is configured at run-time to use all available memory.  It
+   * begins just after the end of the Workspace and continues to the end of
+   * the external RAM.
+   */
+  . = DEFINED(RTEMS_DEBUG) ? 0 + ext_ram_size : int_ram_top + ext_ram_size;
+  _HeapEnd = .;
+  __HeapEnd = .;
+ 
+        
+  /* 
+   * Internal I/O devices 
+   */
+  .usiu 0x002FC000:		/* unified system interface unit */
+  {
+    usiu = .;
+  }
+
+  .imb 0x00300000:		/* inter-module bus and devices */
+  {
+    imb = .;
+  }
+
+  .sram 0x00380000:		/* internal SRAM control registers */
+  {
+    sram = .;
+  }
+
+  /*
+   * SS555 external devices managed by on-board CPLD
+   */
+  .cpld 0xFF000000:		/* SS555 external CPLD devices */
+  {
+    cpld = .;
+  }
+
+
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment 0 : { *(.comment) }
+  
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  /* These must appear regardless of  .  */
+}
diff --git a/c/src/lib/libbsp/powerpc/ss555/startup/start.S b/c/src/lib/libbsp/powerpc/ss555/startup/start.S
new file mode 100644
index 0000000000..d14da23cb5
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/ss555/startup/start.S
@@ -0,0 +1,413 @@
+/*  start.S
+ *
+ *  This file contains the entry veneer for RTEMS programs on the Intec
+ *  SS555 board.  It jumps to the BSP which is responsible for performing
+ *  all remaining initialization.
+ *
+ * This file is based on several others:
+ * 
+ * (1) start360.s from the gen68360 BSP by 
+ *     W. Eric Norum (eric@skatter.usask.ca)
+ *     with the following copyright and license:
+ *
+ *     COPYRIGHT (c) 1989-1998.
+ *     On-Line Applications Research Corporation (OAR).
+ *     
+ *     The license and distribution terms for this file may in
+ *     the file LICENSE in this distribution or at
+ *     http://www.rtems.com/license/LICENSE.
+ *
+ * (2) start.s for the eth_comm port by
+ *     Jay Monkman (jmonkman@fracsa.com),
+ *     which itself is based on the 
+ * 
+ * (3) dlentry.s for the Papyrus BSP, written by:
+ *     Andrew Bray <andy@i-cubed.co.uk>
+ *     with the following copyright and license:
+ *
+ *     COPYRIGHT (c) 1995 by i-cubed ltd.
+ *     
+ * (4) start860.S for the MBX821/MBX860, written by:
+ *     Darlene A. Stewart <darlene.stewart@iit.nrc.ca>
+ *     Copyright (c) 1999, National Research Council of Canada
+ *
+ *     To anyone who acknowledges that this file is provided "AS IS"
+ *     without any express or implied warranty:
+ *         permission to use, copy, modify, and distribute this file
+ *         for any purpose is hereby granted without fee, provided that
+ *         the above copyright notice and this notice appears in all
+ *         copies, and that the name of i-cubed limited not be used in
+ *         advertising or publicity pertaining to distribution of the
+ *         software without specific, written prior permission.
+ *         i-cubed limited makes no representations about the suitability
+ *         of this software for any purpose.
+ *
+ * (5) Modifications (for MBX8xx) of respective RTEMS files:
+ *     Copyright (c) 1999, National Research Council of Canada
+ *
+ * SS555 port sponsored by Defence Research and Development Canada - Suffield
+ * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
+ */
+
+#include "asm.h"
+#include <rtems/powerpc/registers.h>
+
+/*
+ *  The initial stack is set to the top of the internal RAM.
+ *
+ *  All the entry veneer has to do is to clear the .bss section and copy the
+ *  initializers into the .data section.
+ */
+
+/*
+ *  GDB likes to have debugging information for the entry veneer.
+ *  Play compiler and provide some DWARF information.
+ *
+ *  CHANGE TO SUIT YOUR SETUP!
+ */
+
+        .section .entry,"ax",@progbits
+.L_text_b:
+.L_LC1:
+	.previous
+
+.section 	.debug_sfnames
+.L_sfnames_b:
+	.byte "rtems/c/src/lib/libbsp/powerpc/ss555/startup/"
+	.byte 0
+.L_F0:
+	.byte "start.S"
+	.byte 0
+	.previous
+
+.section	.line
+.L_line_b:
+	.4byte	.L_line_e-.L_line_b
+	.4byte	.L_text_b
+.L_LE1:
+.L_line_last:
+	.4byte	0x0
+	.2byte	0xffff
+	.4byte	.L_text_e-.L_text_b
+.L_line_e:
+	.previous
+
+.section	.debug_srcinfo
+.L_srcinfo_b:
+	.4byte	.L_line_b
+	.4byte	.L_sfnames_b
+	.4byte	.L_text_b
+	.4byte	.L_text_e
+	.4byte	0xffffffff
+	.4byte	.L_LE1-.L_line_b
+	.4byte	.L_F0-.L_sfnames_b
+	.4byte	.L_line_last-.L_line_b
+	.4byte	0xffffffff
+	.previous
+
+.section	.debug_pubnames
+	.4byte	.L_debug_b
+	.4byte	.L_P0
+	.byte "start"
+	.byte 0
+	.4byte	0x0
+	.byte 0
+	.previous
+
+.section	.debug_aranges
+	.4byte	.L_debug_b
+	.4byte	.L_text_b
+	.4byte	.L_text_e-.L_text_b
+	.4byte	0
+	.4byte	0
+	.4byte	0
+	.4byte	0
+	.4byte	0
+	.4byte	0
+	.4byte	0x0
+	.4byte	0x0
+	.previous
+
+.section	.debug
+.L_debug_b:
+.L_D1:
+	.4byte	.L_D1_e-.L_D1
+	.2byte	0x11	/* TAG_compile_unit */
+	.2byte	0x12	/* AT_sibling */
+	.4byte	.L_D2
+	.2byte	0x38	/* AT_name */
+	.byte "start.S"
+	.byte 0
+	.2byte	0x258	/* AT_producer */
+	.byte "GAS 2.5.2"
+	.byte 0
+	.2byte	0x111	/* AT_low_pc */
+	.4byte	.L_text_b
+	.2byte	0x121	/* AT_high_pc */
+	.4byte	.L_text_e
+	.2byte	0x106	/* AT_stmt_list */
+	.4byte	.L_line_b
+	.2byte	0x1b8	/* AT_comp_dir */
+	.byte "rtems/c/src/lib/libbsp/powerpc/ss555/startup/"
+	.byte 0
+	.2byte	0x8006	/* AT_sf_names */
+	.4byte	.L_sfnames_b
+	.2byte	0x8016	/* AT_src_info */
+	.4byte	.L_srcinfo_b
+.L_D1_e:
+.L_P0:
+.L_D3:
+	.4byte	.L_D3_e-.L_D3
+	.2byte	0x6	/* TAG_global_subroutine */
+	.2byte	0x12	/* AT_sibling */
+	.4byte	.L_D4
+	.2byte	0x38	/* AT_name */
+	.byte "start"
+	.byte 0
+	.2byte	0x278	/* AT_prototyped */
+	.byte 0
+	.2byte	0x111	/* AT_low_pc */
+	.4byte	.L_text_b
+	.2byte	0x121	/* AT_high_pc */
+	.4byte	.L_text_e
+	.2byte	0x8041	/* AT_body_begin */
+	.4byte	.L_text_b
+	.2byte	0x8051	/* AT_body_end */
+	.4byte	.L_text_e
+.L_D3_e:
+
+.L_D4:
+	.4byte	.L_D4_e-.L_D4
+	.align 2
+.L_D4_e:
+.L_D2:
+	.previous
+	
+/*
+ * Tell C's eabi-ctor's that we have an atexit function,
+ * and that it is to register __do_global_dtors.
+ */
+	EXTERN_PROC(atexit)
+	PUBLIC_VAR(__atexit)
+	.section ".sdata","aw"
+	.align	2
+SYM(__atexit):			
+	EXT_PROC_REF(atexit)@fixup
+	.previous
+
+	.section ".fixup","aw"
+	.align	2
+	EXT_SYM_REF(__atexit)
+	.previous
+
+/* That should do it */
+			
+/*
+ *  Put the entry point in its own section. That way, we can guarantee
+ *  to put it first in the .text section in the linker script.
+ */
+        .section .entry
+
+        PUBLIC_VAR (start)
+SYM(start):
+        bl      .startup	/* or bl .spin */
+base_addr:      
+
+/*
+ * Parameters from linker
+ */
+stack_top:
+	.long	initStackPtr
+
+toc_pointer:    
+        .long   __GOT_START__
+
+bss_length:     
+        .long   bss.size
+bss_addr:       
+        .long   bss.start
+
+data_length:     
+        .long   data.size
+data_addr:       
+        .long   data.start
+contents_addr:       
+        .long   data.contents.start
+
+PUBLIC_VAR (text_addr)
+text_addr:
+        .long   text.start
+
+PUBLIC_VAR (text_length)
+text_length:
+        .long   text.size
+
+/*
+ * Spin, if necessary, to acquire control from debugger (CodeWarrior).
+ */     
+spin:
+	.long	0x0001
+.spin:
+	lis	r3, spin@ha
+	lwz	r3, spin@l(r3)
+	cmpwi	r3, 0x1
+	beq	.spin
+
+/*
+ * Initialization code 
+ */
+.startup:	
+        /* Capture address of linker parameters. */
+        mflr    r3
+
+	/* Set initial stack pointer to end of internal RAM - 56. */
+	lwz	r1, stack_top-base_addr(r3)
+        addi    r1, r1, -56
+
+        /* Initialize essential registers. */
+        bl      initregs
+
+        /* Set TOC pointer */
+        lwz r2, toc_pointer-base_addr(r3)
+
+        /* Initialize the memory mapped MPC555 registers (done in C). */
+        EXTERN_PROC (_InitSS555)
+        bl	PROC (_InitSS555)
+        
+        /* Clear the .bss section. */
+        bl      bssclr
+
+	/* Copy initializers into the .data section */
+	bl	datacopy
+
+	/* Enable floating point, since gcc sometimes uses the floating
+	 * point registers for data moves, even if the C source code doesn't
+	 * include floating point operations.
+	 */
+	mfmsr	r0
+	ori	r0, r0, MSR_FP
+	mtmsr	r0
+
+	/* Start system. */
+	lis	r5, environ@ha
+	la	r5,environ@l(r5)	/* environp */
+	li	r4, 0			/* argv */
+	li	r3, 0			/* argc */
+        EXTERN_PROC (boot_card)
+        bl       PROC (boot_card)	/* call the first C routine */
+        
+        /* We should never return from boot_card, but in case we do ... */
+	/* The next instructions are dependent on your runtime environment. */
+
+stop_here:
+	b	stop_here
+
+/*
+ * datacopy - copy initializers into .data section
+ */
+datacopy:
+	lis	r3, base_addr@ha		/* point to linker data */
+	addi	r3, r3, base_addr@l
+
+        lwz     r4, contents_addr-base_addr(r3) /* .data contents in ROM */
+        lwz     r5, data_addr-base_addr(r3)     /* .data section in RAM */
+        lwz     r6, data_length-base_addr(r3)   /* length of .data */
+
+        rlwinm. r6, r6, 30, 0x3FFFFFFF          /* form length / 4 */
+        beqlr                                   /* no .data - return */
+
+        mtctr   r6                              /* set ctr reg */
+dc1:
+	lwz	r6, 0(r4)			/* get word */
+        stw     r6, 0(r5)                       /* store word */
+        addi    r4, r4, 0x4                     /* next source */
+        addi    r5, r5, 0x4                     /* next target */
+        bdnz    dc1                             /* dec counter and loop */
+        
+        blr                                     /* return */
+
+/*
+ * bssclr - zero out bss
+ */
+bssclr:
+	lis	r3, base_addr@ha		/* point to linker data */
+	addi	r3, r3, base_addr@l
+
+        lwz     r4, bss_addr-base_addr(r3)      /* Start of bss */
+        lwz     r5, bss_length-base_addr(r3)    /* Length of bss */
+
+        rlwinm. r5, r5, 30, 0x3FFFFFFF          /* form length/4 */
+        beqlr                                   /* no bss - return */
+
+        mtctr   r5                              /* set ctr reg */
+        li      r5, 0x0000                      /* r5 = 0 */
+clear_bss:
+        stw     r5, 0(r4)                       /* store r6 */
+        addi    r4, r4, 0x4                     /* update r4 */
+        bdnz    clear_bss                       /* dec counter and loop */
+        
+        blr                                     /* return */
+
+/*
+ * initregs
+ *	Initialize the MSR and basic core PowerPC registers
+ *
+ * Register usage:
+ *	r0 - scratch
+ */
+initregs:
+	/*        
+	 * Set the processor for big-endian mode, exceptions vectored to
+	 * 0x000n_nnnn, no execution tracing, machine check exceptions
+	 * enabled, floating-point not available, supervisor priviledge
+	 * level, external interrupts disabled, power management disabled
+	 * (normal operation mode).
+	 */
+	li	r0, 0x1000	/* MSR_ME */
+	mtmsr	r0		/* Context-synchronizing */
+	isync
+	
+	/*
+	 * Clear the exception handling registers.
+	 */	
+	li	r0, 0x0000
+	mtdar   r0
+	mtspr	sprg0, r0
+	mtspr	sprg1, r0
+	mtspr	sprg2, r0
+	mtspr	sprg3, r0
+	mtspr	srr0, r0
+	mtspr	srr1, r0
+			
+	mr	r6, r0
+	mr	r7, r0
+	mr	r8, r0
+	mr	r9, r0
+	mr	r10, r0
+	mr	r11, r0 
+	mr	r12, r0
+	mr	r13, r0
+	mr	r14, r0
+	mr	r15, r0
+	mr	r16, r0
+	mr	r17, r0
+	mr	r18, r0
+	mr	r19, r0
+	mr	r20, r0
+	mr	r21, r0
+	mr	r22, r0
+	mr	r23, r0
+	mr	r24, r0
+	mr	r25, r0
+	mr	r26, r0
+	mr	r27, r0
+	mr	r28, r0
+	mr	r29, r0
+	mr	r30, r0
+	mr	r31, r0
+	
+	blr			/* return */
+	
+.L_text_e:
+
+	.comm	environ,4,4