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authorRalf Corsepius <ralf.corsepius@rtems.org>2004-04-21 10:43:04 +0000
committerRalf Corsepius <ralf.corsepius@rtems.org>2004-04-21 10:43:04 +0000
commit6128a4aa5e791ed4e0a655bfd346a52d92da7883 (patch)
treeaf53ca3f67ce405b6fbc6c98399c8e0c87e01a9e /c/src/lib/libbsp/powerpc/ss555/startup
parent2004-04-20 Ralf Corsepius <ralf_corsepius@rtems.org> (diff)
downloadrtems-6128a4aa5e791ed4e0a655bfd346a52d92da7883.tar.bz2
Remove stray white spaces.
Diffstat (limited to 'c/src/lib/libbsp/powerpc/ss555/startup')
-rw-r--r--c/src/lib/libbsp/powerpc/ss555/startup/bspstart.c18
-rw-r--r--c/src/lib/libbsp/powerpc/ss555/startup/iss555.c32
-rw-r--r--c/src/lib/libbsp/powerpc/ss555/startup/start.S60
3 files changed, 55 insertions, 55 deletions
diff --git a/c/src/lib/libbsp/powerpc/ss555/startup/bspstart.c b/c/src/lib/libbsp/powerpc/ss555/startup/bspstart.c
index 9e990f354a..626b510732 100644
--- a/c/src/lib/libbsp/powerpc/ss555/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/ss555/startup/bspstart.c
@@ -64,13 +64,13 @@ void bsp_libc_init( void *, unsigned32, int );
void BSP_panic(char *s)
{
printk("%s PANIC %s\n",_RTEMS_version, s);
- __asm__ __volatile ("sc");
+ __asm__ __volatile ("sc");
}
void _BSP_Fatal_error(unsigned int v)
{
printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
- __asm__ __volatile ("sc");
+ __asm__ __volatile ("sc");
}
/*
@@ -95,7 +95,7 @@ void _BSP_Fatal_error(unsigned int v)
*/
void bsp_pretasking_hook(void)
{
- /*
+ /*
* These are assigned addresses in the linkcmds file for the BSP. This
* approach is better than having these defined as manifest constants and
* compiled into the kernel, but it is still not ideal when dealing with
@@ -105,13 +105,13 @@ void bsp_pretasking_hook(void)
* the kernel and the application can be linked and burned into ROM
* independently of each other.
*/
- unsigned char *_HeapStart =
- (char*)BSP_Configuration.work_space_start
+ unsigned char *_HeapStart =
+ (char*)BSP_Configuration.work_space_start
+ BSP_Configuration.work_space_size;
extern unsigned char _HeapEnd[];
bsp_libc_init( _HeapStart, _HeapEnd - _HeapStart, 0 );
-
+
#ifdef RTEMS_DEBUG
rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
#endif
@@ -141,11 +141,11 @@ void bsp_pretasking_hook(void)
void bsp_start(void)
{
extern char _WorkspaceBase[];
-
+
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
register unsigned char* intrStack;
-
+
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
* function stores the result in global variables so that it can be used
@@ -190,7 +190,7 @@ void bsp_start(void)
Cpu_table.clicks_per_usec = BSP_CRYSTAL_HZ / 4 / 1000000;
Cpu_table.clock_speed = BSP_CLOCK_HZ; /* for SCI baud rate generator */
- /*
+ /*
* Call this in case we use TERMIOS for console I/O
*/
m5xx_uart_reserve_resources( &BSP_Configuration );
diff --git a/c/src/lib/libbsp/powerpc/ss555/startup/iss555.c b/c/src/lib/libbsp/powerpc/ss555/startup/iss555.c
index 34731848d2..133fad3b2d 100644
--- a/c/src/lib/libbsp/powerpc/ss555/startup/iss555.c
+++ b/c/src/lib/libbsp/powerpc/ss555/startup/iss555.c
@@ -38,7 +38,7 @@ void _InitSS555 (void)
* Initialize the System Protection Control Register (SYPCR).
* The SYPCR can only be written once after Reset.
*/
- usiu.sypcr =
+ usiu.sypcr =
USIU_SYPCR_SWTC(WATCHDOG_TIMEOUT) /* set watchdog timeout */
| USIU_SYPCR_BMT(0xFF) /* set bus monitor timeout */
| USIU_SYPCR_BME /* enable bus monitor */
@@ -50,12 +50,12 @@ void _InitSS555 (void)
| USIU_SYPCR_SWP; /* prescale watchdog by 2048 */
TICKLE_WATCHDOG(); /* restart watchdog timer */
-
- /*
+
+ /*
* Re-tune the PLL to the desired system clock frequency.
*/
usiu.plprck = USIU_UNLOCK_KEY; /* unlock PLPRCR */
- usiu.plprcr =
+ usiu.plprcr =
USIU_PLPRCR_TEXPS /* assert TEXP always */
| USIU_PLPRCR_MF(BSP_CLOCK_HZ / BSP_CRYSTAL_HZ);
/* PLL multiplication factor */
@@ -63,11 +63,11 @@ void _InitSS555 (void)
while (((plprcr = usiu.plprcr) & USIU_PLPRCR_SPLS) == 0)
; /* wait for PLL to re-lock */
-
- /*
+
+ /*
* Enable the timebase and decrementer, then initialize decrementer
* register to a large value to guarantee that a decrementer interrupt
- * will not be generated before the kernel is fully initialized.
+ * will not be generated before the kernel is fully initialized.
* Initialize the timebase register to zero.
*/
usiu.tbscrk = USIU_UNLOCK_KEY;
@@ -84,7 +84,7 @@ void _InitSS555 (void)
* Run the Inter-Module Bus at full speed.
*/
imb.uimb.umcr &= ~UIMB_UMCR_HSPEED;
-
+
/*
* Initialize Memory Controller for External RAM
*
@@ -96,19 +96,19 @@ void _InitSS555 (void)
* zero but set it up appropriately.
*/
extern char int_ram_top[]; /* top of internal ram */
-
+
usiu.memc[0]._or =
USIU_MEMC_OR_512K /* bank size */
| USIU_MEMC_OR_SCY(0) /* wait states in first beat of burst */
| USIU_MEMC_OR_BSCY(0); /* wait states in subsequent beats */
-
+
usiu.memc[0]._br =
- USIU_MEMC_BR_BA(_read_IMMR() & IMMR_FLEN
+ USIU_MEMC_BR_BA(_read_IMMR() & IMMR_FLEN
? (rtems_unsigned32)int_ram_top : 0) /* base address */
| USIU_MEMC_BR_PS32 /* 32-bit data bus */
| USIU_MEMC_BR_TBDIP /* toggle bdip */
| USIU_MEMC_BR_V; /* base register valid */
-
+
/*
* Initialize Memory Controller for External CPLD
*
@@ -120,21 +120,21 @@ void _InitSS555 (void)
| USIU_MEMC_OR_CSNT /* negate CS/WE early */
| USIU_MEMC_OR_ACS_HALF /* assert CS half cycle after address */
| USIU_MEMC_OR_SCY(15) /* wait states in first beat of burst */
- | USIU_MEMC_OR_TRLX; /* relaxed timing */
+ | USIU_MEMC_OR_TRLX; /* relaxed timing */
usiu.memc[3]._br =
USIU_MEMC_BR_BA(&cpld) /* base address */
| USIU_MEMC_BR_PS16 /* 16-bit data bus */
| USIU_MEMC_BR_BI /* inhibit bursting */
| USIU_MEMC_BR_V; /* base register valid */
-
+
/*
* Disable show cycles and serialization so that burst accesses will work
* properly. A different value, such as 0x0, may be more appropriate for
* debugging, but can be set with the debugger, if needed.
*/
_write_ICTRL(0x00000007);
-
+
/*
* Set up Burst Buffer Controller (BBC)
*/
@@ -144,6 +144,6 @@ void _InitSS555 (void)
_isync;
_CPU_MSR_GET(msr);
- msr |= MSR_IP; /* set prefix for exception relocation */
+ msr |= MSR_IP; /* set prefix for exception relocation */
_CPU_MSR_SET(msr);
}
diff --git a/c/src/lib/libbsp/powerpc/ss555/startup/start.S b/c/src/lib/libbsp/powerpc/ss555/startup/start.S
index ec759f1fa6..73a4606a8d 100644
--- a/c/src/lib/libbsp/powerpc/ss555/startup/start.S
+++ b/c/src/lib/libbsp/powerpc/ss555/startup/start.S
@@ -5,28 +5,28 @@
* all remaining initialization.
*
* This file is based on several others:
- *
- * (1) start360.s from the gen68360 BSP by
+ *
+ * (1) start360.s from the gen68360 BSP by
* W. Eric Norum (eric@skatter.usask.ca)
* with the following copyright and license:
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
- *
+ *
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* (2) start.s for the eth_comm port by
* Jay Monkman (jmonkman@fracsa.com),
- * which itself is based on the
- *
+ * which itself is based on the
+ *
* (3) dlentry.s for the Papyrus BSP, written by:
* Andrew Bray <andy@i-cubed.co.uk>
* with the following copyright and license:
*
* COPYRIGHT (c) 1995 by i-cubed ltd.
- *
+ *
* (4) start860.S for the MBX821/MBX860, written by:
* Darlene A. Stewart <darlene.stewart@iit.nrc.ca>
* Copyright (c) 1999, National Research Council of Canada
@@ -182,7 +182,7 @@
.L_D4_e:
.L_D2:
.previous
-
+
/*
* Tell C's eabi-ctor's that we have an atexit function,
* and that it is to register __do_global_dtors.
@@ -191,7 +191,7 @@
PUBLIC_VAR(__atexit)
.section ".sdata","aw"
.align 2
-SYM(__atexit):
+SYM(__atexit):
EXT_PROC_REF(atexit)@fixup
.previous
@@ -201,7 +201,7 @@ SYM(__atexit):
.previous
/* That should do it */
-
+
/*
* Put the entry point in its own section. That way, we can guarantee
* to put it first in the .text section in the linker script.
@@ -211,7 +211,7 @@ SYM(__atexit):
PUBLIC_VAR (start)
SYM(start):
bl .startup /* or bl .spin */
-base_addr:
+base_addr:
/*
* Parameters from linker
@@ -219,19 +219,19 @@ base_addr:
stack_top:
.long initStackPtr
-toc_pointer:
+toc_pointer:
.long __GOT_START__
-bss_length:
+bss_length:
.long bss.size
-bss_addr:
+bss_addr:
.long bss.start
-data_length:
+data_length:
.long data.size
-data_addr:
+data_addr:
.long data.start
-contents_addr:
+contents_addr:
.long data.contents.start
PUBLIC_VAR (text_addr)
@@ -244,7 +244,7 @@ text_length:
/*
* Spin, if necessary, to acquire control from debugger (CodeWarrior).
- */
+ */
spin:
.long 0x0001
.spin:
@@ -254,9 +254,9 @@ spin:
beq .spin
/*
- * Initialization code
+ * Initialization code
*/
-.startup:
+.startup:
/* Capture address of linker parameters. */
mflr r3
@@ -273,7 +273,7 @@ spin:
/* Initialize the memory mapped MPC555 registers (done in C). */
EXTERN_PROC (_InitSS555)
bl PROC (_InitSS555)
-
+
/* Clear the .bss section. */
bl bssclr
@@ -295,7 +295,7 @@ spin:
li r3, 0 /* argc */
EXTERN_PROC (boot_card)
bl PROC (boot_card) /* call the first C routine */
-
+
/* We should never return from boot_card, but in case we do ... */
/* The next instructions are dependent on your runtime environment. */
@@ -323,7 +323,7 @@ dc1:
addi r4, r4, 0x4 /* next source */
addi r5, r5, 0x4 /* next target */
bdnz dc1 /* dec counter and loop */
-
+
blr /* return */
/*
@@ -345,7 +345,7 @@ clear_bss:
stw r5, 0(r4) /* store r6 */
addi r4, r4, 0x4 /* update r4 */
bdnz clear_bss /* dec counter and loop */
-
+
blr /* return */
/*
@@ -356,7 +356,7 @@ clear_bss:
* r0 - scratch
*/
initregs:
- /*
+ /*
* Set the processor for big-endian mode, exceptions vectored to
* 0x000n_nnnn, no execution tracing, machine check exceptions
* enabled, floating-point not available, supervisor priviledge
@@ -366,10 +366,10 @@ initregs:
li r0, 0x1000 /* MSR_ME */
mtmsr r0 /* Context-synchronizing */
isync
-
+
/*
* Clear the exception handling registers.
- */
+ */
li r0, 0x0000
mtdar r0
mtspr sprg0, r0
@@ -378,13 +378,13 @@ initregs:
mtspr sprg3, r0
mtspr srr0, r0
mtspr srr1, r0
-
+
mr r6, r0
mr r7, r0
mr r8, r0
mr r9, r0
mr r10, r0
- mr r11, r0
+ mr r11, r0
mr r12, r0
mr r13, r0
mr r14, r0
@@ -405,9 +405,9 @@ initregs:
mr r29, r0
mr r30, r0
mr r31, r0
-
+
blr /* return */
-
+
.L_text_e:
.comm environ,4,4