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author | Ralf Corsepius <ralf.corsepius@rtems.org> | 2004-04-21 10:43:04 +0000 |
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committer | Ralf Corsepius <ralf.corsepius@rtems.org> | 2004-04-21 10:43:04 +0000 |
commit | 6128a4aa5e791ed4e0a655bfd346a52d92da7883 (patch) | |
tree | af53ca3f67ce405b6fbc6c98399c8e0c87e01a9e /c/src/lib/libbsp/powerpc/shared/vectors | |
parent | 2004-04-20 Ralf Corsepius <ralf_corsepius@rtems.org> (diff) | |
download | rtems-6128a4aa5e791ed4e0a655bfd346a52d92da7883.tar.bz2 |
Remove stray white spaces.
Diffstat (limited to 'c/src/lib/libbsp/powerpc/shared/vectors')
-rw-r--r-- | c/src/lib/libbsp/powerpc/shared/vectors/vectors.S | 34 | ||||
-rw-r--r-- | c/src/lib/libbsp/powerpc/shared/vectors/vectors.h | 8 | ||||
-rw-r--r-- | c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c | 6 |
3 files changed, 24 insertions, 24 deletions
diff --git a/c/src/lib/libbsp/powerpc/shared/vectors/vectors.S b/c/src/lib/libbsp/powerpc/shared/vectors/vectors.S index 17c4ffecd6..55f990ec33 100644 --- a/c/src/lib/libbsp/powerpc/shared/vectors/vectors.S +++ b/c/src/lib/libbsp/powerpc/shared/vectors/vectors.S @@ -2,37 +2,37 @@ * (c) 1999, Eric Valette valette@crf.canon.fr * * - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * exception veneers for RTEMS. * * $Id$ */ - + #include <rtems/asm.h> #include <rtems/score/cpu.h> #include <bsp/vectors.h> - + #define SYNC \ sync; \ isync - + PUBLIC_VAR (__rtems_start) .section .entry_point_section,"awx",@progbits /* * Entry point information used by bootloader code */ -SYM (__rtems_start): +SYM (__rtems_start): .long __rtems_entry_point /* * end of special Entry point section - */ + */ .text - .p2align 5 - + .p2align 5 + PUBLIC_VAR(default_exception_vector_code_prolog) SYM (default_exception_vector_code_prolog): /* @@ -48,7 +48,7 @@ SYM (default_exception_vector_code_prolog): stw r3, EXC_LR_OFFSET(r1) bl 0f 0: /* - * r3 = exception vector entry point + * r3 = exception vector entry point * (256 * vector number) + few instructions */ mflr r3 @@ -57,13 +57,13 @@ SYM (default_exception_vector_code_prolog): */ srwi r3,r3,8 ba push_normalized_frame - + PUBLIC_VAR (default_exception_vector_code_prolog_size) - + default_exception_vector_code_prolog_size= . - default_exception_vector_code_prolog - + .p2align 5 -PUBLIC_VAR (push_normalized_frame) +PUBLIC_VAR (push_normalized_frame) SYM (push_normalized_frame): stw r3, EXCEPTION_NUMBER_OFFSET(r1) stw r0, GPR0_OFFSET(r1) @@ -77,7 +77,7 @@ SYM (push_normalized_frame): * Saved a few line above : R0 * * Manual says that "stmw" instruction may be slower than - * series of individual "stw" but who cares about performance + * series of individual "stw" but who cares about performance * for the DEFAULT exception handler? */ stmw r4, GPR4_OFFSET(r1) /* save R4->R31 */ @@ -107,7 +107,7 @@ SYM (push_normalized_frame): ori r3,r3, MSR_RI | MSR_IR | MSR_DR mtmsr r3 SYNC - + /* * Call C exception handler */ @@ -148,12 +148,12 @@ SYM (push_normalized_frame): /* * Restore rfi related settings */ - + lwz r3, SRR1_FRAME_OFFSET(r1) mtsrr1 r3 lwz r3, SRR0_FRAME_OFFSET(r1) mtsrr0 r3 - + lwz r3, GPR3_OFFSET(r1) addi r1,r1, EXCEPTION_FRAME_END SYNC diff --git a/c/src/lib/libbsp/powerpc/shared/vectors/vectors.h b/c/src/lib/libbsp/powerpc/shared/vectors/vectors.h index f995b16303..976af3d7f4 100644 --- a/c/src/lib/libbsp/powerpc/shared/vectors/vectors.h +++ b/c/src/lib/libbsp/powerpc/shared/vectors/vectors.h @@ -1,4 +1,4 @@ -/* +/* * vectors.h Exception frame related contant and API. * * This include file describe the data structure and the functions implemented @@ -16,10 +16,10 @@ #define LIBBSP_POWERPC_MCP750_VECTORS_H /* - * The callee (high level exception code written in C) + * The callee (high level exception code written in C) * will store the Link Registers (return address) at entry r1 + 4 !!!. * So let room for it!!!. - */ + */ #define LINK_REGISTER_CALLEE_UPDATE_ROOM 4 #define SRR0_FRAME_OFFSET 8 #define SRR1_FRAME_OFFSET 12 @@ -86,7 +86,7 @@ extern int default_exception_vector_code_prolog_size[]; * zero, it performs more or less like memmove. No copy is performed if * source and destination addresses are equal. However the caches * are synchronized. Note that the size is always rounded up to the - * next mutiple of 4. + * next mutiple of 4. */ extern void * codemove(void *, const void *, unsigned int, unsigned long); extern void initialize_exceptions(); diff --git a/c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c b/c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c index 0a8577b92d..c897d89159 100644 --- a/c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c +++ b/c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c @@ -1,4 +1,4 @@ -/* +/* * vectors_init.c Exception hanlding initialisation (and generic handler). * * This include file describe the data structure and the functions implemented @@ -72,7 +72,7 @@ void *lr; void C_exception_handler(BSP_Exception_frame* excPtr) { int recoverable = 0; - + printk("exception handler called for exception %d\n", excPtr->_EXC_number); printk("\t Next PC or Address of fault = %x\n", excPtr->EXC_SRR0); printk("\t Saved MSR = %x\n", excPtr->EXC_SRR1); @@ -119,7 +119,7 @@ void C_exception_handler(BSP_Exception_frame* excPtr) if (excPtr->_EXC_number == ASM_DEC_VECTOR) recoverable = 1; if (excPtr->_EXC_number == ASM_SYS_VECTOR) -#ifdef TEST_RAW_EXCEPTION_CODE +#ifdef TEST_RAW_EXCEPTION_CODE recoverable = 1; #else recoverable = 0; |