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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-01-03 14:06:42 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-01-03 14:06:42 +0000 |
| commit | 95273a610ff4ed4f4cf78d20a99f6a32acec8841 (patch) | |
| tree | 13070b2dd02c204cbcfeedfc0cdaebb2e1e44e9e /c/src/lib/libbsp/powerpc/shared/start | |
| parent | Use shared coverhd.h. (diff) | |
| download | rtems-95273a610ff4ed4f4cf78d20a99f6a32acec8841.tar.bz2 | |
Combination of coverhd.h cleanup and MVME23xx/MCP750 patch from Eric Valette
<valette@crf.canon.fr> and Jay Kulpinski <jskulpin@eng01.gdds.com>.
Diffstat (limited to 'c/src/lib/libbsp/powerpc/shared/start')
| -rw-r--r-- | c/src/lib/libbsp/powerpc/shared/start/start.S | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/powerpc/shared/start/start.S b/c/src/lib/libbsp/powerpc/shared/start/start.S index cc2dabd2c7..ee09686659 100644 --- a/c/src/lib/libbsp/powerpc/shared/start/start.S +++ b/c/src/lib/libbsp/powerpc/shared/start/start.S @@ -49,6 +49,8 @@ __rtems_entry_point: * r6: Start of command line string * r7: End of command line string * + * The Prep boot loader insure that the MMU is currently off... + * */ mr r31,r3 /* save parameters */ @@ -56,6 +58,11 @@ __rtems_entry_point: mr r29,r5 mr r28,r6 mr r27,r7 + /* + * Make sure we have nothing in BATS and TLB + */ + bl clear_bats + bl flush_tlbs /* * Use the first pair of BAT registers to map the 1st 64MB * of RAM to KERNELBASE. @@ -63,6 +70,7 @@ __rtems_entry_point: lis r11,KERNELBASE@h ori r11,r11,0x7fe /* set up BAT registers for 604 */ li r8,2 /* R/W access */ + isync mtspr DBAT0L,r8 /* N.B. 6xx (not 601) have valid */ mtspr DBAT0U,r11 /* bit in upper BAT register */ mtspr IBAT0L,r8 @@ -129,3 +137,47 @@ _return_to_ppcbug: bl MMUon mtctr r30 bctr + +/* + * An undocumented "feature" of 604e requires that the v bit + * be cleared before changing BAT values. + * + * Also, newer IBM firmware does not clear bat3 and 4 so + * this makes sure it's done. + * -- Cort + */ +clear_bats: + li r20,0 + mfspr r9,PVR + rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ + cmpwi r9, 1 + SYNC + beq 1f + mtspr DBAT0U,r20 + mtspr DBAT0L,r20 + mtspr DBAT1U,r20 + mtspr DBAT1L,r20 + mtspr DBAT2U,r20 + mtspr DBAT2L,r20 + mtspr DBAT3U,r20 + mtspr DBAT3L,r20 +1: + mtspr IBAT0U,r20 + mtspr IBAT0L,r20 + mtspr IBAT1U,r20 + mtspr IBAT1L,r20 + mtspr IBAT2U,r20 + mtspr IBAT2L,r20 + mtspr IBAT3U,r20 + mtspr IBAT3L,r20 + SYNC + blr + +flush_tlbs: + lis r20, 0x1000 +1: addic. r20, r20, -0x1000 + tlbie r20 + blt 1b + sync + blr + |