Combination of coverhd.h cleanup and MVME23xx/MCP750 patch from Eric Valette

<valette@crf.canon.fr> and Jay Kulpinski <jskulpin@eng01.gdds.com>.

9 files changed, 216 insertions, 32 deletions

diff --git a/c/src/lib/libbsp/powerpc/shared/include/bsp.h b/c/src/lib/libbsp/powerpc/shared/include/bsp.h
index 7672298231..a2be655e1e 100644
--- a/c/src/lib/libbsp/powerpc/shared/include/bsp.h
+++ b/c/src/lib/libbsp/powerpc/shared/include/bsp.h
@@ -32,19 +32,22 @@
 /*
  * Total memory using RESIDUAL DATA
  */
-unsigned int BSP_mem_size;
+extern unsigned int BSP_mem_size;
 /*
  * PCI Bus Frequency
  */
-unsigned int BSP_bus_frequency;
+extern unsigned int BSP_bus_frequency;
 /*
  * processor clock frequency
  */
-unsigned int BSP_processor_frequency;
+extern unsigned int BSP_processor_frequency;
 /*
  * Time base divisior (how many tick for 1 second).
  */
-unsigned int BSP_time_base_divisor;
+extern unsigned int BSP_time_base_divisor;
+
+#define BSP_Convert_decrementer( _value ) \
+  ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
 
 extern rtems_configuration_table  BSP_Configuration;
 extern void BSP_panic(char *s);
diff --git a/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c b/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c
index 6253ec789e..f97f21325f 100644
--- a/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c
+++ b/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c
@@ -5,6 +5,9 @@
  *
  *  CopyRight (C) 1999 valette@crf.canon.fr
  *
+ * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
+ * to make it valid for MVME2300 Motorola boards.
+ *
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
  *  http://www.OARcorp.com/rtems/license.html.
@@ -249,10 +252,14 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
 #ifdef TRACE_IRQ_INIT  
   printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
 #endif
-  if ( (currentBoard == MESQUITE) ) {
+  if ( currentBoard == MESQUITE ) {
     VIA_isa_bridge_interrupts_setup();
     known_cpi_isa_bridge = 1;
   }
+  if ( currentBoard == MVME_2300 ) {
+    /* nothing to do for W83C553 bridge */
+    known_cpi_isa_bridge = 1;
+  }
   if (!known_cpi_isa_bridge) {
     printk("Please add code for PCI/ISA bridge init to libbsp/shared/irq/irq_init.c\n");
     printk("If your card works correctly please add a test and set known_cpi_isa_bridge to true\n");
diff --git a/c/src/lib/libbsp/powerpc/shared/start/start.S b/c/src/lib/libbsp/powerpc/shared/start/start.S
index cc2dabd2c7..ee09686659 100644
--- a/c/src/lib/libbsp/powerpc/shared/start/start.S
+++ b/c/src/lib/libbsp/powerpc/shared/start/start.S
@@ -49,6 +49,8 @@ __rtems_entry_point:
  *   r6: Start of command line string
  *   r7: End of command line string
  *
+ *   The Prep boot loader insure that the MMU is currently off...
+ *
  */
 	
 	mr	r31,r3			/* save parameters */
@@ -56,6 +58,11 @@ __rtems_entry_point:
 	mr	r29,r5
 	mr	r28,r6
 	mr	r27,r7
+	/*
+	 * Make sure we have nothing in BATS and TLB
+	 */
+	bl	clear_bats
+	bl	flush_tlbs
 /*
  * Use the first pair of BAT registers to map the 1st 64MB
  * of RAM to KERNELBASE. 
@@ -63,6 +70,7 @@ __rtems_entry_point:
 	lis	r11,KERNELBASE@h
 	ori	r11,r11,0x7fe		/* set up BAT registers for 604 */
 	li	r8,2			/* R/W access */
+	isync
 	mtspr	DBAT0L,r8		/* N.B. 6xx (not 601) have valid */
 	mtspr	DBAT0U,r11		/* bit in upper BAT register */
 	mtspr	IBAT0L,r8
@@ -129,3 +137,47 @@ _return_to_ppcbug:
 	bl	MMUon
 	mtctr	r30
 	bctr	
+
+/* 
+ * An undocumented "feature" of 604e requires that the v bit
+ * be cleared before changing BAT values.
+ *
+ * Also, newer IBM firmware does not clear bat3 and 4 so
+ * this makes sure it's done.
+ *  -- Cort 
+ */
+clear_bats:
+	li	r20,0
+	mfspr	r9,PVR
+	rlwinm	r9,r9,16,16,31		/* r9 = 1 for 601, 4 for 604 */
+	cmpwi	r9, 1
+	SYNC
+	beq	1f
+	mtspr	DBAT0U,r20
+	mtspr	DBAT0L,r20	
+	mtspr	DBAT1U,r20
+	mtspr	DBAT1L,r20
+	mtspr	DBAT2U,r20
+	mtspr	DBAT2L,r20	
+	mtspr	DBAT3U,r20
+	mtspr	DBAT3L,r20
+1:	
+	mtspr	IBAT0U,r20
+	mtspr	IBAT0L,r20
+	mtspr	IBAT1U,r20
+	mtspr	IBAT1L,r20
+	mtspr	IBAT2U,r20
+	mtspr	IBAT2L,r20
+	mtspr	IBAT3U,r20
+	mtspr	IBAT3L,r20
+	SYNC	
+	blr
+
+flush_tlbs:
+	lis	r20, 0x1000
+1:	addic.	r20, r20, -0x1000
+	tlbie	r20
+	blt	1b
+	sync
+	blr
+	
diff --git a/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c b/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c
index 63181b603d..4ca991e229 100644
--- a/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c
@@ -233,8 +233,7 @@ void bsp_start( void )
    * Must have acces to open pic PCI ACK registers 
    * provided by the RAVEN
    */
-  setdbat(3, 0xfeff0000, 0xfeff0000, 0x10000, IO_PAGE);
-
+  setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
   select_console(CONSOLE_LOG);
 
   /* We check that the keyboard is present and immediately 
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c b/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c
index b3d93f8f34..035af4d61d 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c
@@ -143,7 +143,7 @@ rtems_device_driver Clock_initialize(
   void *pargp
 )
 {
-  Clock_Decrementer_value = (BSP_bus_frequency/4000)*
+  Clock_Decrementer_value = (BSP_bus_frequency/BSP_time_base_divisor)*
                             (BSP_Configuration.microseconds_per_tick/1000);
 
   if (!BSP_connect_clock_handler ()) {
@@ -185,7 +185,7 @@ rtems_device_driver Clock_control(
     if (args == 0)
         goto done;
  
-    Clock_Decrementer_value = (BSP_bus_frequency/4000)*
+    Clock_Decrementer_value = (BSP_bus_frequency/BSP_time_base_divisor)*
       (BSP_Configuration.microseconds_per_tick/1000);
 
     if      (args->command == rtems_build_name('I', 'S', 'R', ' '))
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.c b/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.c
index cd8274e2e1..5b4ac21ea4 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.c
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.c
@@ -11,6 +11,9 @@
  * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
  *                     Canon Centre Recherche France.
  *
+ * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
+ * to support 603, 603e, 604, 604e exceptions
+ *
  *  The license and distribution terms for this file may be
  *  found in found in the file LICENSE in this distribution or at
  *  http://www.OARcorp.com/rtems/license.html.
@@ -50,12 +53,61 @@ int mpc750_vector_is_valid(rtems_vector vector)
   }
 }
 
+int mpc603_vector_is_valid(rtems_vector vector)
+{
+  switch(vector) {
+  case ASM_RESET_VECTOR: /* fall through */
+  case ASM_MACH_VECTOR:
+  case ASM_PROT_VECTOR:
+  case ASM_ISI_VECTOR:
+  case ASM_EXT_VECTOR:
+  case ASM_ALIGN_VECTOR:
+  case ASM_PROG_VECTOR:
+  case ASM_FLOAT_VECTOR:
+  case ASM_DEC_VECTOR:
+  case ASM_SYS_VECTOR:
+  case ASM_TRACE_VECTOR:
+    return 1;
+  case ASM_PERFMON_VECTOR:
+    return 0;
+  case ASM_IMISS_VECTOR: /* fall through */
+  case ASM_DLMISS_VECTOR:
+  case ASM_DSMISS_VECTOR:
+  case ASM_ADDR_VECTOR:
+  case ASM_SYSMGMT_VECTOR:
+    return 1;
+  case ASM_ITM_VECTOR:
+    return 0;
+  }
+  return 0;
+}
+
 int mpc604_vector_is_valid(rtems_vector vector)
 {
-  /*
-   * Please fill this for MVME2307
-   */
-  printk("Please complete libcpu/powerpc/XXX/raw_exception.c\n");
+  switch(vector) {
+  case ASM_RESET_VECTOR: /* fall through */
+  case ASM_MACH_VECTOR:
+  case ASM_PROT_VECTOR:
+  case ASM_ISI_VECTOR:
+  case ASM_EXT_VECTOR:
+  case ASM_ALIGN_VECTOR:
+  case ASM_PROG_VECTOR:
+  case ASM_FLOAT_VECTOR:
+  case ASM_DEC_VECTOR:
+  case ASM_SYS_VECTOR:
+  case ASM_TRACE_VECTOR:
+  case ASM_PERFMON_VECTOR:
+    return 1;
+  case ASM_IMISS_VECTOR: /* fall through */
+  case ASM_DLMISS_VECTOR:
+  case ASM_DSMISS_VECTOR:
+    return 0;
+  case ASM_ADDR_VECTOR: /* fall through */
+  case ASM_SYSMGMT_VECTOR:
+    return 1;
+  case ASM_ITM_VECTOR:
+    return 0;
+  }
   return 0;
 }
 
@@ -63,22 +115,31 @@ int mpc60x_set_exception  (const rtems_raw_except_connect_data* except)
 {
     unsigned int level;
 
-    if (current_ppc_cpu == PPC_750) {
-      if (!mpc750_vector_is_valid(except->exceptIndex)){
-	return 0;
-      }
-      goto exception_ok;
-    }
-    if (current_ppc_cpu == PPC_604) {
-      if (!mpc604_vector_is_valid(except->exceptIndex)){
-	return 0;
-      }
-      goto exception_ok;
+    switch (current_ppc_cpu) {
+        case PPC_750:
+            if (!mpc750_vector_is_valid(except->exceptIndex)) {
+                return 0;
+            }
+            break;
+        case PPC_604:
+        case PPC_604e:
+        case PPC_604r:
+            if (!mpc604_vector_is_valid(except->exceptIndex)) {
+                return 0;
+            }
+            break;
+        case PPC_603:
+        case PPC_603e:
+            if (!mpc603_vector_is_valid(except->exceptIndex)) {
+                return 0;
+            }
+            break;
+        default:
+            printk("Please complete libcpu/powerpc/mpc6xx/raw_exception.c\n");
+            printk("current_ppc_cpu = %x\n", current_ppc_cpu);
+            return 0;
     }
-    printk("Please complete libcpu/powerpc/XXX/raw_exception.c\n");
-    return 0;
-    
-exception_ok:
+
     /*
      * Check if default handler is actually connected. If not issue an error.
      * You must first get the current handler via mpc60x_get_current_exception
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.h b/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.h
index f6542b9dfe..4419fdda8e 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.h
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.h
@@ -13,6 +13,9 @@
  * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
  *                     Canon Centre Recherche France.
  *
+ * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
+ * to support 603, 603e, 604, 604e exceptions
+ *
  *  The license and distribution terms for this file may be
  *  found in found in the file LICENSE in this distribution or at
  *  http://www.OARcorp.com/rtems/license.html.
@@ -38,6 +41,10 @@
 #define	ASM_DEC_VECTOR		0x09
 #define	ASM_SYS_VECTOR		0x0C
 #define	ASM_TRACE_VECTOR	0x0D
+#define	ASM_PERFMON_VECTOR	0x0F
+#define	ASM_IMISS_VECTOR	0x10
+#define	ASM_DLMISS_VECTOR	0x11
+#define	ASM_DSMISS_VECTOR	0x12
 #define	ASM_ADDR_VECTOR		0x13
 #define	ASM_SYSMGMT_VECTOR	0x14
 #define	ASM_ITM_VECTOR		0x17
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S
index a0f298e5c3..b5a76704c2 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S
@@ -19,27 +19,48 @@
 #include <rtems/score/targopts.h>
 #include "asm.h"
 
+/*
+ * Each setdbat routine start by invalidating the DBAT as some
+ * proc (604e) request the valid bit set to 0 before accepting 
+ * to write in BAT
+ */
+
 	.globl  asm_setdbat1
 	.type	asm_setdbat1,@function
-asm_setdbat1:	
-	mtspr DBAT1U, r3
+asm_setdbat1:
+	li	r20,0
+	SYNC
+	mtspr	DBAT1U,r20
+	mtspr	DBAT1L,r20
+	SYNC
 	mtspr DBAT1L, r4
+	mtspr DBAT1U, r3
 	SYNC
 	blr
 
 	.globl  asm_setdbat2
 	.type	asm_setdbat2,@function
 asm_setdbat2:	
-	mtspr DBAT2U, r3
+	li	r20,0
+	SYNC
+	mtspr	DBAT2U,r20
+	mtspr	DBAT2L,r20
+	SYNC
 	mtspr DBAT2L, r4
+	mtspr DBAT2U, r3
 	SYNC
 	blr
 
 	.globl  asm_setdbat3
 	.type	asm_setdbat3,@function
 asm_setdbat3:	
-	mtspr DBAT3U, r3
+	li	r20,0
+	SYNC
+	mtspr	DBAT3U,r20
+	mtspr	DBAT3L,r20
+	SYNC
 	mtspr DBAT3L, r4
+	mtspr DBAT3U, r3
 	SYNC
 	blr
 		
diff --git a/c/src/lib/libcpu/powerpc/shared/cpu.h b/c/src/lib/libcpu/powerpc/shared/cpu.h
index f071683972..3fe27f5496 100644
--- a/c/src/lib/libcpu/powerpc/shared/cpu.h
+++ b/c/src/lib/libcpu/powerpc/shared/cpu.h
@@ -191,6 +191,40 @@ extern ppc_cpu_id_t get_ppc_cpu_type();
 extern ppc_cpu_id_t current_ppc_cpu;
 extern ppc_cpu_revision_t get_ppc_cpu_revision();
 extern ppc_cpu_revision_t current_ppc_revision;
+/*
+ *  Routines to access the time base register
+ */
+
+static inline unsigned long long PPC_Get_timebase_register( void )
+{
+  unsigned long tbr_low;
+  unsigned long tbr_high;
+  unsigned long tbr_high_old;
+  unsigned long long tbr;
+
+  do {
+    asm volatile( "mftbu %0" : "=r" (tbr_high_old));
+    asm volatile( "mftb  %0" : "=r" (tbr_low));
+    asm volatile( "mftbu %0" : "=r" (tbr_high));
+  } while ( tbr_high_old != tbr_high );
+
+  tbr = tbr_high;
+  tbr <<= 32;
+  tbr |= tbr_low;
+  return tbr;
+}
+
+static inline  void PPC_Set_timebase_register (unsigned long long tbr)
+{
+  unsigned long tbr_low;
+  unsigned long tbr_high;
+
+  tbr_low = (tbr & 0xffffffff) ;
+  tbr_high = (tbr >> 32) & 0xffffffff;
+  asm volatile( "mtspr 284, %0" : : "r" (tbr_low));
+  asm volatile( "mtspr 285, %0" : : "r" (tbr_high));
+  
+}
 #endif
 
 #define _CPU_MSR_GET( _msr_value ) \