2009-05-05 Jennifer Averett <jennifer.averett@OARcorp.com>

	* Makefile.am, configure.ac, preinstall.am, PCI_bus/PCI.c,
	PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, console/85c30.c,
	console/85c30.h, console/console.c, console/consolebsp.h,
	console/tbl85c30.c, include/bsp.h, include/gen2.h,
	include/irq-config.h, include/tm27.h, irq/FPGA.c, irq/irq.h,
	irq/irq_init.c, start/start.S, startup/Hwr_init.c,
	startup/bspstart.c, startup/linkcmds, timer/timer.c, tod/tod.c,
	vme/VMEConfig.h: Updated and tested with latest interrupt source.
	Modified with latest memory allocation, but this needs testing.
	* irq/no_pic.c: New file.

1 files changed, 71 insertions, 112 deletions

diff --git a/c/src/lib/libbsp/powerpc/score603e/irq/irq.h b/c/src/lib/libbsp/powerpc/score603e/irq/irq.h
index c06a546176..78353cd269 100644
--- a/c/src/lib/libbsp/powerpc/score603e/irq/irq.h
+++ b/c/src/lib/libbsp/powerpc/score603e/irq/irq.h
@@ -1,17 +1,19 @@
-/*
+/* irq.h
+ *
  *  This include file describe the data structure and the functions implemented
  *  by RTEMS to write interrupt handlers.
  *
- *  Copyright (C) 1999 valette@crf.canon.fr
- *
  *  This code is heavilly inspired by the public specification of STREAM V2
  *  that can be found at :
  *
- *      <http://www.chorus.com/Documentation/index.html> by following
+ *  <http://www.chorus.com/Documentation/index.html> by following
  *  the STREAM API Specification Document link.
  *
+ *  COPYRIGHT (c) 1989-2009.
+ *  On-Line Applications Research Corporation (OAR).
+ *
  *  The license and distribution terms for this file may be
- *  found in found in the file LICENSE in this distribution or at
+ *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
  *  $Id$
@@ -23,46 +25,13 @@
 #define BSP_SHARED_HANDLER_SUPPORT      1
 #include <rtems/irq.h>
 
-/*
- * 8259 edge/level control definitions at VIA
- */
-#define ISA8259_M_ELCR 		0x4d0
-#define ISA8259_S_ELCR 		0x4d1
-
-#define ELCRS_INT15_LVL         0x80
-#define ELCRS_INT14_LVL         0x40
-#define ELCRS_INT13_LVL         0x20
-#define ELCRS_INT12_LVL         0x10
-#define ELCRS_INT11_LVL         0x08
-#define ELCRS_INT10_LVL         0x04
-#define ELCRS_INT9_LVL          0x02
-#define ELCRS_INT8_LVL          0x01
-#define ELCRM_INT7_LVL          0x80
-#define ELCRM_INT6_LVL          0x40
-#define ELCRM_INT5_LVL          0x20
-#define ELCRM_INT4_LVL          0x10
-#define ELCRM_INT3_LVL          0x8
-#define ELCRM_INT2_LVL          0x4
-#define ELCRM_INT1_LVL          0x2
-#define ELCRM_INT0_LVL          0x1
-
-    /* PIC's command and mask registers */
-#define PIC_MASTER_COMMAND_IO_PORT		0x20	/* Master PIC command register */
-#define PIC_SLAVE_COMMAND_IO_PORT		0xa0	/* Slave PIC command register */
-#define PIC_MASTER_IMR_IO_PORT			0x21	/* Master PIC Interrupt Mask Register */
-#define PIC_SLAVE_IMR_IO_PORT		 	0xa1	/* Slave PIC Interrupt Mask Register */
-
-    /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
-#define PIC_EOSI	0x60	/* End of Specific Interrupt (EOSI) */
-#define	SLAVE_PIC_EOSI  0x62	/* End of Specific Interrupt (EOSI) for cascade */
-#define PIC_EOI		0x20	/* Generic End of Interrupt (EOI) */
-
 #ifndef ASM
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+
 /*
  * rtems_irq_number Definitions
  */
@@ -73,20 +42,30 @@ extern "C" {
 #define BSP_ISA_IRQ_NUMBER		(16)
 #define BSP_ISA_IRQ_LOWEST_OFFSET	(0)
 #define BSP_ISA_IRQ_MAX_OFFSET		(BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
+
 /*
  * PCI IRQ handlers related definitions
- * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
  */
 #define BSP_PCI_IRQ_NUMBER		(16)
 #define BSP_PCI_IRQ_LOWEST_OFFSET	(BSP_ISA_IRQ_NUMBER)
 #define BSP_PCI_IRQ_MAX_OFFSET		(BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
+
+/*
+ * PMC IRQ
+ */
+#define BSP_PMC_IRQ_NUMBER              (4)
+#define BSP_PMC_IRQ_LOWEST_OFFSET	(BSP_PCI_IRQ_MAX_OFFSET + 1)
+#define BSP_PMC_IRQ_MAX_OFFSET		(BSP_PMC_IRQ_LOWEST_OFFSET + BSP_PMC_IRQ_NUMBER - 1)
+
+
 /*
  * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
  * handler might be connected
  */
 #define BSP_PROCESSOR_IRQ_NUMBER	(1)
-#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
+#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PMC_IRQ_MAX_OFFSET + 1)
 #define BSP_PROCESSOR_IRQ_MAX_OFFSET	(BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
+
 /* Misc vectors for OPENPIC irqs (IPI, timers)
  */
 #define BSP_MISC_IRQ_NUMBER		(8)
@@ -98,96 +77,76 @@ extern "C" {
 #define BSP_IRQ_NUMBER			(BSP_MISC_IRQ_MAX_OFFSET + 1)
 #define BSP_LOWEST_OFFSET		(BSP_ISA_IRQ_LOWEST_OFFSET)
 #define BSP_MAX_OFFSET			(BSP_MISC_IRQ_MAX_OFFSET)
-/*
- * Some ISA IRQ symbolic name definition
- */
-#define BSP_ISA_PERIODIC_TIMER      	(0)
-#define BSP_ISA_KEYBOARD          	(1)
-#define BSP_ISA_UART_COM2_IRQ		(3)
-#define BSP_ISA_UART_COM1_IRQ		(4)
-#define BSP_ISA_RT_TIMER1	      	(8)
-#define BSP_ISA_RT_TIMER3		(10)
-/*
- * Some PCI IRQ symbolic name definition
- */
-#define BSP_PCI_IRQ0			(BSP_PCI_IRQ_LOWEST_OFFSET)
-#define BSP_PCI_ISA_BRIDGE_IRQ		(BSP_PCI_IRQ0)
-
-#if defined(mvme2100)
-#define BSP_DEC21143_IRQ                (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
-#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
-#define BSP_PCMIP_TYPE1_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
-#define BSP_PCMIP_TYPE2_SLOT0_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
-#define BSP_PCMIP_TYPE2_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
-#define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
-#define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
-#define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
-#define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
-#define BSP_UART_COM1_IRQ               (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
-#define BSP_FRONT_PANEL_ABORT_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
-#define BSP_RTC_IRQ                     (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
-#else
-#define BSP_UART_COM1_IRQ		BSP_ISA_UART_COM1_IRQ
-#define BSP_UART_COM2_IRQ		BSP_ISA_UART_COM2_IRQ
-#endif
 
 /*
  * Some Processor execption handled as RTEMS IRQ symbolic name definition
  */
 #define BSP_DECREMENTER			(BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
 
-
 /*
- * Type definition for RTEMS managed interrupts
+ * First Score Unique IRQ
  */
-typedef unsigned short rtems_i8259_masks;
+#define Score_IRQ_First ( BSP_PCI_IRQ_LOWEST_OFFSET )
 
-extern  volatile rtems_i8259_masks i8259s_cache;
-
-/*-------------------------------------------------------------------------+
-| Function Prototypes.
-+--------------------------------------------------------------------------*/
 /*
- * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
+ * The Following Are part of a Score603e FPGA.
  */
-void BSP_i8259s_init(void);
+#define SCORE603E_IRQ00   ( Score_IRQ_First +  0 )
+#define SCORE603E_IRQ01   ( Score_IRQ_First +  1 )
+#define SCORE603E_IRQ02   ( Score_IRQ_First +  2 )
+#define SCORE603E_IRQ03   ( Score_IRQ_First +  3 )
+#define SCORE603E_IRQ04   ( Score_IRQ_First +  4 )
+#define SCORE603E_IRQ05   ( Score_IRQ_First +  5 )
+#define SCORE603E_IRQ06   ( Score_IRQ_First +  6 )
+#define SCORE603E_IRQ07   ( Score_IRQ_First +  7 )
+#define SCORE603E_IRQ08   ( Score_IRQ_First +  8 )
+#define SCORE603E_IRQ09   ( Score_IRQ_First +  9 )
+#define SCORE603E_IRQ10   ( Score_IRQ_First + 10 )
+#define SCORE603E_IRQ11   ( Score_IRQ_First + 11 )
+#define SCORE603E_IRQ12   ( Score_IRQ_First + 12 )
+#define SCORE603E_IRQ13   ( Score_IRQ_First + 13 )
+#define SCORE603E_IRQ14   ( Score_IRQ_First + 14 )
+#define SCORE603E_IRQ15   ( Score_IRQ_First + 15 )
+
+#define SCORE603E_TIMER1_IRQ           SCORE603E_IRQ00
+#define SCORE603E_TIMER2_IRQ           SCORE603E_IRQ01
+#define SCORE603E_TIMER3_IRQ           SCORE603E_IRQ02
+#define SCORE603E_85C30_1_IRQ          SCORE603E_IRQ03
+#define SCORE603E_85C30_0_IRQ          SCORE603E_IRQ04
+#define SCORE603E_RTC_IRQ              SCORE603E_IRQ05
+#define SCORE603E_PCI_IRQ_0            SCORE603E_IRQ06
+#define SCORE603E_PCI_IRQ_1            SCORE603E_IRQ07
+#define SCORE603E_PCI_IRQ_2            SCORE603E_IRQ08
+#define SCORE603E_PCI_IRQ_3            SCORE603E_IRQ09
+#define SCORE603E_UNIVERSE_IRQ         SCORE603E_IRQ10
+#define SCORE603E_1553_IRQ             SCORE603E_IRQ11
+#define SCORE603E_MAIL_BOX_IRQ_0       SCORE603E_IRQ12
+#define SCORE603E_MAIL_BOX_IRQ_1       SCORE603E_IRQ13
+#define SCORE603E_MAIL_BOX_IRQ_2       SCORE603E_IRQ14
+#define SCORE603E_MAIL_BOX_IRQ_3       SCORE603E_IRQ15
 
 /*
- * function to disable a particular irq at 8259 level. After calling
- * this function, even if the device asserts the interrupt line it will
- * not be propagated further to the processor
- *
- * RETURNS: 1/0 if the interrupt was enabled/disabled originally or
- *          a value < 0 on error.
- */
-int BSP_irq_disable_at_i8259s        (const rtems_irq_number irqLine);
-/*
- * function to enable a particular irq at 8259 level. After calling
- * this function, if the device asserts the interrupt line it will
- * be propagated further to the processor
- */
-int BSP_irq_enable_at_i8259s		(const rtems_irq_number irqLine);
-/*
- * function to acknowledge a particular irq at 8259 level. After calling
- * this function, if a device asserts an enabled interrupt line it will
- * be propagated further to the processor. Mainly usefull for people
- * writing raw handlers as this is automagically done for RTEMS managed
- * handlers.
+ * The Score FPGA maps all interrupts comming from the PMC card to
+ * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be
+ * read to indicate which interrupt was chained to the FPGA.
  */
-int BSP_irq_ack_at_i8259s           	(const rtems_irq_number irqLine);
+#define SCORE603E_IRQ16   ( Score_IRQ_First + 16 )
+#define SCORE603E_IRQ17   ( Score_IRQ_First + 17 )
+#define SCORE603E_IRQ18   ( Score_IRQ_First + 18 )
+#define SCORE603E_IRQ19   ( Score_IRQ_First + 19 )
+
 /*
- * function to check if a particular irq is enabled at 8259 level. After calling
+ * IRQ'a read from the PMC card
  */
-int BSP_irq_enabled_at_i8259s        	(const rtems_irq_number irqLine);
-
-extern void BSP_rtems_irq_mng_init(unsigned cpuId);
-extern void BSP_i8259s_init(void);
+#define SCORE603E_85C30_4_IRQ          SCORE603E_IRQ16    /* SCC 422-1 */
+#define SCORE603E_85C30_2_IRQ          SCORE603E_IRQ17    /* SCC 232-1 */
+#define SCORE603E_85C30_5_IRQ          SCORE603E_IRQ18    /* SCC 422-2 */
+#define SCORE603E_85C30_3_IRQ          SCORE603E_IRQ19    /* SCC 232-2 */
 
-/* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */
-/* #include <bsp/irq_supp.h> */
+#define MAX_BOARD_IRQS                 SCORE603E_IRQ19
 
 #ifdef __cplusplus
-};
+}
 #endif
 
 #endif