2009-05-05 Jennifer Averett <jennifer.averett@OARcorp.com>

	* Makefile.am, configure.ac, preinstall.am, PCI_bus/PCI.c,
	PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, console/85c30.c,
	console/85c30.h, console/console.c, console/consolebsp.h,
	console/tbl85c30.c, include/bsp.h, include/gen2.h,
	include/irq-config.h, include/tm27.h, irq/FPGA.c, irq/irq.h,
	irq/irq_init.c, start/start.S, startup/Hwr_init.c,
	startup/bspstart.c, startup/linkcmds, timer/timer.c, tod/tod.c,
	vme/VMEConfig.h: Updated and tested with latest interrupt source.
	Modified with latest memory allocation, but this needs testing.
	* irq/no_pic.c: New file.

4 files changed, 212 insertions, 397 deletions

diff --git a/c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c b/c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c
index 4ce59314ff..91a8e7a9df 100644
--- a/c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c
+++ b/c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c
@@ -1,20 +1,23 @@
 /*  FPGA.c -- Bridge for second and subsequent generations
  *
- *  COPYRIGHT (c) 1989-2008.
+ *  COPYRIGHT (c) 1989-2009.
  *  On-Line Applications Research Corporation (OAR).
  *
- *  The license and distribution terms for this file may in
- *  the file LICENSE in this distribution or at
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
  *  $Id$
  */
 
 #include <bsp.h>
+#include <bsp/irq.h>
 #include <string.h>
 #include <fcntl.h>
 #include <assert.h>
 
+#include <rtems/libio.h>
+#include <rtems/libcsupport.h>
 #include <rtems/bspIo.h>
 
 /*
@@ -25,24 +28,23 @@ void initialize_PCI_bridge (void)
   /* Note: Accept DINKs setup of the PCI Bridge and don't 
    *       change anything.
    */
-  printk("initialize_PCI_bridge: \n");
 }
 
 void set_irq_mask(
   uint16_t         value
 )
 {
-  uint16_t          *loc;
+  volatile uint16_t   *loc;
 
   loc = (uint16_t*)SCORE603E_FPGA_MASK_DATA;
 
   *loc = value;
 }
 
-uint16_t         get_irq_mask(voi)
+uint16_t get_irq_mask( void )
 {
-  uint16_t          *loc;
-  uint16_t          value;
+  volatile uint16_t  *loc;
+  uint16_t            value;
 
   loc =  (uint16_t*)SCORE603E_FPGA_MASK_DATA;
 
@@ -51,6 +53,32 @@ uint16_t         get_irq_mask(voi)
   return value;
 }
 
+void mask_irq(
+  uint16_t         irq_idx
+)
+{
+  uint16_t         value;
+  uint32_t         mask_idx = irq_idx;
+
+  value = get_irq_mask();
+
+#if (HAS_PMC_PSC8)
+  switch (irq_idx + Score_IRQ_First ) {
+    case SCORE603E_85C30_4_IRQ:
+    case SCORE603E_85C30_2_IRQ:
+    case SCORE603E_85C30_5_IRQ:
+    case SCORE603E_85C30_3_IRQ:
+      mask_idx = SCORE603E_PCI_IRQ_0 - Score_IRQ_First;
+      break;
+    default:
+      break;
+  }
+#endif
+
+  value |= (0x1 << mask_idx);
+  set_irq_mask( value );
+}
+
 void unmask_irq(
   uint16_t         irq_idx
 )
@@ -98,7 +126,7 @@ uint16_t         read_and_clear_PMC_irq(
   uint16_t            irq
 )
 {
-  uint16_t            status_word = irq;
+  uint16_t   status_word = irq;
 
   status_word = (*BSP_PMC_STATUS_ADDRESS);
 
@@ -137,14 +165,15 @@ uint16_t         read_and_clear_irq(void)
 {
   uint16_t            irq;
 
-  irq = (*SCORE603E_FPGA_VECT_DATA);
 
+  irq = (*SCORE603E_FPGA_VECT_DATA);
+  Processor_Synchronize();
   if ((irq & 0xffff0) != 0x10) {
-    printk( "ERROR:: no irq data\n");
+    printk( "read_and_clear_irq:: ERROR==>no irq data 0x%x\n", irq);
     return (irq | 0x80);
   }
 
   irq &=0xf;
-
+  irq += Score_IRQ_First;
   return irq;
 }
diff --git a/c/src/lib/libbsp/powerpc/score603e/irq/irq.h b/c/src/lib/libbsp/powerpc/score603e/irq/irq.h
index c06a546176..78353cd269 100644
--- a/c/src/lib/libbsp/powerpc/score603e/irq/irq.h
+++ b/c/src/lib/libbsp/powerpc/score603e/irq/irq.h
@@ -1,17 +1,19 @@
-/*
+/* irq.h
+ *
  *  This include file describe the data structure and the functions implemented
  *  by RTEMS to write interrupt handlers.
  *
- *  Copyright (C) 1999 valette@crf.canon.fr
- *
  *  This code is heavilly inspired by the public specification of STREAM V2
  *  that can be found at :
  *
- *      <http://www.chorus.com/Documentation/index.html> by following
+ *  <http://www.chorus.com/Documentation/index.html> by following
  *  the STREAM API Specification Document link.
  *
+ *  COPYRIGHT (c) 1989-2009.
+ *  On-Line Applications Research Corporation (OAR).
+ *
  *  The license and distribution terms for this file may be
- *  found in found in the file LICENSE in this distribution or at
+ *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
  *  $Id$
@@ -23,46 +25,13 @@
 #define BSP_SHARED_HANDLER_SUPPORT      1
 #include <rtems/irq.h>
 
-/*
- * 8259 edge/level control definitions at VIA
- */
-#define ISA8259_M_ELCR 		0x4d0
-#define ISA8259_S_ELCR 		0x4d1
-
-#define ELCRS_INT15_LVL         0x80
-#define ELCRS_INT14_LVL         0x40
-#define ELCRS_INT13_LVL         0x20
-#define ELCRS_INT12_LVL         0x10
-#define ELCRS_INT11_LVL         0x08
-#define ELCRS_INT10_LVL         0x04
-#define ELCRS_INT9_LVL          0x02
-#define ELCRS_INT8_LVL          0x01
-#define ELCRM_INT7_LVL          0x80
-#define ELCRM_INT6_LVL          0x40
-#define ELCRM_INT5_LVL          0x20
-#define ELCRM_INT4_LVL          0x10
-#define ELCRM_INT3_LVL          0x8
-#define ELCRM_INT2_LVL          0x4
-#define ELCRM_INT1_LVL          0x2
-#define ELCRM_INT0_LVL          0x1
-
-    /* PIC's command and mask registers */
-#define PIC_MASTER_COMMAND_IO_PORT		0x20	/* Master PIC command register */
-#define PIC_SLAVE_COMMAND_IO_PORT		0xa0	/* Slave PIC command register */
-#define PIC_MASTER_IMR_IO_PORT			0x21	/* Master PIC Interrupt Mask Register */
-#define PIC_SLAVE_IMR_IO_PORT		 	0xa1	/* Slave PIC Interrupt Mask Register */
-
-    /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
-#define PIC_EOSI	0x60	/* End of Specific Interrupt (EOSI) */
-#define	SLAVE_PIC_EOSI  0x62	/* End of Specific Interrupt (EOSI) for cascade */
-#define PIC_EOI		0x20	/* Generic End of Interrupt (EOI) */
-
 #ifndef ASM
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+
 /*
  * rtems_irq_number Definitions
  */
@@ -73,20 +42,30 @@ extern "C" {
 #define BSP_ISA_IRQ_NUMBER		(16)
 #define BSP_ISA_IRQ_LOWEST_OFFSET	(0)
 #define BSP_ISA_IRQ_MAX_OFFSET		(BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
+
 /*
  * PCI IRQ handlers related definitions
- * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
  */
 #define BSP_PCI_IRQ_NUMBER		(16)
 #define BSP_PCI_IRQ_LOWEST_OFFSET	(BSP_ISA_IRQ_NUMBER)
 #define BSP_PCI_IRQ_MAX_OFFSET		(BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
+
+/*
+ * PMC IRQ
+ */
+#define BSP_PMC_IRQ_NUMBER              (4)
+#define BSP_PMC_IRQ_LOWEST_OFFSET	(BSP_PCI_IRQ_MAX_OFFSET + 1)
+#define BSP_PMC_IRQ_MAX_OFFSET		(BSP_PMC_IRQ_LOWEST_OFFSET + BSP_PMC_IRQ_NUMBER - 1)
+
+
 /*
  * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
  * handler might be connected
  */
 #define BSP_PROCESSOR_IRQ_NUMBER	(1)
-#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
+#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PMC_IRQ_MAX_OFFSET + 1)
 #define BSP_PROCESSOR_IRQ_MAX_OFFSET	(BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
+
 /* Misc vectors for OPENPIC irqs (IPI, timers)
  */
 #define BSP_MISC_IRQ_NUMBER		(8)
@@ -98,96 +77,76 @@ extern "C" {
 #define BSP_IRQ_NUMBER			(BSP_MISC_IRQ_MAX_OFFSET + 1)
 #define BSP_LOWEST_OFFSET		(BSP_ISA_IRQ_LOWEST_OFFSET)
 #define BSP_MAX_OFFSET			(BSP_MISC_IRQ_MAX_OFFSET)
-/*
- * Some ISA IRQ symbolic name definition
- */
-#define BSP_ISA_PERIODIC_TIMER      	(0)
-#define BSP_ISA_KEYBOARD          	(1)
-#define BSP_ISA_UART_COM2_IRQ		(3)
-#define BSP_ISA_UART_COM1_IRQ		(4)
-#define BSP_ISA_RT_TIMER1	      	(8)
-#define BSP_ISA_RT_TIMER3		(10)
-/*
- * Some PCI IRQ symbolic name definition
- */
-#define BSP_PCI_IRQ0			(BSP_PCI_IRQ_LOWEST_OFFSET)
-#define BSP_PCI_ISA_BRIDGE_IRQ		(BSP_PCI_IRQ0)
-
-#if defined(mvme2100)
-#define BSP_DEC21143_IRQ                (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
-#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
-#define BSP_PCMIP_TYPE1_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
-#define BSP_PCMIP_TYPE2_SLOT0_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
-#define BSP_PCMIP_TYPE2_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
-#define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
-#define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
-#define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
-#define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
-#define BSP_UART_COM1_IRQ               (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
-#define BSP_FRONT_PANEL_ABORT_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
-#define BSP_RTC_IRQ                     (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
-#else
-#define BSP_UART_COM1_IRQ		BSP_ISA_UART_COM1_IRQ
-#define BSP_UART_COM2_IRQ		BSP_ISA_UART_COM2_IRQ
-#endif
 
 /*
  * Some Processor execption handled as RTEMS IRQ symbolic name definition
  */
 #define BSP_DECREMENTER			(BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
 
-
 /*
- * Type definition for RTEMS managed interrupts
+ * First Score Unique IRQ
  */
-typedef unsigned short rtems_i8259_masks;
+#define Score_IRQ_First ( BSP_PCI_IRQ_LOWEST_OFFSET )
 
-extern  volatile rtems_i8259_masks i8259s_cache;
-
-/*-------------------------------------------------------------------------+
-| Function Prototypes.
-+--------------------------------------------------------------------------*/
 /*
- * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
+ * The Following Are part of a Score603e FPGA.
  */
-void BSP_i8259s_init(void);
+#define SCORE603E_IRQ00   ( Score_IRQ_First +  0 )
+#define SCORE603E_IRQ01   ( Score_IRQ_First +  1 )
+#define SCORE603E_IRQ02   ( Score_IRQ_First +  2 )
+#define SCORE603E_IRQ03   ( Score_IRQ_First +  3 )
+#define SCORE603E_IRQ04   ( Score_IRQ_First +  4 )
+#define SCORE603E_IRQ05   ( Score_IRQ_First +  5 )
+#define SCORE603E_IRQ06   ( Score_IRQ_First +  6 )
+#define SCORE603E_IRQ07   ( Score_IRQ_First +  7 )
+#define SCORE603E_IRQ08   ( Score_IRQ_First +  8 )
+#define SCORE603E_IRQ09   ( Score_IRQ_First +  9 )
+#define SCORE603E_IRQ10   ( Score_IRQ_First + 10 )
+#define SCORE603E_IRQ11   ( Score_IRQ_First + 11 )
+#define SCORE603E_IRQ12   ( Score_IRQ_First + 12 )
+#define SCORE603E_IRQ13   ( Score_IRQ_First + 13 )
+#define SCORE603E_IRQ14   ( Score_IRQ_First + 14 )
+#define SCORE603E_IRQ15   ( Score_IRQ_First + 15 )
+
+#define SCORE603E_TIMER1_IRQ           SCORE603E_IRQ00
+#define SCORE603E_TIMER2_IRQ           SCORE603E_IRQ01
+#define SCORE603E_TIMER3_IRQ           SCORE603E_IRQ02
+#define SCORE603E_85C30_1_IRQ          SCORE603E_IRQ03
+#define SCORE603E_85C30_0_IRQ          SCORE603E_IRQ04
+#define SCORE603E_RTC_IRQ              SCORE603E_IRQ05
+#define SCORE603E_PCI_IRQ_0            SCORE603E_IRQ06
+#define SCORE603E_PCI_IRQ_1            SCORE603E_IRQ07
+#define SCORE603E_PCI_IRQ_2            SCORE603E_IRQ08
+#define SCORE603E_PCI_IRQ_3            SCORE603E_IRQ09
+#define SCORE603E_UNIVERSE_IRQ         SCORE603E_IRQ10
+#define SCORE603E_1553_IRQ             SCORE603E_IRQ11
+#define SCORE603E_MAIL_BOX_IRQ_0       SCORE603E_IRQ12
+#define SCORE603E_MAIL_BOX_IRQ_1       SCORE603E_IRQ13
+#define SCORE603E_MAIL_BOX_IRQ_2       SCORE603E_IRQ14
+#define SCORE603E_MAIL_BOX_IRQ_3       SCORE603E_IRQ15
 
 /*
- * function to disable a particular irq at 8259 level. After calling
- * this function, even if the device asserts the interrupt line it will
- * not be propagated further to the processor
- *
- * RETURNS: 1/0 if the interrupt was enabled/disabled originally or
- *          a value < 0 on error.
- */
-int BSP_irq_disable_at_i8259s        (const rtems_irq_number irqLine);
-/*
- * function to enable a particular irq at 8259 level. After calling
- * this function, if the device asserts the interrupt line it will
- * be propagated further to the processor
- */
-int BSP_irq_enable_at_i8259s		(const rtems_irq_number irqLine);
-/*
- * function to acknowledge a particular irq at 8259 level. After calling
- * this function, if a device asserts an enabled interrupt line it will
- * be propagated further to the processor. Mainly usefull for people
- * writing raw handlers as this is automagically done for RTEMS managed
- * handlers.
+ * The Score FPGA maps all interrupts comming from the PMC card to
+ * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be
+ * read to indicate which interrupt was chained to the FPGA.
  */
-int BSP_irq_ack_at_i8259s           	(const rtems_irq_number irqLine);
+#define SCORE603E_IRQ16   ( Score_IRQ_First + 16 )
+#define SCORE603E_IRQ17   ( Score_IRQ_First + 17 )
+#define SCORE603E_IRQ18   ( Score_IRQ_First + 18 )
+#define SCORE603E_IRQ19   ( Score_IRQ_First + 19 )
+
 /*
- * function to check if a particular irq is enabled at 8259 level. After calling
+ * IRQ'a read from the PMC card
  */
-int BSP_irq_enabled_at_i8259s        	(const rtems_irq_number irqLine);
-
-extern void BSP_rtems_irq_mng_init(unsigned cpuId);
-extern void BSP_i8259s_init(void);
+#define SCORE603E_85C30_4_IRQ          SCORE603E_IRQ16    /* SCC 422-1 */
+#define SCORE603E_85C30_2_IRQ          SCORE603E_IRQ17    /* SCC 232-1 */
+#define SCORE603E_85C30_5_IRQ          SCORE603E_IRQ18    /* SCC 422-2 */
+#define SCORE603E_85C30_3_IRQ          SCORE603E_IRQ19    /* SCC 232-2 */
 
-/* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */
-/* #include <bsp/irq_supp.h> */
+#define MAX_BOARD_IRQS                 SCORE603E_IRQ19
 
 #ifdef __cplusplus
-};
+}
 #endif
 
 #endif
diff --git a/c/src/lib/libbsp/powerpc/score603e/irq/irq_init.c b/c/src/lib/libbsp/powerpc/score603e/irq/irq_init.c
index 63930a7293..ea0e257a2e 100644
--- a/c/src/lib/libbsp/powerpc/score603e/irq/irq_init.c
+++ b/c/src/lib/libbsp/powerpc/score603e/irq/irq_init.c
@@ -1,4 +1,5 @@
-/*
+/* irq_init.c
+ *
  *  This file contains the implementation of rtems initialization
  *  related to interrupt handling.
  *
@@ -21,16 +22,14 @@
 #include <libcpu/spr.h>
 #include <bsp/pci.h>
 #include <bsp/residual.h>
-#include <bsp/openpic.h>
 #include <bsp/irq.h>
 #include <bsp.h>
 #include <libcpu/raw_exception.h>
-#include <bsp/motorola.h>
 #include <rtems/bspIo.h>
 
 #define SHOW_ISA_PCI_BRIDGE_SETTINGS 1
 #define SCAN_PCI_PRINT               1
-#define TRACE_IRQ_INIT               1
+#define TRACE_IRQ_INIT               0 
 
 typedef struct {
   unsigned char bus;	/* few chance the PCI/ISA bridge is not on first bus but ... */
@@ -39,223 +38,26 @@ typedef struct {
 } pci_isa_bridge_device;
 
 pci_isa_bridge_device* via_82c586 = 0;
-static pci_isa_bridge_device bridge;
 
 extern unsigned int external_exception_vector_prolog_code_size[];
 extern void external_exception_vector_prolog_code(void);
 extern unsigned int decrementer_exception_vector_prolog_code_size[];
 extern void decrementer_exception_vector_prolog_code(void);
 
-/*
- * default on/off function
- */
-static void nop_func(void){}
-/*
- * default isOn function
- */
-static int not_connected(void) {return 0;}
-/*
- * default possible isOn function
- */
-static int connected(void) {return 1;}
+static void IRQ_Default_rtems_irq_hdl( rtems_irq_hdl_param ptr ) {}
+static void IRQ_Default_rtems_irq_enable (const struct __rtems_irq_connect_data__ *ptr){}
+static void IRQ_Default_rtems_irq_disable(const struct __rtems_irq_connect_data__ *ptr){}
+static int  IRQ_Default_rtems_irq_is_enabled(const struct __rtems_irq_connect_data__ *ptr){ return 1; }
 
 static rtems_irq_connect_data     	rtemsIrq[BSP_IRQ_NUMBER];
 static rtems_irq_global_settings     	initial_config;
-static rtems_irq_connect_data     	defaultIrq = {
-  /* vectorIdex,	 hdl		, handle	, on		, off		, isOn */
-  0, 			 nop_func	, NULL		, nop_func	, nop_func	, not_connected
-};
-static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
-  /*
-   * actual priorities for interrupt :
-   *	0   means that only current interrupt is masked
-   *	255 means all other interrupts are masked
-   */
-  /*
-   * ISA interrupts.
-   * The second entry has a priority of 255 because
-   * it is the slave pic entry and should always remain
-   * unmasked.
-   */
-  0,0,
-  255,
-  0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
-  /*
-   * PCI Interrupts
-   */
-  8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */
-  /*
-   * Processor exceptions handled as interrupts
-   */
-  0
-};
 
-#if defined(mvme2100)
-static unsigned char mvme2100_openpic_initpolarities[16] = {
-    0,  /* Not used - should be disabled */
-    0,	/* DEC21143 Controller */
-    0,  /* PMC/PC-MIP Type I Slot 0 */
-    0,  /* PC-MIP Type I Slot 1 */
-    0,  /* PC-MIP Type II Slot 0 */
-    0,  /* PC-MIP Type II Slot 1 */
-    0,  /* Not used - should be disabled */
-    0,  /* PCI Expansion Interrupt A/Universe II (LINT0) */
-    0,  /* PCI Expansion Interrupt B/Universe II (LINT1) */
-    0,  /* PCI Expansion Interrupt C/Universe II (LINT2) */
-    0,  /* PCI Expansion Interrupt D/Universe II (LINT3) */
-    0,  /* Not used - should be disabled */
-    0,  /* Not used - should be disabled */
-    1,  /* 16550 UART */
-    0,  /* Front panel Abort Switch */
-    0,  /* RTC IRQ */
-};
-
-static unsigned char mvme2100_openpic_initsenses[] = {
-    0,  /* Not used - should be disabled */
-    1,	/* DEC21143 Controller */
-    1,  /* PMC/PC-MIP Type I Slot 0 */
-    1,  /* PC-MIP Type I Slot 1 */
-    1,  /* PC-MIP Type II Slot 0 */
-    1,  /* PC-MIP Type II Slot 1 */
-    0,  /* Not used - should be disabled */
-    1,  /* PCI Expansion Interrupt A/Universe II (LINT0) */
-    1,  /* PCI Expansion Interrupt B/Universe II (LINT1) */
-    1,  /* PCI Expansion Interrupt C/Universe II (LINT2) */
-    1,  /* PCI Expansion Interrupt D/Universe II (LINT3) */
-    0,  /* Not used - should be disabled */
-    0,  /* Not used - should be disabled */
-    1,  /* 16550 UART */
-    0,  /* Front panel Abort Switch */
-    1,  /* RTC IRQ */
-};
-#else
-static unsigned char mcp750_openpic_initpolarities[16] = {
-    1,  /* 8259 cascade */
-    0,	/* all the rest of them */
-};
-
-static unsigned char mcp750_openpic_initsenses[] = {
-    1,	/* MCP750_INT_PCB(8259) */
-    0,	/* MCP750_INT_FALCON_ECC_ERR */
-    1,	/* MCP750_INT_PCI_ETHERNET */
-    1,	/* MCP750_INT_PCI_PMC */
-    1,	/* MCP750_INT_PCI_WATCHDOG_TIMER1 */
-    1,	/* MCP750_INT_PCI_PRST_SIGNAL */
-    1,	/* MCP750_INT_PCI_FALL_SIGNAL */
-    1,	/* MCP750_INT_PCI_DEG_SIGNAL */
-    1,	/* MCP750_INT_PCI_BUS1_INTA */
-    1,	/* MCP750_INT_PCI_BUS1_INTB */
-    1,	/* MCP750_INT_PCI_BUS1_INTC */
-    1,	/* MCP750_INT_PCI_BUS1_INTD */
-    1,	/* MCP750_INT_PCI_BUS2_INTA */
-    1,	/* MCP750_INT_PCI_BUS2_INTB */
-    1,	/* MCP750_INT_PCI_BUS2_INTC */
-    1,	/* MCP750_INT_PCI_BUS2_INTD */
+static rtems_irq_connect_data     	defaultIrq = {
+/*name,	 hdl				handle	on				off				isOn */
+  0,	 IRQ_Default_rtems_irq_hdl,	NULL,	IRQ_Default_rtems_irq_enable,	IRQ_Default_rtems_irq_disable,	IRQ_Default_rtems_irq_is_enabled
 };
-#endif
-
-void VIA_isa_bridge_interrupts_setup(void)
-{
-  pci_isa_bridge_device pci_dev;
-  unsigned int temp;
-  unsigned char tmp;
-  unsigned char maxBus;
-  unsigned found = 0;
-
-  maxBus = pci_bus_count();
-  pci_dev.function 	= 0; /* Assumes the bidge is the first function */
-
-  for (pci_dev.bus = 0; pci_dev.bus < maxBus; pci_dev.bus++) {
-#ifdef SCAN_PCI_PRINT
-    printk("isa_bridge_interrupts_setup: Scanning bus %d\n", pci_dev.bus);
-#endif
-    for (pci_dev.device = 0; pci_dev.device < PCI_MAX_DEVICES; pci_dev.device++) {
-#ifdef SCAN_PCI_PRINT
-      printk("isa_bridge_interrupts_setup: Scanning device %d\n", pci_dev.device);
-#endif
-      pci_read_config_dword(pci_dev.bus, pci_dev.device,  pci_dev.function,
-			       PCI_VENDOR_ID, &temp);
-#ifdef SCAN_PCI_PRINT
-      printk("Vendor/device = %x\n", temp);
-#endif
-      if ((temp == (((unsigned short) PCI_VENDOR_ID_VIA) | (PCI_DEVICE_ID_VIA_82C586_0 << 16)))
-	 ) {
-	bridge = pci_dev;
-	via_82c586 = &bridge;
-#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
-	/*
-	 * Should print : bus = 0, device = 11, function = 0 on a MCP750.
-	 */
-	printk("Via PCI/ISA bridge found at bus = %d, device = %d, function = %d\n",
-	       via_82c586->bus,
-	       via_82c586->device,
-	       via_82c586->function);
-#endif
-	found = 1;
-	goto loop_exit;
-
-      }
-    }
-  }
-loop_exit:
-  if (!found) BSP_panic("VIA_82C586 PCI/ISA bridge not found!n");
 
-  tmp = inb(0x810);
-  if  ( !(tmp & 0x2)) {
-#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
-    printk("This is a second generation MCP750 board\n");
-    printk("We must reprogram the PCI/ISA bridge...\n");
-#endif
-    pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
-			 0x47,  &tmp);
-#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
-    printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp);
-#endif
-    /*
-     * Enable 4D0/4D1 ISA interrupt level/edge config registers
-     */
-    tmp |= 0x20;
-    pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
-			  0x47, tmp);
-    /*
-     * Now program the ISA interrupt edge/level
-     */
-    tmp = ELCRS_INT9_LVL | ELCRS_INT10_LVL | ELCRS_INT11_LVL;
-    outb(tmp, ISA8259_S_ELCR);
-    tmp = ELCRM_INT5_LVL;
-    outb(tmp, ISA8259_M_ELCR);;
-    /*
-     * Set the Interrupt inputs to non-inverting level interrupt
-     */
-    pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
-			    0x54, &tmp);
-#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
-    printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp);
-#endif
-    tmp = 0;
-    pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
-			  0x54, tmp);
-  }
-  else {
-#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
-    printk("This is a first generation MCP750 board\n");
-    printk("We just show the actual value used by PCI/ISA bridge\n");
-#endif
-    pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
-			 0x47,  &tmp);
-#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
-    printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp);
-#endif
-    /*
-     * Show the Interrupt inputs inverting/non-inverting level status
-     */
-    pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
-			 0x54, &tmp);
-#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
-    printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp);
-#endif
-  }
-}
+static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER];
 
   /*
    * This code assumes the exceptions management setup has already
@@ -265,54 +67,11 @@ loop_exit:
    */
 void BSP_rtems_irq_mng_init(unsigned cpuId)
 {
-#if !defined(mvme2100)
-  int known_cpi_isa_bridge = 0;
-#endif
-  rtems_raw_except_connect_data vectorDesc;
   int i;
 
   /*
    * First initialize the Interrupt management hardware
    */
-#if defined(mvme2100)
-#ifdef TRACE_IRQ_INIT 
-  printk("Going to initialize EPIC interrupt controller (openpic compliant)\n");
-#endif
-  openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses);
-#else
-#ifdef TRACE_IRQ_INIT 
-  printk("Going to initialize raven interrupt controller (openpic compliant)\n");
-#endif
-  openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses);
-#endif       
-
-#if !defined(mvme2100)
-#ifdef TRACE_IRQ_INIT  
-  printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
-#endif
-  if ( currentBoard == MESQUITE ) {
-    VIA_isa_bridge_interrupts_setup();
-    known_cpi_isa_bridge = 1;
-  }
-  if ( currentBoard == MVME_2300 ) {
-    /* nothing to do for W83C553 bridge */
-    known_cpi_isa_bridge = 1;
-  }
-  if ( currentBoard == MTX_WO_PP || currentBoard == MTX_W_PP ) {
-     /* W83C554, don't to anything at the moment.  gregm 11/6/2002 */
-     known_cpi_isa_bridge = 1;
-  }
-
-  if (!known_cpi_isa_bridge) {
-    printk("Please add code for PCI/ISA bridge init to libbsp/powerpc/shared/irq/irq_init.c\n");
-    printk("If your card works correctly please add a test and set known_cpi_isa_bridge to true\n");
-    printk("currentBoard = %i\n", currentBoard);
-  }
-#ifdef TRACE_IRQ_INIT
-  printk("Going to initialize the ISA PC legacy IRQ management hardware\n");
-#endif
-  BSP_i8259s_init();
-#endif
 
   /*
    * Initialize RTEMS management interrupt table
@@ -321,9 +80,14 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
      * re-init the rtemsIrq table
      */
     for (i = 0; i < BSP_IRQ_NUMBER; i++) {
+      irqPrioTable[i]  = 8;
       rtemsIrq[i]      = defaultIrq;
       rtemsIrq[i].name = i;
+#ifdef BSP_SHARED_HANDLER_SUPPORT
+      rtemsIrq[i].next_handler = NULL;
+#endif
     }
+
     /*
      * Init initial Interrupt management config
      */
@@ -340,27 +104,6 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
       BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
     }
 
-  /*
-   * We must connect the raw irq handler for the two
-   * expected interrupt sources : decrementer and external interrupts.
-   */
-    vectorDesc.exceptIndex 	=	ASM_DEC_VECTOR;
-    vectorDesc.hdl.vector	=	ASM_DEC_VECTOR;
-    vectorDesc.hdl.raw_hdl	=	decrementer_exception_vector_prolog_code;
-    vectorDesc.hdl.raw_hdl_size	=	(unsigned) decrementer_exception_vector_prolog_code_size;
-    vectorDesc.on		=	nop_func;
-    vectorDesc.off		=	nop_func;
-    vectorDesc.isOn		=	connected;
-    if (!ppc_set_exception (&vectorDesc)) {
-      BSP_panic("Unable to initialize RTEMS decrementer raw exception\n");
-    }
-    vectorDesc.exceptIndex	=	ASM_EXT_VECTOR;
-    vectorDesc.hdl.vector	=	ASM_EXT_VECTOR;
-    vectorDesc.hdl.raw_hdl	=	external_exception_vector_prolog_code;
-    vectorDesc.hdl.raw_hdl_size	=	(unsigned) external_exception_vector_prolog_code_size;
-    if (!ppc_set_exception (&vectorDesc)) {
-      BSP_panic("Unable to initialize RTEMS external raw exception\n");
-    }
 #ifdef TRACE_IRQ_INIT
     printk("RTEMS IRQ management is now operational\n");
 #endif
diff --git a/c/src/lib/libbsp/powerpc/score603e/irq/no_pic.c b/c/src/lib/libbsp/powerpc/score603e/irq/no_pic.c
new file mode 100644
index 0000000000..c30fb20156
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/score603e/irq/no_pic.c
@@ -0,0 +1,84 @@
+/*
+ *
+ *  This file contains the implementation of the function described in irq.h
+ *
+ *  COPYRIGHT (c) 1989-2009.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/irq_supp.h>
+#include <libcpu/raw_exception.h>
+
+static rtems_irq_connect_data *rtems_hdl_tbl;
+static rtems_irq_connect_data  dflt_entry;
+
+/*
+ * High level IRQ handler called from shared_raw_irq_code_entry
+ */
+int C_dispatch_irq_handler(
+  struct _BSP_Exception_frame *frame,
+  unsigned int excNum
+)
+{
+  register unsigned int irq;
+#if (HAS_PMC_PSC8)
+  uint16_t              check_irq;
+  uint16_t              status_word;
+#endif
+
+  if (excNum == ASM_DEC_VECTOR) {
+    bsp_irq_dispatch_list(rtems_hdl_tbl, BSP_DECREMENTER, dflt_entry.hdl);
+    return 0;
+  }
+
+  irq = read_and_clear_irq();
+
+#if (HAS_PMC_PSC8)
+   if (irq ==  SCORE603E_PCI_IRQ_0) {
+     status_word = read_and_clear_PMC_irq( irq );
+     for (check_irq=SCORE603E_IRQ16; check_irq<=SCORE603E_IRQ19; check_irq++) {
+       if ( Is_PMC_IRQ( check_irq, status_word )) {
+         bsp_irq_dispatch_list_base(rtems_hdl_tbl, check_irq, dflt_entry.hdl);
+       }
+     }
+   } else
+#endif
+   {
+    bsp_irq_dispatch_list_base(rtems_hdl_tbl, irq, dflt_entry.hdl);
+   }
+
+  return 0;
+}
+
+void
+BSP_enable_irq_at_pic(const rtems_irq_number irq)
+{
+  uint16_t  vec_idx  = irq - Score_IRQ_First;
+  unmask_irq( vec_idx );
+}
+
+int
+BSP_disable_irq_at_pic(const rtems_irq_number irq)
+{
+  uint16_t  vec_idx  = irq - Score_IRQ_First;
+  unmask_irq( vec_idx );
+  return 0;
+}
+
+int
+BSP_setup_the_pic(rtems_irq_global_settings *config)
+{
+  dflt_entry    = config->defaultEntry;
+  rtems_hdl_tbl = config->irqHdlTbl;
+  init_irq_data_register();
+  return 1;
+}