Remove stray white spaces.

4 files changed, 152 insertions, 152 deletions

diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c
index 0c853fabaf..2fc1a2f194 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c
@@ -57,13 +57,13 @@ void bsp_libc_init( void *, uint32_t, int );
 void BSP_panic(char *s)
 {
   printk("%s PANIC %s\n",_RTEMS_version, s);
-  __asm__ __volatile ("sc"); 
+  __asm__ __volatile ("sc");
 }
 
 void _BSP_Fatal_error(unsigned int v)
 {
   printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
-  __asm__ __volatile ("sc"); 
+  __asm__ __volatile ("sc");
 }
 
 /*
@@ -75,7 +75,7 @@ void _BSP_Fatal_error(unsigned int v)
  *  Must not use libc (to do io) from here, since drivers are not yet
  *  initialized.
  *
- *  Installed in the rtems_cpu_table defined in 
+ *  Installed in the rtems_cpu_table defined in
  *  rtems/c/src/exec/score/cpu/m68k/cpu.h in main() below. Called from
  *  rtems_initialize_executive() defined in rtems/c/src/exec/sapi/src/init.c
  *
@@ -87,7 +87,7 @@ void _BSP_Fatal_error(unsigned int v)
  */
 void bsp_pretasking_hook(void)
 {
-  /* 
+  /*
    *  These are assigned addresses in the linkcmds file for the BSP. This
    *  approach is better than having these defined as manifest constants and
    *  compiled into the kernel, but it is still not ideal when dealing with
@@ -101,7 +101,7 @@ void bsp_pretasking_hook(void)
     extern unsigned char _HeapEnd;
 
     bsp_libc_init( &_HeapStart, &_HeapEnd - &_HeapStart, 0 );
-  
+
 #ifdef RTEMS_DEBUG
   rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
 #endif
@@ -135,11 +135,11 @@ void bsp_pretasking_hook(void)
 void bsp_start(void)
 {
   extern void *_WorkspaceBase;
-  
+
   ppc_cpu_id_t myCpu;
   ppc_cpu_revision_t myCpuRevision;
   register unsigned char* intrStack;
-  
+
   /*
    * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
    * store the result in global variables so that it can be used latter...
@@ -148,7 +148,7 @@ void bsp_start(void)
   myCpuRevision = get_ppc_cpu_revision();
 
   mmu_init();
-  
+
   /*
    * Enable instruction and data caches. Do not force writethrough mode.
    */
@@ -168,7 +168,7 @@ void bsp_start(void)
   /*
    * Initialize some SPRG registers related to irq handling
    */
-  
+
   intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE);
   _write_SPRG1((unsigned int)intrStack);
   /* signal them that we have fixed PR288 - eventually, this should go away */
@@ -217,7 +217,7 @@ void bsp_start(void)
   Cpu_table.timer_least_valid = 3;
 #endif
 
-  /* 
+  /*
    * Call this in case we use TERMIOS for console I/O
    */
   m8xx_uart_reserve_resources( &BSP_Configuration );
@@ -232,6 +232,6 @@ void bsp_start(void)
   BSP_rtems_irq_mng_init(0);
 #ifdef SHOW_MORE_INIT_SETTINGS
   printk("Exit from bspstart\n");
-#endif  
+#endif
 
 }
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c
index 676d473051..19d8c59b77 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c
@@ -18,7 +18,7 @@
  *  in the SIU when it takes control, but does not restore it before
  *  returning control to the program. We thus keep a copy of the
  *  register, and restore it from gdb using the hook facilities.
- *  
+ *
  *  We arrange for simask_copy to be initialized to zero so that
  *  it resides in the .data section. This avoids having gdb set
  *  the mask to crud before we get to initialize explicitly. Of
@@ -35,11 +35,11 @@ uint32_t   simask_copy = 0;
  *  number MBXA/PG1. We are assuming that the values in MBXA/PG1
  *  are for the older MBX boards whose part number does not have
  *  the "B" suffix, but we have discovered that the values from
- *  MBXA/PG2 work better, even for the older boards. 
- *  
+ *  MBXA/PG2 work better, even for the older boards.
+ *
  *  THESE VALUES HAVE ONLY BEEN VERIFIED FOR THE MBX821-001 and
  *  MBX860-002. USE WITH CARE!
- *  
+ *
  *  NOTE: The MBXA/PG2 manual lists the clock speed of the MBX821_001B
  *  as being 50 MHz, while the MBXA/IH2.1 manual lists it as 40 MHz.
  *  We think the MBX821_001B is an entry level board and thus is 50 MHz,
@@ -58,7 +58,7 @@ static uint32_t   upmaTable[64] = {
          * initialized by EPPCBug 1.1. In particular, the original
          * burst-write values do not work! Also, the following values
          * facilitate higher performance.
-         */  
+         */
 	/* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */
 	0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04,
 	0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005,
@@ -83,7 +83,7 @@ static uint32_t   upmaTable[64] = {
 	0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
 	0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005,
 	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
- 
+
 	/*  Exception. (offset 0x3c in UPM RAM) */
 	0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007
 
@@ -109,14 +109,14 @@ static uint32_t   upmaTable[64] = {
 
         /* 40 MHz MBX */
         /*
-         * Note: For the older MBX models (i.e. without the "b" 
+         * Note: For the older MBX models (i.e. without the "b"
          * suffix, e.g. mbx860_001), the following values (from the
          * MBXA/PG2 manual) work better than, but are different
          * from those published in the original MBXA/PG1 manual and
          * initialized by EPPCBug 1.1. In particular, the following
          * burst-read and burst-write values facilitate higher
          * performance.
-         */  
+         */
 	/* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */
 	0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00,
 	0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
@@ -141,7 +141,7 @@ static uint32_t   upmaTable[64] = {
 	0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
 	0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
 	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
- 
+
 	/*  Exception. (offset 0x3c in UPM RAM) */
 	0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007
 #else
@@ -157,14 +157,14 @@ void _InitMBX8xx (void)
   register uint32_t   r1, i;
   extern uint32_t   simask_copy;
 
-  /*			
+  /*
    *  Initialize the Debug Enable Register (DER) to an appropriate
-   *  value for EPPCBug debugging. 
+   *  value for EPPCBug debugging.
    *  (This value should also work for BDM debugging.)
    */
   r1 = 0x70C67C07;	/* All except EXTIE, ALIE, DECIE */
   _mtspr( M8xx_DER, r1 );
-  
+
   /*
    * Initialize the Instruction Support Control Register (ICTRL) to a
    * an appropriate value for normal operation. A different value,
@@ -172,7 +172,7 @@ void _InitMBX8xx (void)
    */
   r1 = 0x00000007;
   _mtspr( M8xx_ICTRL, r1 );
-	
+
   /*
    * Disable and invalidate the instruction and data caches.
    */
@@ -185,7 +185,7 @@ void _InitMBX8xx (void)
   r1 = M8xx_CACHE_CMD_INVALIDATE;	/* invalidate all */
   _mtspr( M8xx_IC_CST, r1 );
   _isync;
-  
+
   r1 = M8xx_CACHE_CMD_DISABLE;
   _mtspr( M8xx_DC_CST, r1 );
   _isync;
@@ -214,14 +214,14 @@ void _InitMBX8xx (void)
    *  imd: accessing m8xx.* should not occure before setting up the immr !
    */
    simask_copy = m8xx.simask;
-  
-  /* 
-   * Initialize the SIU Module Configuration Register (SIUMCR) 
+
+  /*
+   * Initialize the SIU Module Configuration Register (SIUMCR)
    * m8xx.siumcr = 0x00602900, the default MBX and firmware value.
    */
-  m8xx.siumcr = M8xx_SIUMCR_EARP0 | M8xx_SIUMCR_DBGC3 | M8xx_SIUMCR_DBPC0 | 
+  m8xx.siumcr = M8xx_SIUMCR_EARP0 | M8xx_SIUMCR_DBGC3 | M8xx_SIUMCR_DBPC0 |
 		M8xx_SIUMCR_DPC | M8xx_SIUMCR_MLRC2 | M8xx_SIUMCR_SEME;
-  
+
   /*
    * Initialize the System Protection Control Register (SYPCR).
    * The SYPCR can only be written once after Reset.
@@ -229,39 +229,39 @@ void _InitMBX8xx (void)
    *	- Disable software watchdog timer
    * m8xx.sypcr = 0xFFFFFF88, the default MBX and firmware value.
    */
-  m8xx.sypcr = M8xx_SYPCR_SWTC(0xFFFF) | M8xx_SYPCR_BMT(0xFF) | 
+  m8xx.sypcr = M8xx_SYPCR_SWTC(0xFFFF) | M8xx_SYPCR_BMT(0xFF) |
 		M8xx_SYPCR_BME | M8xx_SYPCR_SWF;
 
   /* Initialize the SIU Interrupt Edge Level Mask Register (SIEL) */
   m8xx.siel = 0xAAAA0000;         	/* Default MBX and firmware value. */
-  
+
   /* Initialize the Transfer Error Status Register (TESR) */
   m8xx.tesr = 0xFFFFFFFF;         	/* Default firmware value. */
-  
+
   /* Initialize the SDMA Configuration Register (SDCR) */
   m8xx.sdcr = 0x00000001;         	/* Default firmware value. */
-  
+
   /*
    * Initialize the Timebase Status and Control Register (TBSCR)
    * m8xx.tbscr = 0x00C3, default MBX and firmware value.
    */
   m8xx.tbscrk = M8xx_UNLOCK_KEY;	/* unlock TBSCR */
-  m8xx.tbscr = M8xx_TBSCR_REFA | M8xx_TBSCR_REFB | 
+  m8xx.tbscr = M8xx_TBSCR_REFA | M8xx_TBSCR_REFB |
   		M8xx_TBSCR_TBF | M8xx_TBSCR_TBE;
-  
+
   /* Initialize the Real-Time Clock Status and Control Register (RTCSC) */
   m8xx.rtcsk = M8xx_UNLOCK_KEY;		/* unlock RTCSC */
   m8xx.rtcsc = 0x00C3;			/* Default MBX and firmware value. */
-  
+
   /* Unlock other Real-Time Clock registers */
   m8xx.rtck = M8xx_UNLOCK_KEY;		/* unlock RTC */
   m8xx.rtseck = M8xx_UNLOCK_KEY;	/* unlock RTSEC */
   m8xx.rtcalk = M8xx_UNLOCK_KEY;	/* unlock RTCAL */
-  
+
   /* Initialize the Periodic Interrupt Status and Control Register (PISCR) */
   m8xx.piscrk = M8xx_UNLOCK_KEY;	/* unlock PISCR */
   m8xx.piscr = 0x0083; 			/* Default MBX and firmware value. */
-      
+
   /* Initialize the System Clock and Reset Control Register (SCCR)
    * Set the clock sources and division factors:
    *   Timebase Source is GCLK2 / 16
@@ -299,18 +299,18 @@ void _InitMBX8xx (void)
         defined(mbx821_005))
   m8xx.plprcr = 0x4C400000;
 #else
-#error "MBX board not defined"  
+#error "MBX board not defined"
 #endif
   /* Unlock the timebase and decrementer registers. */
   m8xx.tbk = M8xx_UNLOCK_KEY;
-  /* 
+  /*
    * Initialize decrementer register to a large value to
    * guarantee that a decrementer interrupt will not be
    * generated before the kernel is fully initialized.
    */
   r1 = 0x7FFFFFFF;
   _mtspr( M8xx_DEC, r1 );
-	
+
   /* Initialize the timebase register (TB is 64 bits) */
   r1 = 0x00000000;
   _mtspr( M8xx_TBU_WR, r1 );
@@ -322,24 +322,24 @@ void _InitMBX8xx (void)
 
   /*
    * User Programmable Machine A (UPMA) Initialization
-   * 
+   *
    * If this initialization code is running from DRAM, it is very
    * dangerous to change the value of any UPMA Ram array word from
    * what the firmware (EPPCBug) initialized it to. Thus we don't
    * initialize UPMA if EPPCBUG_VECTORS is defined; we assume EPPCBug
    * has done the appropriate initialization.
-   * 
+   *
    * An exception to our rule, is that, for the older MBX boards
    * (those without the "B" suffix, e.g. MBX821-001 and MBX860-002),
    * we do re-initialize the burst-read and burst-write values with
    * values that are more efficient. Also, in the MBX821 case,
-   * the burst-write original values set by EPPCBug do not work! 
+   * the burst-write original values set by EPPCBug do not work!
    * This change can be done safely because the caches have not yet
    * been activated.
    *
    * The RAM array of UPMA is initialized by writing to each of
    * its 64 32-bit RAM locations.
-   * Note: UPM register initialization should occur before 
+   * Note: UPM register initialization should occur before
    * initialization of the corresponding BRx and ORx registers.
    */
 #if ( !defined(EPPCBUG_VECTORS) )
@@ -373,27 +373,27 @@ void _InitMBX8xx (void)
 #if ( !defined(EPPCBUG_VECTORS) )
   /*
    *  Initialize the memory periodic timer.
-   *	Memory Periodic Timer Prescaler Register (MPTPR: 16-bit register) 
+   *	Memory Periodic Timer Prescaler Register (MPTPR: 16-bit register)
    *  m8xx.mptpr = 0x0200;
    */
   m8xx.mptpr = M8xx_MPTPR_PTP(0x2);
-  
+
   /*
    *  Initialize the Machine A Mode Register (MAMR)
-   * 
+   *
    *  ASSUMES THAT DIMMs ARE NOT INSTALLED!
-   *  
+   *
    *  Without DIMMs:
    *  m8xx.mamr = 0x13821000 (40 MHz) or 0x18821000 (50 MHz).
-   *  
+   *
    *  With DIMMs:
    *  m8xx.mamr = 0x06821000 (40 MHz) or 0x08821000 (50 MHz).
    */
 #if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) )
-  m8xx.mamr = M8xx_MEMC_MMR_PTP(0x18) | M8xx_MEMC_MMR_PTE | 
+  m8xx.mamr = M8xx_MEMC_MMR_PTP(0x18) | M8xx_MEMC_MMR_PTE |
 	M8xx_MEMC_MMR_DSP(0x1) | M8xx_MEMC_MMR_G0CL(0) | M8xx_MEMC_MMR_UPWAIT;
 #else
-  m8xx.mamr = M8xx_MEMC_MMR_PTP(0x13) | M8xx_MEMC_MMR_PTE | 
+  m8xx.mamr = M8xx_MEMC_MMR_PTP(0x13) | M8xx_MEMC_MMR_PTE |
 	M8xx_MEMC_MMR_DSP(0x1) | M8xx_MEMC_MMR_G0CL(0) | M8xx_MEMC_MMR_UPWAIT;
 #endif
 #endif /* ! defined(EPPCBUG_VECTORS) */
@@ -416,31 +416,31 @@ void _InitMBX8xx (void)
    *	FC000000  FC7FFFFF  7    8  N   N   GPCM  Y   Y  Socketed FLASH Memory
    *
    *  z = 3 for 4MB installed on the motherboard, z = F for 16M
-   *  
+   *
    *  NOTE: The devices selected by CS0 and CS7 can be selected with jumper J4.
    *  This table assumes that the 32-bit soldered flash device is the boot ROM.
    */
 
   /*
    *  CS0 : Soldered (32-bit) Flash Memory at 0xFE000000
-   *  
+   *
    *  CHANGE THIS CODE IF YOU CHANGE JUMPER J4 FROM ITS FACTORY DEFAULT SETTING!
    *  (or better yet, don't reprogram BR0 and OR0; just program BR7 and OR7 to
    *  access whatever flash device is not selected during hard reset.)
-   * 
+   *
    *  MBXA/PG2 appears to lie in note 14 for table 2-4. The manual states that
    *  "EPPCBUG configures the reset flash device at the lower address, and the
    *  nonreset flash device at the higher address." If we take reset flash device
    *  to mean the boot flash memory, then the statement must mean that BR0 must
    *  point to the device at the lower address, i.e. 0xFC000000, while BR7 must
    *  point to the device at the highest address, i.e. 0xFE000000.
-   *  
+   *
    *  THIS IS NOT THE CASE!
-   *  
+   *
    *  The boot flash is always configured to start at 0xFE000000, and the other
    *  one to start at 0xFC000000. Changing jumper J4 only changes the width of
    *  the memory ports into these two region.
-   *  
+   *
    * BR0 = 0xFE000001
    *	Base addr [0-16]	0b11111110000000000 = 0xFE000000
    *	Address type [17-19]	0b000
@@ -464,7 +464,7 @@ void _InitMBX8xx (void)
    *
    * m8xx.memc[0]._or = 0xFF800930 (40 MHz)
    * m8xx.memc[0]._or = 0xFF800940 (50 MHz)
-   * m8xx.memc[0]._br = 0xFE000001 
+   * m8xx.memc[0]._br = 0xFE000001
    */
 #if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) )
   m8xx.memc[0]._or = M8xx_MEMC_OR_8M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT |
@@ -476,13 +476,13 @@ void _InitMBX8xx (void)
   m8xx.memc[0]._br = M8xx_BR_BA(0xFE000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 |
 		M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V;
 
-  /* 
+  /*
    * CS1 : Local DRAM Memory at 0x00000000
    * m8xx.memc[1]._or = 0xFFC00400;
    * m8xx.memc[1]._br = 0x00000081;
    */
 #if ( defined(mbx860_001b) )
-    m8xx.memc[1]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) | 
+    m8xx.memc[1]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) |
     M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0);
 #elif ( defined(mbx860_002b) || \
          defined(mbx860_003b) || \
@@ -495,7 +495,7 @@ void _InitMBX8xx (void)
          defined(mbx821_001)  || \
          defined(mbx821_002)  || \
          defined(mbx821_003) )
-    m8xx.memc[1]._or = M8xx_MEMC_OR_4M | M8xx_MEMC_OR_ATM(0) | 
+    m8xx.memc[1]._or = M8xx_MEMC_OR_4M | M8xx_MEMC_OR_ATM(0) |
     M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0);
 #elif ( defined(mbx860_004) || \
         defined(mbx860_005) || \
@@ -507,7 +507,7 @@ void _InitMBX8xx (void)
         defined(mbx821_004b) || \
         defined(mbx821_005b) || \
         defined(mbx821_006b) )
-    m8xx.memc[1]._or = M8xx_MEMC_OR_16M | M8xx_MEMC_OR_ATM(0) | 
+    m8xx.memc[1]._or = M8xx_MEMC_OR_16M | M8xx_MEMC_OR_ATM(0) |
       M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0);
 #else
 #error "MBX board not defined"
@@ -515,28 +515,28 @@ void _InitMBX8xx (void)
   m8xx.memc[1]._br = M8xx_BR_BA(0x00000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 |
 		M8xx_BR_MS_UPMA | M8xx_MEMC_BR_V;
 
-  /* 
-   * CS2 : DIMM Memory - Bank #0, not present 
+  /*
+   * CS2 : DIMM Memory - Bank #0, not present
    * m8xx.memc[2]._or = 0x00000400;
    * m8xx.memc[2]._br = 0x00000080;
    */
-  m8xx.memc[2]._or = M8xx_MEMC_OR_ATM(0) | 
+  m8xx.memc[2]._or = M8xx_MEMC_OR_ATM(0) |
 		M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0);
   m8xx.memc[2]._br = M8xx_BR_AT(0) | M8xx_BR_PS32 |
 		M8xx_BR_MS_UPMA;	/* ! M8xx_MEMC_BR_V */
 
-  /* 
-   * CS3 : DIMM Memory - Bank #1, not present 
+  /*
+   * CS3 : DIMM Memory - Bank #1, not present
    * m8xx.memc[3]._or = 0x00000400;
    * m8xx.memc[3]._br = 0x00000080;
    */
-  m8xx.memc[3]._or = M8xx_MEMC_OR_ATM(0) | 
+  m8xx.memc[3]._or = M8xx_MEMC_OR_ATM(0) |
 		M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0);
   m8xx.memc[3]._br = M8xx_BR_AT(0) | M8xx_BR_PS32 |
 		M8xx_BR_MS_UPMA;	/* ! M8xx_MEMC_BR_V */
 
   /*
-   * CS4 : Battery-Backed SRAM at 0xFA000000 
+   * CS4 : Battery-Backed SRAM at 0xFA000000
    * m8xx.memc[4]._or = 0xFFE00920@ 40 MHz, 0xFFE00930 @ 50 MHz
    * m8xx.memc[4]._br = 0xFA000401;
    */
@@ -551,7 +551,7 @@ void _InitMBX8xx (void)
 		M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V;
 
   /*
-   * CS5 : PCI I/O and Memory at 0x80000000 
+   * CS5 : PCI I/O and Memory at 0x80000000
    * m8xx.memc[5]._or = 0xA0000108;
    * m8xx.memc[5]._br = 0x80000001;
    */
@@ -560,8 +560,8 @@ void _InitMBX8xx (void)
   m8xx.memc[5]._br = M8xx_BR_BA(0x80000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 |
 		M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V;
 
-  /* 
-   * CS6 : QSPAN Registers at 0xFA210000 
+  /*
+   * CS6 : QSPAN Registers at 0xFA210000
    * m8xx.memc[6]._or = 0xFFFF0108;
    * m8xx.memc[6]._br = 0xFA210001;
    */
@@ -570,8 +570,8 @@ void _InitMBX8xx (void)
   m8xx.memc[6]._br = M8xx_BR_BA(0xFA210000) | M8xx_BR_AT(0) | M8xx_BR_PS32 |
 		M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V;
 
-  /* 
-   * CS7 : Socketed (8-bit) Flash at 0xFC000000 
+  /*
+   * CS7 : Socketed (8-bit) Flash at 0xFC000000
    * m8xx.memc[7]._or = 0xFF800930 @ 40 MHz, 0xFF800940 @ 50 MHz
    * m8xx.memc[7]._br = 0xFC000401;
    */
@@ -591,36 +591,36 @@ void _InitMBX8xx (void)
    * PCMCIA region 0: common memory
    */
   m8xx.pbr0 = PCMCIA_MEM_ADDR;
-  m8xx.por0 = (M8xx_PCMCIA_POR_BSIZE_64MB 
-	       | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) 
-	       | M8xx_PCMCIA_POR_PSL(32)  
-	       | M8xx_PCMCIA_POR_PPS_16   | M8xx_PCMCIA_POR_PRS_MEM 
+  m8xx.por0 = (M8xx_PCMCIA_POR_BSIZE_64MB
+	       | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15)
+	       | M8xx_PCMCIA_POR_PSL(32)
+	       | M8xx_PCMCIA_POR_PPS_16   | M8xx_PCMCIA_POR_PRS_MEM
 	       |M8xx_PCMCIA_POR_PSLOT_A   |  M8xx_PCMCIA_POR_VALID);
   /*
    * PCMCIA region 1: dma memory
    */
   m8xx.pbr1 = PCMCIA_DMA_ADDR;
-  m8xx.por1 = (M8xx_PCMCIA_POR_BSIZE_64MB 
-	       | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) 
-	       | M8xx_PCMCIA_POR_PSL(32)  
-	       | M8xx_PCMCIA_POR_PPS_16   | M8xx_PCMCIA_POR_PRS_DMA 
+  m8xx.por1 = (M8xx_PCMCIA_POR_BSIZE_64MB
+	       | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15)
+	       | M8xx_PCMCIA_POR_PSL(32)
+	       | M8xx_PCMCIA_POR_PPS_16   | M8xx_PCMCIA_POR_PRS_DMA
 	       |M8xx_PCMCIA_POR_PSLOT_A   |  M8xx_PCMCIA_POR_VALID);
   /*
    * PCMCIA region 2: attribute memory
    */
   m8xx.pbr2 = PCMCIA_ATTRB_ADDR;
-  m8xx.por2 = (M8xx_PCMCIA_POR_BSIZE_64MB 
-	       | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) 
-	       | M8xx_PCMCIA_POR_PSL(32)  
+  m8xx.por2 = (M8xx_PCMCIA_POR_BSIZE_64MB
+	       | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15)
+	       | M8xx_PCMCIA_POR_PSL(32)
 	       | M8xx_PCMCIA_POR_PPS_16   | M8xx_PCMCIA_POR_PRS_ATT
 	       |M8xx_PCMCIA_POR_PSLOT_A   |  M8xx_PCMCIA_POR_VALID);
   /*
    * PCMCIA region 3: I/O access
    */
   m8xx.pbr3 = PCMCIA_IO_ADDR;
-  m8xx.por3 = (M8xx_PCMCIA_POR_BSIZE_64MB 
-	       | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) 
-	       | M8xx_PCMCIA_POR_PSL(32)  
+  m8xx.por3 = (M8xx_PCMCIA_POR_BSIZE_64MB
+	       | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15)
+	       | M8xx_PCMCIA_POR_PSL(32)
 	       | M8xx_PCMCIA_POR_PPS_16   | M8xx_PCMCIA_POR_PRS_IO
 	       |M8xx_PCMCIA_POR_PSLOT_A   |  M8xx_PCMCIA_POR_VALID);
 
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c
index a252f7d1ac..47b34f3e12 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c
@@ -1,7 +1,7 @@
-/* 
+/*
  * mmutlbtab.c
- * 
- * This file defines the  MMU_TLB_table for the MBX8xx. 
+ *
+ * This file defines the  MMU_TLB_table for the MBX8xx.
  *
  * Copyright (c) 1999, National Research Council of Canada
  *
@@ -27,14 +27,14 @@
  * The instruction and data TLBs each can hold 32 entries, so _TLB_Table must
  * not have more than 32 lines in it!
  *
- * We set up the virtual memory map so that virtual address of a 
+ * We set up the virtual memory map so that virtual address of a
  * location is equal to its real address.
  */
 MMU_TLB_table_t MMU_TLB_table[] = {
 #if ( defined(mbx860_001b) )
   /*
-	 * DRAM: CS1, Start address 0x00000000, 2M, 
-	 *	ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, 
+	 * DRAM: CS1, Start address 0x00000000, 2M,
+	 *	ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy,
 	 *	R/W,X for all, no ASID comparison, not cache-inhibited.
 	 *	Last 512K block is cache-inhibited, but not guarded for use by EPPCBug.
 	 * EPN		TWC	RPN
@@ -55,8 +55,8 @@ MMU_TLB_table_t MMU_TLB_table[] = {
          defined(mbx821_002)  || \
          defined(mbx821_003) )
   /*
-	 * DRAM: CS1, Start address 0x00000000, 4M, 
-	 *	ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, 
+	 * DRAM: CS1, Start address 0x00000000, 4M,
+	 *	ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy,
 	 *	R/W,X for all, no ASID comparison, not cache-inhibited.
 	 *	Last 512K block is cache-inhibited, but not guarded for use by EPPCBug.
 	 * EPN		TWC	RPN
@@ -78,10 +78,10 @@ MMU_TLB_table_t MMU_TLB_table[] = {
         defined(mbx821_005) || \
         defined(mbx821_004b) || \
         defined(mbx821_005b) || \
-        defined(mbx821_006b) ) 
+        defined(mbx821_006b) )
   /*
-	 * DRAM: CS1, Start address 0x00000000, 16M, 
-	 *	ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, 
+	 * DRAM: CS1, Start address 0x00000000, 16M,
+	 *	ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy,
 	 *	R/W,X for all, no ASID comparison, not cache-inhibited.
 	 * EPN		TWC	RPN
 	 */
@@ -93,9 +93,9 @@ MMU_TLB_table_t MMU_TLB_table[] = {
 	/*
 	 *
 	 * NVRAM: CS4, Start address 0xFA000000, 32K,
-	 *	ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, 
+	 *	ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy,
 	 *	R/W,X for all, no ASID comparison, cache-inhibited.
-	 * 
+	 *
 	 * EPN		TWC	RPN
 	 */
 	{ 0xFA000200,	0x01,	0xFA0009FF },	/* NVRAM - PS=16K */
@@ -103,7 +103,7 @@ MMU_TLB_table_t MMU_TLB_table[] = {
 	/*
 	 *
 	 * Board Control/Status Register #1/#2: CS4, Start address 0xFA100000, (4 x 8 bits?)
-	 *	ASID=0x0, APG=0x0, guarded memory, write-through data cache policy, 
+	 *	ASID=0x0, APG=0x0, guarded memory, write-through data cache policy,
 	 *	R/W,X for all, no ASID comparison, cache-inhibited.
 	 * EPN		TWC	RPN
 	 */
@@ -111,10 +111,10 @@ MMU_TLB_table_t MMU_TLB_table[] = {
 	/*
 	 *
 	 * (IMMR-SPRs) Dual Port RAM: Start address 0xFA200000, 16K,
-	 *	ASID=0x0, APG=0x0, guarded memory, write-through data cache policy, 
+	 *	ASID=0x0, APG=0x0, guarded memory, write-through data cache policy,
 	 *	R/W,X for all, no ASID comparison, cache-inhibited.
-	 *	
-	 *	Note: We use the value in MBXA/PG2, which is also the value that 
+	 *
+	 *	Note: We use the value in MBXA/PG2, which is also the value that
 	 *	EPPC-Bug programmed into our boards. The alternative is the value
 	 * 	in MBXA/PG1: 0xFFA00000. This value might well depend on the revision
 	 *	of the firmware.
@@ -124,7 +124,7 @@ MMU_TLB_table_t MMU_TLB_table[] = {
 	/*
 	 *
 	 * Flash: CS0, Start address 0xFE000000, 4M, (BootROM-EPPCBug)
-	 *	ASID=0x0, APG=0x0, not guarded memory, 
+	 *	ASID=0x0, APG=0x0, not guarded memory,
 	 *	R/O,X for all, no ASID comparison, not cache-inhibited.
 	 * EPN		TWC	RPN
 	 */
@@ -138,7 +138,7 @@ MMU_TLB_table_t MMU_TLB_table[] = {
 	{ 0xFE380200,	0x05,	0xFE380CFD },	/* Flash - PS=512K */
 	/*
 	 * BootROM: CS7, Start address 0xFC000000, 4M?, (socketed FLASH)
-	 *	ASID=0x0, APG=0x0, not guarded memory, 
+	 *	ASID=0x0, APG=0x0, not guarded memory,
 	 *	R/O,X for all, no ASID comparison, not cache-inhibited.
 	 * EPN		TWC	RPN
 	 */
@@ -173,23 +173,23 @@ MMU_TLB_table_t MMU_TLB_table[] = {
 	 * For each space (MEM/DMA/ATTRIB/IO) only the first 8MB are mapped
 	 *	ASID=0x0, APG=0x0, guarded memory,
 	 *	R/W,X for all, no ASID comparison, cache-inhibited.
-	 * EPN		                           TWC	
+	 * EPN		                           TWC
 	 * RPN
 	 */
-	{ (PCMCIA_MEM_ADDR & 0xfffff000) | 0x200, 0x1D,	
+	{ (PCMCIA_MEM_ADDR & 0xfffff000) | 0x200, 0x1D,
 	  (PCMCIA_MEM_ADDR & 0xfffff000) | 0x9F7 },/* PCMCIA Memory - PS=8M */
 
-	{ (PCMCIA_DMA_ADDR & 0xfffff000) | 0x200, 0x1D,	
+	{ (PCMCIA_DMA_ADDR & 0xfffff000) | 0x200, 0x1D,
 	  (PCMCIA_DMA_ADDR & 0xfffff000) | 0x9F7 },/* PCMCIA DMA - PS=8M */
 
-	{ (PCMCIA_ATTRB_ADDR & 0xfffff000) | 0x200, 0x1D,	
+	{ (PCMCIA_ATTRB_ADDR & 0xfffff000) | 0x200, 0x1D,
 	  (PCMCIA_ATTRB_ADDR & 0xfffff000) | 0x9F7 },/* PCMCIA ATTRIB-PS=8M*/
 
-	{ (PCMCIA_IO_ADDR & 0xfffff000) | 0x200, 0x1D,	
+	{ (PCMCIA_IO_ADDR & 0xfffff000) | 0x200, 0x1D,
 	  (PCMCIA_IO_ADDR & 0xfffff000) | 0x9F7 }     /* PCMCIA I/O - PS=8M */
 };
 
-/* 
+/*
  * MMU_N_TLB_Table_Entries is defined here because the size of the
  * MMU_TLB_table is only known in this file.
  */
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S b/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S
index ebd60be5ab..ed44cfd41c 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S
@@ -6,28 +6,28 @@
  *  all remaining initialization.
  *
  * This file is based on several others:
- * 
- * (1) start360.s from the gen68360 BSP by 
+ *
+ * (1) start360.s from the gen68360 BSP by
  *     W. Eric Norum (eric@skatter.usask.ca)
  *     with the following copyright and license:
  *
  *     COPYRIGHT (c) 1989-1998.
  *     On-Line Applications Research Corporation (OAR).
- *     
+ *
  *     The license and distribution terms for this file may in
  *     the file LICENSE in this distribution or at
  *     http://www.rtems.com/license/LICENSE.
  *
  * (2) start.s for the eth_comm port by
  *     Jay Monkman (jmonkman@fracsa.com),
- *     which itself is based on the 
- * 
+ *     which itself is based on the
+ *
  * (3) dlentry.s for the Papyrus BSP, written by:
  *     Andrew Bray <andy@i-cubed.co.uk>
  *     with the following copyright and license:
  *
  *     COPYRIGHT (c) 1995 by i-cubed ltd.
- *     
+ *
  * (4) start860.S for the MBX821/MBX860, written by:
  *     Darlene A. Stewart <darlene.stewart@iit.nrc.ca>
  *     Copyright (c) 1999, National Research Council of Canada
@@ -179,7 +179,7 @@
 .L_D4_e:
 .L_D2:
 	.previous
-	
+
 /*
  * Tell C's eabi-ctor's that we have an atexit function,
  * and that it is to register __do_global_dtors.
@@ -188,7 +188,7 @@
 	PUBLIC_VAR(__atexit)
 	.section ".sdata","aw"
 	.align	2
-SYM(__atexit):			
+SYM(__atexit):
 	EXT_PROC_REF(atexit)@fixup
 	.previous
 
@@ -198,7 +198,7 @@ SYM(__atexit):
 	.previous
 
 /* That should do it */
-			
+
 /*
  *  Put the entry point in its own section. That way, we can guarantee
  *  to put it first in the .text section in the linker script.
@@ -208,16 +208,16 @@ SYM(__atexit):
         PUBLIC_VAR (start)
 SYM(start):
         bl      .startup	/* or bl .spin */
-base_addr:      
+base_addr:
 
 /*
  * Parameters from linker
  */
-toc_pointer:    
+toc_pointer:
         .long   __GOT_START__
-bss_length:     
+bss_length:
         .long   bss.size
-bss_addr:       
+bss_addr:
         .long   bss.start
 
 PUBLIC_VAR (text_addr)
@@ -230,7 +230,7 @@ text_length:
 
 /*
  * Spin, if necessary, to acquire control from debugger (CodeWarrior).
- */     
+ */
 spin:
 	.long	0x0001
 .spin:
@@ -238,22 +238,22 @@ spin:
 	lwz	r3, spin@l(r3)
 	cmpwi	r3, 0x1
 	beq	.spin
-/*	
+/*
  * #define LOADED_BY_EPPCBUG
  */
 #define LOADED_BY_EPPCBUG
-#define EARLY_CONSOLE		
+#define EARLY_CONSOLE
 /*
- * Initialization code 
+ * Initialization code
  */
-.startup:	
+.startup:
         /* Get the start address. */
         mflr    r1
-#ifdef LOADED_BY_EPPCBUG	
+#ifdef LOADED_BY_EPPCBUG
 	/* Save pointer to residual/board data */
 	lis	r9,eppcbugInfo@ha
 	stw	r3,eppcbugInfo@l(r9)
-#endif	
+#endif
         /* Initialize essential registers. */
         bl      initregs
         nop
@@ -272,24 +272,24 @@ spin:
         EXTERN_PROC (_InitMBX8xx)
         bl	PROC (_InitMBX8xx)
         nop
-        
+
         /* Clear the bss section. */
         bl      bssclr
         nop
 #if defined(EARLY_CONSOLE) && defined(LOADED_BY_EPPCBUG)
 	EXTERN_PROC (serial_init)
 	bl	PROC (serial_init)
-#endif	
+#endif
 	lis	r5,environ@ha
         la	r5,environ@l(r5)		/* environp */
         /* clear argc and argv */
         xor     r3, r3, r3
         xor     r4, r4, r4
-        
+
         EXTERN_PROC (boot_card)
         bl       PROC (boot_card)	/* call the first C routine */
         nop
-        
+
         /* we should never return from boot_card, but in case we do ... */
 	/* The next instructions are dependent on your runtime environment */
 
@@ -297,14 +297,14 @@ spin:
 	lis  	r10, 0x0400		/* Data cache disable */
 	mtspr 	568, r10
 	isync
-		
+
 	mtspr   560, r10		/* Instruction cache disable */
 	isync
-		
+
 stop_here:
 	li	r10, 0x0F00		/* .RETURN */
 	sc
-	
+
 	b	stop_here
         nop
 
@@ -320,13 +320,13 @@ bssclr:
         rlwinm. r5,r5,30,0x3FFFFFFF             /* form length/4 */
         beqlr                                   /* no bss - return */
         mtctr   r5                              /* set ctr reg */
-        
+
         li      r5,0x0000                       /* r5 = 0 */
 clear_bss:
         stw     r5,0(r4)                        /* store r6 */
         addi    r4,r4,0x4                       /* update r4 */
         bdnz    clear_bss                       /* dec counter and loop */
-        
+
         blr                                     /* return */
 
 /*
@@ -337,24 +337,24 @@ clear_bss:
  *	r0 - scratch
  */
 initregs:
-	/*        
+	/*
 	 * Disable address translation. We should already be running in real space,
 	 * so this should be a no-op, i.e. no need to switch instruction stream
 	 * addresses from virtual space to real space. Other bits set the processor
 	 * for big-endian mode, exceptions vectored to 0x000n_nnnn (vectors are
 	 * already in low memory!), no execution tracing, machine check exceptions
-	 * enabled, floating-point not available (MPC8xx has none), supervisor 
+	 * enabled, floating-point not available (MPC8xx has none), supervisor
 	 * priviledge level, external interrupts disabled, power management
 	 * disabled (normal operation mode).
 	 */
 	li	r0, 0x1000	/* MSR_ME */
 	mtmsr	r0		/* Context-synchronizing */
 	isync
-	
+
 	/*
 	 * Clear the exception handling registers.
 	 * Note SPRG3 is reserved for use by EPPCBug on the MBX8xx.
-	 */	
+	 */
 	li	r0, 0x0000
 	mtdar   r0
 	mtspr	sprg0, r0
@@ -362,13 +362,13 @@ initregs:
 	mtspr	sprg2, r0
 	mtspr	srr0, r0
 	mtspr	srr1, r0
-			
+
 	mr	r6, r0
 	mr	r7, r0
 	mr	r8, r0
 	mr	r9, r0
 	mr	r10, r0
-	mr	r11, r0 
+	mr	r11, r0
 	mr	r12, r0
 	mr	r13, r0
 	mr	r14, r0
@@ -389,9 +389,9 @@ initregs:
 	mr	r29, r0
 	mr	r30, r0
 	mr	r31, r0
-	
+
 	blr			/* return */
-	
+
 .L_text_e:
 
 	.comm	environ,4,4