diff options
author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-04-06 15:52:03 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-04-06 15:52:03 +0000 |
commit | 35bb69b1cd7d5a54f5727195cc7b5f06a7cb2344 (patch) | |
tree | d7435f5a462d5e266b113b29ee4ad4ed9e21f4af /c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c | |
parent | 2001-03-26 Zoltan Kocsi <zoltan@bendor.com.au> (diff) | |
download | rtems-35bb69b1cd7d5a54f5727195cc7b5f06a7cb2344.tar.bz2 |
2001-03-30 Eric Valette <valette@crf.canon.fr>
* clock/.cvsignore, clock/Makefile.am, clock/p_clock.c,
include/8xx_immap.h, include/commproc.h, include/mbx.h,
irq/.cvsignore, irq/Makefile.am, irq/irq.c, irq/irq.h,
irq/irq_asm.S, irq/irq_init.c, vectors/.cvsignore,
vectors/Makefile.am, vectors/vectors.S, vectors/vectors.h,
vectors/vectors_init.c: New files.
* Makefile.am, configure.in, console/console.c,
include/Makefile.am, network/network.c, startup/Makefile.am,
startup/bspstart.c, startup/imbx8xx.c, startup/linkcmds,
startup/mmutlbtab.c, startup/start.S, wrapup/Makefile.am:
The modifications to this BSP reflect the conversion of the
mpc8xx CPU to the "new exception processing model."
Diffstat (limited to 'c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c')
-rw-r--r-- | c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c | 48 |
1 files changed, 47 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c index 7e6a7ae9cf..bf874f70b6 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c @@ -32,6 +32,7 @@ * the .bss section (RAM). */ extern rtems_configuration_table Configuration; +extern unsigned long intrStackPtr; rtems_configuration_table BSP_Configuration; rtems_cpu_table Cpu_table; @@ -46,6 +47,18 @@ char *rtems_progname; void bsp_postdriver_hook(void); void bsp_libc_init( void *, unsigned32, int ); +void BSP_panic(char *s) +{ + printk("%s PANIC %s\n",_RTEMS_version, s); + __asm__ __volatile ("sc"); +} + +void _BSP_Fatal_error(unsigned int v) +{ + printk("%s PANIC ERROR %x\n",_RTEMS_version, v); + __asm__ __volatile ("sc"); +} + /* * bsp_pretasking_hook * @@ -116,6 +129,18 @@ void bsp_start(void) { extern void *_WorkspaceBase; + ppc_cpu_id_t myCpu; + ppc_cpu_revision_t myCpuRevision; + register unsigned char* intrStack; + register unsigned int intrNestingLevel = 0; + + /* + * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function + * store the result in global variables so that it can be used latter... + */ + myCpu = get_ppc_cpu_type(); + myCpuRevision = get_ppc_cpu_revision(); + mmu_init(); /* @@ -134,7 +159,20 @@ void bsp_start(void) rtems_cache_enable_data(); #endif #endif - + /* + * Initialize some SPRG registers related to irq handling + */ + + intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE); + asm volatile ("mtspr 273, %0" : "=r" (intrStack) : "0" (intrStack)); + asm volatile ("mtspr 272, %0" : "=r" (intrNestingLevel) : "0" (intrNestingLevel)); + + /* + * Install our own set of exception vectors + */ + initialize_exceptions(); + + /* * Allocate the memory for the RTEMS Work Space. This can come from * a variety of places: hard coded address, malloc'ed from outside @@ -181,5 +219,13 @@ void bsp_start(void) m8xx.scc2p.rbase=0; m8xx.scc2p.tbase=0; m8xx_cp_execute_cmd( M8xx_CR_OP_STOP_TX | M8xx_CR_CHAN_SCC2 ); + /* + * Initalize RTEMS IRQ system + */ + BSP_rtems_irq_mng_init(0); +#ifdef SHOW_MORE_INIT_SETTINGS + printk("Exit from bspstart\n"); +#endif + } |