2001-03-30 Eric Valette <valette@crf.canon.fr>

	* clock/.cvsignore, clock/Makefile.am, clock/p_clock.c,
	include/8xx_immap.h, include/commproc.h, include/mbx.h,
	irq/.cvsignore, irq/Makefile.am, irq/irq.c, irq/irq.h,
	irq/irq_asm.S, irq/irq_init.c, vectors/.cvsignore,
	vectors/Makefile.am, vectors/vectors.S, vectors/vectors.h,
	vectors/vectors_init.c: New files.
	* Makefile.am, configure.in, console/console.c,
	include/Makefile.am, network/network.c, startup/Makefile.am,
	startup/bspstart.c, startup/imbx8xx.c, startup/linkcmds,
	startup/mmutlbtab.c, startup/start.S, wrapup/Makefile.am:
	The modifications to this BSP reflect the conversion of the
	mpc8xx CPU to the "new exception processing model."

6 files changed, 73 insertions, 13 deletions

diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/Makefile.am b/c/src/lib/libbsp/powerpc/mbx8xx/startup/Makefile.am
index 1047f49ab7..f112f6297a 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/Makefile.am
@@ -9,7 +9,7 @@ VPATH = @srcdir@:@srcdir@/../../../shared
 PGM = $(ARCH)/startup.rel
 
 C_FILES = bspclean.c bsplibc.c bsppost.c bspstart.c bootcard.c imbx8xx.c \
-    main.c mmutlbtab.c sbrk.c setvec.c gnatinstallhandler.c
+    main.c mmutlbtab.c sbrk.c gnatinstallhandler.c
 C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
 
 S_FILES = start.s
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c
index 7e6a7ae9cf..bf874f70b6 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c
@@ -32,6 +32,7 @@
  *  the .bss section (RAM).
  */
 extern rtems_configuration_table Configuration;
+extern unsigned long intrStackPtr;
 rtems_configuration_table  BSP_Configuration;
 
 rtems_cpu_table Cpu_table;
@@ -46,6 +47,18 @@ char *rtems_progname;
 void bsp_postdriver_hook(void);
 void bsp_libc_init( void *, unsigned32, int );
 
+void BSP_panic(char *s)
+{
+  printk("%s PANIC %s\n",_RTEMS_version, s);
+  __asm__ __volatile ("sc"); 
+}
+
+void _BSP_Fatal_error(unsigned int v)
+{
+  printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
+  __asm__ __volatile ("sc"); 
+}
+
 /*
  *  bsp_pretasking_hook
  *
@@ -116,6 +129,18 @@ void bsp_start(void)
 {
   extern void *_WorkspaceBase;
   
+  ppc_cpu_id_t myCpu;
+  ppc_cpu_revision_t myCpuRevision;
+  register unsigned char* intrStack;
+  register unsigned int intrNestingLevel = 0;
+  
+  /*
+   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
+   * store the result in global variables so that it can be used latter...
+   */
+  myCpu 	= get_ppc_cpu_type();
+  myCpuRevision = get_ppc_cpu_revision();
+
   mmu_init();
   
   /*
@@ -134,7 +159,20 @@ void bsp_start(void)
   rtems_cache_enable_data();
 #endif
 #endif
-   
+  /*
+   * Initialize some SPRG registers related to irq handling
+   */
+  
+  intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE);
+  asm volatile ("mtspr	273, %0" : "=r" (intrStack) : "0" (intrStack));
+  asm volatile ("mtspr	272, %0" : "=r" (intrNestingLevel) : "0" (intrNestingLevel));
+
+  /*
+   * Install our own set of exception vectors
+   */
+  initialize_exceptions();
+
+
   /*
    *  Allocate the memory for the RTEMS Work Space.  This can come from
    *  a variety of places: hard coded address, malloc'ed from outside
@@ -181,5 +219,13 @@ void bsp_start(void)
   m8xx.scc2p.rbase=0;
   m8xx.scc2p.tbase=0;
   m8xx_cp_execute_cmd( M8xx_CR_OP_STOP_TX | M8xx_CR_CHAN_SCC2 );
+  /*
+   * Initalize RTEMS IRQ system
+   */
+  BSP_rtems_irq_mng_init(0);
+#ifdef SHOW_MORE_INIT_SETTINGS
+  printk("Exit from bspstart\n");
+#endif  
+
 }
 
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c
index eca58e56f5..716e86ab61 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c
@@ -258,7 +258,7 @@ void _InitMBX8xx (void)
   
   /* Initialize the Periodic Interrupt Status and Control Register (PISCR) */
   m8xx.piscrk = M8xx_UNLOCK_KEY;	/* unlock PISCR */
-  m8xx.piscr = 0x0083;			/* Default MBX and firmware value. */
+  m8xx.piscr = 0x0083; 			/* Default MBX and firmware value. */
       
   /* Initialize the System Clock and Reset Control Register (SCCR)
    * Set the clock sources and division factors:
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/linkcmds b/c/src/lib/libbsp/powerpc/mbx8xx/startup/linkcmds
index 565e7f175b..5afa4b1d51 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/linkcmds
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/linkcmds
@@ -198,7 +198,15 @@ SECTIONS
   bss.size = bss.end - bss.start;
   text.size = text.end - text.start;
   PROVIDE(_end = bss.end);
-	
+  /*
+   * Interrupt stack setup
+   */
+
+  IntrStack_start = ALIGN(0x10);
+  . += 0x4000;
+  intrStack = .;
+  PROVIDE(intrStackPtr = intrStack);
+
   _HeapStart = .;
   __HeapStart = .;
   . += HeapSize;  /* XXX -- Old gld can't handle this */
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c
index 50e1a57abd..6330bc1741 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c
@@ -103,15 +103,15 @@ MMU_TLB_table_t MMU_TLB_table[] = {
 	/*
 	 *
 	 * Board Control/Status Register #1/#2: CS4, Start address 0xFA100000, (4 x 8 bits?)
-	 *	ASID=0x0, APG=0x0, guarded memory, copyback data cache policy, 
+	 *	ASID=0x0, APG=0x0, guarded memory, write-through data cache policy, 
 	 *	R/W,X for all, no ASID comparison, cache-inhibited.
 	 * EPN		TWC	RPN
 	 */
-	{ 0xFA100200,	0x11,	0xFA1009F7 },	/* BCSR - PS=4K */
+	{ 0xFA100200,	0x13,	0xFA1009F7 },	/* BCSR - PS=4K */
 	/*
 	 *
 	 * (IMMR-SPRs) Dual Port RAM: Start address 0xFA200000, 16K,
-	 *	ASID=0x0, APG=0x0, guarded memory, copyback data cache policy, 
+	 *	ASID=0x0, APG=0x0, guarded memory, write-through data cache policy, 
 	 *	R/W,X for all, no ASID comparison, cache-inhibited.
 	 *	
 	 *	Note: We use the value in MBXA/PG2, which is also the value that 
@@ -120,7 +120,7 @@ MMU_TLB_table_t MMU_TLB_table[] = {
 	 *	of the firmware.
 	 * EPN		TWC	RPN
 	 */
-	{ 0xFA200200,	0x11,	0xFA2009FF },	/* IMMR - PS=16K */
+	{ 0xFA200200,	0x13,	0xFA2009FF },	/* IMMR - PS=16K */
 	/*
 	 *
 	 * Flash: CS0, Start address 0xFE000000, 4M, (BootROM-EPPCBug)
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S b/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S
index ecd2971559..7b8dfde7f9 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S
@@ -239,14 +239,20 @@ spin:
 	lwz	r3, spin@l(r3)
 	cmpwi	r3, 0x1
 	beq	.spin
-
+/*	
+ * #define LOADED_BY_EPPCBUG
+ */
 /*
  * Initialization code 
  */
 .startup:	
         /* Get the start address. */
         mflr    r1
-
+#ifdef LOADED_BY_EPPCBUG	
+	/* Save pointer to residual/board data */
+	lis	r9,eppcbugInfo@ha
+	stw	r3,eppcbugInfo@l(r9)
+#endif	
         /* Initialize essential registers. */
         bl      initregs
         nop
@@ -270,8 +276,8 @@ spin:
         bl      bssclr
         nop
 
-        lis 5,environ@ha
-        la 5,environ@l(5)		/* environp */
+	lis	r5,environ@ha
+        la	r5,environ@l(r5)		/* environp */
         /* clear argc and argv */
         xor     r3, r3, r3
         xor     r4, r4, r4
@@ -358,7 +364,7 @@ initregs:
 	mr	r8, r0
 	mr	r9, r0
 	mr	r10, r0
-	mr	r11, r0
+	mr	r11, r0 
 	mr	r12, r0
 	mr	r13, r0
 	mr	r14, r0