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| author | Ralf Corsepius <ralf.corsepius@rtems.org> | 2008-08-20 03:41:07 +0000 |
|---|---|---|
| committer | Ralf Corsepius <ralf.corsepius@rtems.org> | 2008-08-20 03:41:07 +0000 |
| commit | 378bea5a7d75b674c79557154c964a122309b51f (patch) | |
| tree | a797ca693e2aba6ecf7c30bca438ebabbf34e4e2 /c/src/lib/libbsp/powerpc/haleakala/startup | |
| parent | 2008-08-19 Cedric Aubert <cedric_aubert@yahoo.fr> (diff) | |
| download | rtems-378bea5a7d75b674c79557154c964a122309b51f.tar.bz2 | |
Add missing prototypes.
Diffstat (limited to 'c/src/lib/libbsp/powerpc/haleakala/startup')
| -rw-r--r-- | c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c b/c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c index 8fc2cea2c5..5c564b7836 100644 --- a/c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c @@ -156,7 +156,7 @@ EarlyUARTInit(int baudRate) static void -InitUARTClock() +InitUARTClock(void) { uint32_t reg; mfsdr(SDR0_UART0,reg); @@ -184,7 +184,7 @@ void GPIO_AlternateSelect(int bitnum, int source) } } -void Init_FPGA() +void Init_FPGA(void) { /* Have to write to the FPGA to enable the UART drivers */ /* Have to enable CS2 as an output in GPIO to get the FPGA working */ |