Jay Monkman <jmonkman@frasca.com> submitted the eth_comm BSP for a PPC860

based board.

6 files changed, 688 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/Makefile.in b/c/src/lib/libbsp/powerpc/eth_comm/startup/Makefile.in
new file mode 100644
index 0000000000..7d75dfca56
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/Makefile.in
@@ -0,0 +1,61 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@:@srcdir@/../../../shared
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+PGM=${ARCH}/startup.rel
+
+# C source names, if any, go here -- minus the .c
+C_PIECES=bspclean bsplibc bsppost bspstart main sbrk setvec alloc860 mmu
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+H_FILES=
+
+# Assembly source names, if any, go here -- minus the .s
+S_PIECES=
+S_FILES=$(S_PIECES:%=%.s)
+S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o)
+
+SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
+OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS +=
+CFLAGS   +=
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS +=
+CLOBBER_ADDITIONS +=
+
+${PGM}: ${SRCS} ${OBJS}
+	$(make-rel)
+
+all:	${ARCH} $(SRCS) $(PGM)
+	$(INSTALL) $(srcdir)/linkcmds ${PROJECT_RELEASE}/lib
+
+# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
+install:  all
+
diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/alloc860.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/alloc860.c
new file mode 100644
index 0000000000..b43cb4877b
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/alloc860.c
@@ -0,0 +1,117 @@
+/*
+ * MPC860 buffer descriptor allocation routines
+ *
+ * Modified from original code by Jay Monkman (jmonkman@frasca.com)
+ *
+ * Original was written by:
+ * W. Eric Norum
+ * Saskatchewan Accelerator Laboratory
+ * University of Saskatchewan
+ * Saskatoon, Saskatchewan, CANADA
+ * eric@skatter.usask.ca
+ *
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include <rtems/rtems/intr.h>
+#include <rtems/error.h>
+#include <mpc860.h>
+#include <info.h>
+
+/*
+ * Send a command to the CPM RISC processer
+ */
+void M860ExecuteRISC(rtems_unsigned16 command)
+{
+  rtems_unsigned16 lvl;
+  
+  rtems_interrupt_disable(lvl);
+  while (m860.cpcr & M860_CR_FLG) {
+    continue;
+  }
+
+  m860.cpcr = command | M860_CR_FLG;
+  rtems_interrupt_enable (lvl);
+}
+
+
+/*
+ * Allocation order:
+ *      - Dual-Port RAM section 0
+ *      - Dual-Port RAM section 1
+ *      - Dual-Port RAM section 2
+ *      - Dual-Port RAM section 3
+ *      - Dual-Port RAM section 4
+ */
+static struct {
+  char          *base;
+  unsigned int  size;
+  unsigned int  used;
+} bdregions[] = {
+  { (char *)&m860.dpram0[0],    sizeof m860.dpram0,     0 },
+  { (char *)&m860.dpram1[0],    sizeof m860.dpram1,     0 },
+  { (char *)&m860.dpram2[0],    sizeof m860.dpram2,     0 },
+  { (char *)&m860.dpram3[0],    sizeof m860.dpram3,     0 },
+  { (char *)&m860.dpram4[0],    sizeof m860.dpram4,     0 },
+};
+
+void *
+M860AllocateBufferDescriptors (int count)
+{
+  unsigned int i;
+  ISR_Level level;
+  void *bdp = NULL;
+  unsigned int want = count * sizeof(m860BufferDescriptor_t);
+  
+  /*
+   * Running with interrupts disabled is usually considered bad
+   * form, but this routine is probably being run as part of an
+   * initialization sequence so the effect shouldn't be too severe.
+   */
+  _ISR_Disable (level);
+  for (i = 0 ; i < sizeof(bdregions) / sizeof(bdregions[0]) ; i++) {
+    /*
+     * Verify that the region exists.
+     * This test is necessary since some chips have
+     * less dual-port RAM.
+     */
+    if (bdregions[i].used == 0) {
+      volatile unsigned char *cp = bdregions[i].base;
+      *cp = 0xAA;
+      if (*cp != 0xAA) {
+        bdregions[i].used = bdregions[i].size;
+        continue;
+      }
+      *cp = 0x55;
+      if (*cp != 0x55) {
+        bdregions[i].used = bdregions[i].size;
+        continue;
+      }
+      *cp = 0x0;
+    }
+    if (bdregions[i].size - bdregions[i].used >= want) {
+      bdp = bdregions[i].base + bdregions[i].used;
+      bdregions[i].used += want;
+      break;
+    }
+  }
+  _ISR_Enable(level);
+  if (bdp == NULL)
+    rtems_panic("Can't allocate %d buffer descriptor(s).\n", count);
+  return bdp;
+}
+
+void *
+M860AllocateRiscTimers (int count)
+{
+  /*
+   * Convert the count to the number of buffer descriptors
+   * of equal or larger size.  This ensures that all buffer
+   * descriptors are allocated with appropriate alignment.
+   */
+  return M860AllocateBufferDescriptors (((count * 4) +
+                                         sizeof(m860BufferDescriptor_t) - 1) / 
+                                        sizeof(m860BufferDescriptor_t));
+}
diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c
new file mode 100644
index 0000000000..beb734031f
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c
@@ -0,0 +1,187 @@
+/*  bsp_start()
+ *
+ *  This routine starts the application.  It includes application,
+ *  board, and monitor specific initialization and configuration.
+ *  The generic CPU dependent initialization has been performed
+ *  before this routine is invoked.
+ *
+ *  The MPC860 specific stuff was written by Jay Monkman (jmonkman@frasca.com)
+ *
+ *  COPYRIGHT (c) 1989-1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#include <bsp.h>
+#include <mpc860.h>
+#include <rtems/libio.h>
+ 
+#include <libcsupport.h>
+ 
+#include <string.h>
+#include <info.h>
+ 
+#ifdef STACK_CHECKER_ON
+#include <stackchk.h>
+#endif
+
+boardinfo_t M860_binfo;
+
+
+/*
+ *  The original table from the application and our copy of it with
+ *  some changes.
+ */
+extern rtems_configuration_table Configuration;
+
+rtems_configuration_table  BSP_Configuration;
+
+rtems_cpu_table Cpu_table;
+
+char *rtems_progname;
+
+/*
+ *  Use the shared implementations of the following routines
+ */
+void bsp_postdriver_hook(void);
+void bsp_libc_init( void *, unsigned32, int );
+
+/*
+ *  Function:   bsp_pretasking_hook
+ *  Created:    95/03/10
+ *
+ *  Description:
+ *      BSP pretasking hook.  Called just before drivers are initialized.
+ *      Used to setup libc and install any BSP extensions.
+ *
+ *  NOTES:
+ *      Must not use libc (to do io) from here, since drivers are
+ *      not yet initialized.
+ *
+ */
+ 
+void
+bsp_pretasking_hook(void)
+{
+  extern int       _end;
+  rtems_unsigned32  heap_start;
+
+  /* 
+   * Let's check to see if the size of M860_binfo is what
+   * it should be. It might not be if the info.h files
+   * for RTEMS and the bootloader define boardinfo_t
+   * differently.
+   */
+
+  /* Oops. printf() won't work yet, since the console is not initialized.
+     I should probably find some way of doing this though.
+  if (M860_binfo.size != sizeof(boardinfo_t)) {
+      printf("The size of the Board Info Block appears to be incorrect.\n");
+      printf(" This could occur if the 'info.h' files for RTEMS and the\n");
+      printf(" bootloader differ in their definition of boardinfo_t\n");
+  }
+  */
+  heap_start = (rtems_unsigned32) &_end;
+
+  /* Align the heap on a natural boundary (4 bytes?) */
+  if (heap_start & (CPU_ALIGNMENT-1)) {
+    heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
+  }
+  /* set up a 256K heap */
+  bsp_libc_init((void *) heap_start, 256 * 1024, 0);
+  
+#ifdef STACK_CHECKER_ON
+  /*
+   *  Initialize the stack bounds checker
+   *  We can either turn it on here or from the app.
+   */
+  
+  Stack_check_Initialize();
+#endif
+  
+#ifdef RTEMS_DEBUG
+  rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
+#endif
+}
+
+
+void bsp_start(void)
+{
+  extern int _end;
+  rtems_unsigned32  heap_start;
+  rtems_unsigned32  ws_start;
+  /*
+   *  Allocate the memory for the RTEMS Work Space.  This can come from
+   *  a variety of places: hard coded address, malloc'ed from outside
+   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
+   *  typically done by stock BSPs) by subtracting the required amount
+   *  of work space from the last physical address on the CPU board.
+   */
+
+  /*
+   *  Need to "allocate" the memory for the RTEMS Workspace and
+   *  tell the RTEMS configuration where it is.  This memory is
+   *  not malloc'ed.  It is just "pulled from the air".
+   */
+
+  heap_start = (rtems_unsigned32) &_end;
+  if (heap_start & (CPU_ALIGNMENT-1))
+    heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
+
+
+  ws_start = heap_start + (256 * 1024);
+  if (ws_start & ((512 * 1024) - 1)) {  /* align to 512K boundary */
+    ws_start = (ws_start + (512 * 1024)) & ~((512 * 1024) - 1);
+  }
+
+  BSP_Configuration.work_space_start = (void *)ws_start;
+  BSP_Configuration.work_space_size = 512 * 1024; 
+
+  /*
+   *  initialize the CPU table for this BSP
+   */
+
+  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
+  Cpu_table.postdriver_hook = bsp_postdriver_hook;
+  Cpu_table.interrupt_stack_size = 4 * 1024;
+
+  Cpu_table.clicks_per_usec = 1;  /* for 4MHz extclk */
+  Cpu_table.serial_per_sec = 10000000;
+  Cpu_table.serial_external_clock = 1;
+  Cpu_table.serial_xon_xoff = 0;
+  Cpu_table.serial_cts_rts = 1;
+  Cpu_table.serial_rate = 9600;
+  Cpu_table.timer_average_overhead = 0;
+  Cpu_table.timer_least_valid = 0;
+  Cpu_table.clock_speed = 40000000;
+
+  /* 
+   * Call this in case we use TERMIOS for console I/O
+   */
+  m860_console_reserve_resources(&BSP_Configuration);
+
+  /*
+   * Since we are currently autodetecting whether to use SCC1 or
+   * the FEC for ethernet, we set up a register in the ethernet
+   * transciever that is used for 10/100 Mbps ethernet now, so that 
+   * we can attempt to read it later in rtems_enet_driver_attach()
+  */
+  m860.fec.mii_speed = 0x0a;
+  m860.fec.mii_data = 0x680a0000;
+
+
+  m860.scc2.sccm=0;
+  m860.scc2p.rbase=0;
+  m860.scc2p.tbase=0;
+  M860ExecuteRISC(M860_CR_OP_STOP_TX | M860_CR_CHAN_SCC2);
+
+  mmu_init(); 
+}
+
+
diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/linkcmds b/c/src/lib/libbsp/powerpc/eth_comm/startup/linkcmds
new file mode 100644
index 0000000000..d805fedf39
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/linkcmds
@@ -0,0 +1,153 @@
+/*
+ *  This file contains directives for the GNU linker which are specific
+ *  to the Ethernet-Comm Board
+ *
+ *  $Id$
+ */
+
+OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
+              "elf32-powerpc")
+OUTPUT_ARCH(powerpc)
+ SEARCH_DIR(/usr/local/powerpc-rtems/lib);
+ 
+ENTRY(start)
+ 
+MEMORY
+	{
+	ram : org = 0x0, l = 4M
+	dpram : org = 0xff000000, l = 16K
+	canbus : org = 0xff100000, l = 12K
+	flash : org = 0xfff00000, l = 512K
+	}
+
+
+SECTIONS
+{
+	.vectors :
+	{
+	  *(.vectors)
+	} >ram
+
+	/* 
+	 * The stack will live in this area - between the vectors and
+	 * the text section.
+	 */
+	
+	.text 0x10000:
+  	{
+	     text.start = .;
+	     *(.entry)
+	     *(.entry2)
+	     *(.text)
+	     *(.rodata)
+	     *(.rodata1)
+	     *(.descriptors)
+	     *(rom_ver)
+	     etext = ALIGN(0x10);
+	     _etext = .;
+	
+	     __CTOR_LIST__ = .;
+	     LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
+	     *(.ctors)
+	     LONG(0)
+	     __CTOR_END__ = .;
+	
+	     __DTOR_LIST__ = .;
+	     LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
+	     *(.dtors)
+	     LONG(0)
+	     __DTOR_END__ = .;
+	
+	     *(.lit)
+	     *(.shdata)
+	     *(.init)
+	     *(.fini)
+	     _endtext = .;
+	     text.end = .;
+	} > ram
+ 
+	/* R/W Data */
+	.data :
+	{
+	  *(.data)
+	  *(.data1)
+	  PROVIDE (__SDATA_START__ = .);
+	  *(.sdata)
+	} > ram
+	
+	PROVIDE (__EXCEPT_START__ = .);
+	.gcc_except_table   : { *(.gcc_except_table) } >RAM
+	PROVIDE (__EXCEPT_END__ = .);
+	__GOT_START__ = .;
+	.got :
+	{
+	   s.got = .;
+	   *(.got.plt) *(.got)
+	} > ram
+	__GOT_END__ = .;
+	
+	.got1		  : { *(.got1) 		} >ram
+	PROVIDE (__GOT2_START__ = .);
+	PROVIDE (_GOT2_START_ = .);
+	.got2		  :  { *(.got2) 	} >ram
+	PROVIDE (__GOT2_END__ = .);
+	PROVIDE (_GOT2_END_ = .);
+	
+	PROVIDE (__FIXUP_START__ = .);
+	PROVIDE (_FIXUP_START_ = .);
+	.fixup	  : { *(.fixup) 	} >ram
+	PROVIDE (_FIXUP_END_ = .);
+	PROVIDE (__FIXUP_END__ = .);
+	 
+	PROVIDE (__SDATA2_START__ = .);
+	.sdata2   	  : { *(.sdata2) 	} >ram
+	.sbss2   	  : { *(.sbss2) 	} >ram
+	PROVIDE (__SBSS2_END__ = .);
+	
+	.sbss2   	  : { *(.sbss2) 	} >ram
+	PROVIDE (__SBSS2_END__ = .);
+	
+	__SBSS_START__ = .;
+	.bss :
+	{
+	  bss.start = .;
+	  *(.bss) *(.sbss) *(COMMON)
+	  . = ALIGN(4);
+	  bss.end = .;
+	} > ram
+	__SBSS_END__ = .;
+
+	bss.size = bss.end - bss.start;
+	text.size = text.end - text.start;
+	PROVIDE(_end = bss.end);
+	
+        dpram : 
+	{
+          m860 = .;
+          _m860 = .;
+          . += (8 * 1024);
+        } >dpram
+
+	canbus :
+	{
+	  canbus0 = .;
+	  . += (0x1000);
+	  canbus1 = .;
+	  . += (0x1000);
+	  canbus2 = .;
+	  . += (0x1000);
+	} >canbus
+
+
+	.line 0 : { *(.line) }
+	.debug 0 : { *(.debug) }
+	.debug_sfnames 0 : { *(.debug_sfnames) }
+	.debug_srcinfo 0 : { *(.debug_srcinfo) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+	.debug_aregion 0 : { *(.debug_aregion) }
+	.debug_macinfo 0 : { *(.debug_macinfo) }
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+
+}
diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/mmu.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/mmu.c
new file mode 100644
index 0000000000..1a3f11e20a
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/mmu.c
@@ -0,0 +1,126 @@
+/* 
+ *  mmu.c - this file contains functions for initializing the MMU 
+ *
+ *  Written by Jay Monkman (jmonkman@frasca.com)
+ */
+
+#include <bsp.h>
+#include <mpc860.h>
+
+/* Macros for handling all the MMU SPRs */
+#define PUT_MI_CTR(r)   __asm__ volatile ("mtspr 0x310,%0\n" ::"r"(r))
+#define GET_MI_CTR(r)   __asm__ volatile ("mfspr %0,0x310\n" :"=r"(r))
+#define PUT_MD_CTR(r)   __asm__ volatile ("mtspr 0x318,%0\n" ::"r"(r))
+#define GET_MD_CTR(r)   __asm__ volatile ("mfspr %0,0x318\n" :"=r"(r))
+#define PUT_M_CASID(r)  __asm__ volatile ("mtspr 0x319,%0\n" ::"r"(r))
+#define GET_M_CASID(r)  __asm__ volatile ("mfspr %0,0x319\n" :"=r"(r))
+#define PUT_MI_EPN(r)   __asm__ volatile ("mtspr 0x313,%0\n" ::"r"(r))
+#define GET_MI_EPN(r)   __asm__ volatile ("mfspr %0,0x313\n" :"=r"(r))
+#define PUT_MI_TWC(r)   __asm__ volatile ("mtspr 0x315,%0\n" ::"r"(r))
+#define GET_MI_TWC(r)   __asm__ volatile ("mfspr %0,0x315\n" :"=r"(r))
+#define PUT_MI_RPN(r)   __asm__ volatile ("mtspr 0x316,%0\n" ::"r"(r))
+#define GET_MI_RPN(r)   __asm__ volatile ("mfspr %0,0x316\n" :"=r"(r))
+#define PUT_MD_EPN(r)   __asm__ volatile ("mtspr 0x313,%0\n" ::"r"(r))
+#define GET_MD_EPN(r)   __asm__ volatile ("mfspr %0,0x313\n" :"=r"(r))
+#define PUT_M_TWB(r)    __asm__ volatile ("mtspr 0x31c,%0\n" ::"r"(r))
+#define GET_M_TWB(r)    __asm__ volatile ("mfspr %0,0x31c\n" :"=r"(r))
+#define PUT_MD_TWC(r)   __asm__ volatile ("mtspr 0x31d,%0\n" ::"r"(r))
+#define GET_MD_TWC(r)   __asm__ volatile ("mfspr %0,0x31d\n" :"=r"(r))
+#define PUT_MD_RPN(r)   __asm__ volatile ("mtspr 0x31e,%0\n" ::"r"(r))
+#define GET_MD_RPN(r)   __asm__ volatile ("mfspr %0,0x31e\n" :"=r"(r))
+#define PUT_MI_AP(r)    __asm__ volatile ("mtspr 0x312,%0\n" ::"r"(r))
+#define GET_MI_AP(r)    __asm__ volatile ("mfspr %0,0x312\n" :"=r"(r))
+#define PUT_MD_AP(r)    __asm__ volatile ("mtspr 0x31a,%0\n" ::"r"(r))
+#define GET_MD_AP(r)    __asm__ volatile ("mfspr %0,0x31a\n" :"=r"(r))
+#define PUT_M_TW(r)     __asm__ volatile ("mtspr 0x31f,%0\n" ::"r"(r))
+#define GET_M_TW(r)     __asm__ volatile ("mfspr %0,0x31f\n" :"=r"(r))
+#define PUT_MI_DCAM(r)  __asm__ volatile ("mtspr 0x330,%0\n" ::"r"(r))
+#define GET_MI_DCAM(r)  __asm__ volatile ("mfspr %0,0x330\n" :"=r"(r))
+#define PUT_MI_DRAM0(r) __asm__ volatile ("mtspr 0x331,%0\n" ::"r"(r))
+#define GET_MI_DRAM0(r) __asm__ volatile ("mfspr %0,0x331\n" :"=r"(r))
+#define PUT_MI_DRAM1(r) __asm__ volatile ("mtspr 0x332,%0\n" ::"r"(r))
+#define GET_MI_DRAM1(r) __asm__ volatile ("mfspr %0,0x332\n" :"=r"(r))
+#define PUT_MD_DCAM(r)  __asm__ volatile ("mtspr 0x338,%0\n" ::"r"(r))
+#define GET_MD_DCAM(r)  __asm__ volatile ("mfspr %0,0x338\n" :"=r"(r))
+#define PUT_MD_DRAM0(r) __asm__ volatile ("mtspr 0x339,%0\n" ::"r"(r))
+#define GET_MD_DRAM0(r) __asm__ volatile ("mfspr %0,0x339\n" :"=r"(r))
+#define PUT_MD_DRAM1(r) __asm__ volatile ("mtspr 0x33a,%0\n" ::"r"(r))
+#define GET_MD_DRAM1(r) __asm__ volatile ("mfspr %0,0x33a\n" :"=r"(r))
+#define PUT_IC_CST(r)   __asm__ volatile ("mtspr 0x230,%0\n" ::"r"(r))
+#define GET_IC_CST(r)   __asm__ volatile ("mfspr %0,0x230\n" :"=r"(r))
+#define PUT_DC_CST(r)   __asm__ volatile ("mtspr 0x238,%0\n" ::"r"(r))
+#define GET_DC_CST(r)   __asm__ volatile ("mfspr %0,0x238\n" :"=r"(r))
+#define PUT_IC_ADR(r)   __asm__ volatile ("mtspr 0x231,%0\n" ::"r"(r))
+#define GET_IC_ADR(r)   __asm__ volatile ("mfspr %0,0x231\n" :"=r"(r))
+#define PUT_IC_DAT(r)   __asm__ volatile ("mtspr 0x232,%0\n" ::"r"(r))
+#define GET_IC_DAT(r)   __asm__ volatile ("mfspr %0,0x232\n" :"=r"(r))
+
+extern rtems_configuration_table BSP_Configuration;
+
+void mmu_init(void)
+{
+  register unsigned long t1, t2;
+
+  /* Let's clear MSR[IR] and MSR[DR] */ 
+  t2 = PPC_MSR_IR | PPC_MSR_DR;
+  __asm__ volatile (
+    "mfmsr    %0\n"
+    "andc     %0, %0, %1\n"
+    "mtmsr    %0\n" :"=r"(t1), "=r"(t2):
+    "1"(t2));
+
+  /* Invalidate the TLBs */
+  __asm__ volatile ("tlbia\n"::);
+  __asm__ volatile ("isync\n"::);
+
+  /* make sure no TLB entries are reserved */
+  t1 = 0;
+  PUT_MI_CTR(t1);
+
+  t1 = M860_MD_CTR_TWAM;   /* 4K pages */
+  /*  PUT_MD_CTR(t1); */
+
+  t1 = M860_MI_EPN_VALID;    /* make entry valid */
+  /*  PUT_MD_EPN(t1); */
+  PUT_MI_EPN(t1);
+
+  t1 = M860_MI_TWC_PS8 | M860_MI_TWC_VALID;   /* 8 MB pages, valid */
+  /*  PUT_MD_TWC(t1); */
+  PUT_MI_TWC(t1);
+
+  t1 = M860_MD_RPN_CHANGE | M860_MD_RPN_F | M860_MD_RPN_16K | 
+       M860_MD_RPN_SHARED | M860_MD_RPN_VALID;
+  /*  PUT_MD_RPN(t1); */
+  PUT_MI_RPN(t1);
+
+  t1 = M860_MI_AP_Kp << 30;  
+  PUT_MI_AP(t1);
+  /*  PUT_MD_AP(t1); */
+  
+  t1 = M860_CACHE_CMD_UNLOCK;
+  /*  PUT_DC_CST(t1); */
+  PUT_IC_CST(t1);
+
+  t1 = M860_CACHE_CMD_INVALIDATE;
+  /*  PUT_DC_CST(t1); */
+  PUT_IC_CST(t1);
+
+  t1 = M860_CACHE_CMD_ENABLE;
+  PUT_IC_CST(t1);
+
+  t1 = M860_CACHE_CMD_SFWT;
+  /*  PUT_DC_CST(t1); */
+  t1 = M860_CACHE_CMD_ENABLE;
+  /*  PUT_DC_CST(t1);*/
+
+
+
+  /* Let's set MSR[IR]  */ 
+  t2 = PPC_MSR_IR;
+  __asm__ volatile (
+    "mfmsr    %0\n"
+    "or       %0, %0, %1\n"
+    "mtmsr    %0\n" :"=r"(t1), "=r"(t2):
+    "1"(t2));
+
+}
diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/setvec.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/setvec.c
new file mode 100644
index 0000000000..b32dc8aaec
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/setvec.c
@@ -0,0 +1,44 @@
+/*  set_vector
+ *
+ *  This routine installs an interrupt vector on the target Board/CPU.
+ *  This routine is allowed to be as board dependent as necessary.
+ *
+ *  INPUT:
+ *    handler - interrupt handler entry point
+ *    vector  - vector number
+ *    type    - 0 indicates raw hardware connect
+ *              1 indicates RTEMS interrupt connect
+ *
+ *  RETURNS:
+ *    address of previous interrupt handler
+ *
+ *  COPYRIGHT (c) 1989-1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+
+rtems_isr_entry set_vector(                     /* returns old vector */
+  rtems_isr_entry     handler,                  /* isr routine        */
+  rtems_vector_number vector,                   /* vector number      */
+  int                 type                      /* RTEMS or RAW intr  */
+)
+{
+  rtems_isr_entry previous_isr;
+  
+  if (type) {
+    rtems_interrupt_catch(handler, vector, (rtems_isr_entry *) &previous_isr );
+  } else {
+    /* XXX: install non-RTEMS ISR as "raw" interupt */
+  }
+  return previous_isr;
+}
+