diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-02-17 20:24:53 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-02-17 20:24:53 +0000 |
| commit | ee733965291f61dd959c0f75659b0482df7a64ca (patch) | |
| tree | 1b7cd7bafa0e265b562fb8c6df14070293161c9a /c/src/lib/libbsp | |
| parent | Patch from Eric Valette <valette@crf.canon.fr> to undo the patch (diff) | |
| download | rtems-ee733965291f61dd959c0f75659b0482df7a64ca.tar.bz2 | |
Jay Monkman <jmonkman@frasca.com> submitted the eth_comm BSP for a PPC860
based board.
Diffstat (limited to 'c/src/lib/libbsp')
25 files changed, 4618 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/powerpc/eth_comm/Makefile.in b/c/src/lib/libbsp/powerpc/eth_comm/Makefile.in new file mode 100644 index 0000000000..43035c0f35 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/Makefile.in @@ -0,0 +1,25 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/directory.cfg + +SRCS=README + +# We only build the networking device driver if HAS_NETWORKING was defined +NETWORKING_DRIVER_yes_V = network +NETWORKING_DRIVER = $(NETWORKING_DRIVER_$(HAS_NETWORKING)_V) + +all: $(SRCS) + +# wrapup is the one that actually builds and installs the library +# from the individual .rel files built in other directories +SUB_DIRS=include startup start canbus console $(NETWORKING_DRIVER) wrapup + diff --git a/c/src/lib/libbsp/powerpc/eth_comm/README b/c/src/lib/libbsp/powerpc/eth_comm/README new file mode 100644 index 0000000000..87533ae4dc --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/README @@ -0,0 +1,100 @@ +# +# $Id$ +# + +BSP NAME: eth_comm +BOARD: Frasca International, Inc Ethernet Comm board +BUS: N/A +CPU FAMILY: ppc +CPU: PowerPC MPC860/MPC860T +COPROCESSORS: N/A +MODE: 32 bit mode + +DEBUG MONITOR: None + +PERIPHERALS +=========== +TIMERS: PIT + RESOLUTION: 1 microsecond +SERIAL PORTS: 4 SCCs (one is used for ethernet on MPC860, and unused + on MPC860T), 2 SMC, 4 on external FPGA, 3 CANBUS +REAL-TIME CLOCK: +DMA: Each serial port +VIDEO: none +SCSI: none +NETWORKING: Ethernet (10 Mbps) on SCC1 (MPC860) + Fast ethernet (100/10 Mbps) on FEC (MPC860T) + +DRIVER INFORMATION +================== +CLOCK DRIVER: +IOSUPP DRIVER: +SHMSUPP: none +TIMER DRIVER: + +STDIO +===== +PORT: SCC2 +ELECTRICAL: RS-232 +BAUD: 9600 +BITS PER CHARACTER: 8 +PARITY: None +STOP BITS: 1 + +NOTES +===== +On-chip resources: + SCC1 network or console + SCC2 console + SCC3 console + SCC4 console + CLK1 network + CLK2 network + CLK3 + CLK4 + CLK5 + CLK6 + CLK7 + CLK8 + BRG1 console + BRG2 console + BRG3 console + BRG4 console + RTC + PIT clock + TB + DEC + SWT + *CS0 FLASH + *CS1 DRAM bank 1 + *CS2 CAN0 + *CS3 CAN1 + *CS4 CAN2 + *CS5 MB1 + *CS6 ARINC + *CS7 DRAM bank 0 + UPMA + UPMB + IRQ0 + IRQ1 + IRQ2 CAN2 + IRQ3 CAN0 + IRQ4 CAN1 + IRQ5 + IRQ6 + IRQ7 + IRQ_LVL0 clock - PIT + IRQ_LVL1 + IRQ_LVL2 + IRQ_LVL3 + IRQ_LVL4 + IRQ_LVL5 + IRQ_LVL6 + IRQ_LVL7 +Board description +----------------- +Clock rate: 40 - 66 MHz, depending on CPU +Bus width: 16 bit Flash, 32 bit DRAM +FLASH: 128K - 1024K, 120ns +RAM: 2 - 32M DRAM SIMM, autodetects size and speed + diff --git a/c/src/lib/libbsp/powerpc/eth_comm/bsp_specs b/c/src/lib/libbsp/powerpc/eth_comm/bsp_specs new file mode 100644 index 0000000000..ef57a1a4a7 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/bsp_specs @@ -0,0 +1,23 @@ +%rename cpp old_cpp +%rename lib old_lib +%rename endfile old_endfile +%rename startfile old_startfile +%rename link old_link + +*cpp: +%(old_cpp) %{qrtems: -D__embedded__} -Asystem(embedded) + +*lib: +%{!qrtems: %(old_lib)} %{qrtems: ecrti%O%s --start-group \ +%{!qrtems_debug: -lrtemsall} %{qrtems_debug: -lrtemsall_g} \ +-lc -lgcc --end-group \ +%{!qnolinkcmds: -T linkcmds%s}} + +*startfile: +%{!qrtems: %(old_startfile)} %{qrtems: \ +%{!qrtems_debug: } \ +%{qrtems_debug: }} + +*link: +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -u __vectors -N -u start -e start} + diff --git a/c/src/lib/libbsp/powerpc/eth_comm/canbus/Makefile.in b/c/src/lib/libbsp/powerpc/eth_comm/canbus/Makefile.in new file mode 100644 index 0000000000..3c867b87b6 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/canbus/Makefile.in @@ -0,0 +1,54 @@ +# +# $Id: +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +PGM=${ARCH}/canbus.rel + +# C source names, if any, go here -- minus the .c +C_PIECES=canbus +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +SRCS=$(C_FILES) $(H_FILES) +OBJS=$(C_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile +install: all diff --git a/c/src/lib/libbsp/powerpc/eth_comm/canbus/canbus.c b/c/src/lib/libbsp/powerpc/eth_comm/canbus/canbus.c new file mode 100644 index 0000000000..70ad23a609 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/canbus/canbus.c @@ -0,0 +1,479 @@ +/* + * RTEMS CANBUS driver for eth-comm BSP + * + * Written by Jay Monkman (jmonkman@frasca.com) + * + * COPYRIGHT (c) 1998 + * Frasca International, Inc. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Note: All of this code assumes a 10Mhz clock input to the 82527 + * + * $Id: + */ +#include <stdio.h> +#include <bsp.h> +#include <mpc860.h> +#include <rtems/error.h> +#include <canbus.h> +/* How many CAN interfaces are there? */ +#define NUM_CAN_DEVS 3 + +/* How many received messages should be buffered for each channel */ +#define RX_CAN_BUF_SIZE 16 + +int rxMsgBufHead[NUM_CAN_DEVS]; +int rxMsgBufTail[NUM_CAN_DEVS]; +i82527_msg_t rxMsgBuf[NUM_CAN_DEVS][RX_CAN_BUF_SIZE]; + +volatile i82527_t *candev[NUM_CAN_DEVS]; + + +static rtems_isr +canInterruptHandler (rtems_vector_number v) +{ + int dev; + int tmpTail; + + switch (v) { + case PPC_IRQ_IRQ3: dev = 0; break; + case PPC_IRQ_IRQ4: dev = 1; break; + case PPC_IRQ_IRQ2: dev = 2; break; + default: return; /* something screwed up */ + } + + /* we only do rx interrupts right now */ + if (!(candev[dev]->msg15.ctrl1 & I82527_MSG_CTRL_NEWDAT)) { + /* Hmmm, that's odd. Why were we triggered? */ + candev[dev]->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_INTPND_CLR | + I82527_MSG_CTRL_MSGVAL_SET); + candev[dev]->msg15.ctrl1 = 0xff & (I82527_MSG_CTRL_RMTPND_CLR | + I82527_MSG_CTRL_MSGLST_CLR | + I82527_MSG_CTRL_NEWDAT_CLR); + return; + } + tmpTail = rxMsgBufTail[dev]; + while (1) { + if ((tmpTail == rxMsgBufHead[dev]) && + (rxMsgBuf[dev][tmpTail].ctrl1 & I82527_MSG_CTRL_NEWDAT)) { + break; /* Buf is full */ + } + + if (!(rxMsgBuf[dev][tmpTail].ctrl1 & I82527_MSG_CTRL_NEWDAT)) { + int pkt_len; + int i; + + rxMsgBuf[dev][tmpTail].ctrl0 = candev[dev]->msg15.ctrl0; + rxMsgBuf[dev][tmpTail].ctrl1 = candev[dev]->msg15.ctrl1; + rxMsgBuf[dev][tmpTail].arb = candev[dev]->msg15.arb; + rxMsgBuf[dev][tmpTail].cfg = candev[dev]->msg15.cfg; + + pkt_len = (rxMsgBuf[dev][tmpTail].cfg >> 4) & 0xf; + for (i=0; i<pkt_len; i++) { + rxMsgBuf[dev][tmpTail].data[i] = candev[dev]->msg15.data[i]; + } + + tmpTail++; + if (tmpTail == RX_CAN_BUF_SIZE) { + tmpTail = 0; + } + + rxMsgBufTail[dev] = tmpTail; + + break; + } + + tmpTail++; + if (tmpTail == RX_CAN_BUF_SIZE) { + tmpTail = 0; + } + if (tmpTail == rxMsgBufTail[dev]) { + break; + } + } + + + candev[dev]->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_MSGVAL_SET | + I82527_MSG_CTRL_INTPND_CLR); + candev[dev]->msg15.ctrl1 = 0xff & (I82527_MSG_CTRL_NEWDAT_CLR | + I82527_MSG_CTRL_RMTPND_CLR); + candev[dev]->status = 0x0; +} + +rtems_device_driver canbus_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + int i,j; + char dev_str[16]; /* This allows us to have a device name up to */ + /* 15 chars long. If we only use names like */ + /* /dev/can0 (9 chars) we will be fine up to */ + /* /dev/can9999999 */ + rtems_status_code status; + rtems_isr_entry old_handler; + +#if (NUM_CAN_DEVS > 0) + candev[0]=&canbus0; + rtems_interrupt_catch (canInterruptHandler, + PPC_IRQ_IRQ3, + &old_handler); + +#if (NUM_CAN_DEVS > 1) + candev[1]=&canbus1; + rtems_interrupt_catch (canInterruptHandler, + PPC_IRQ_IRQ4, + &old_handler); + +#if (NUM_CAN_DEVS > 2) + candev[2]=&canbus2; + rtems_interrupt_catch (canInterruptHandler, + PPC_IRQ_IRQ2, + &old_handler); + + /* Right now, we only support 3 CAN interfaces */ +#else +#error NUM_CAN_DEVS is too big. Fix it, damnit! +#endif /* NUM_CAN_DEVS > 2 */ +#endif /* NUM_CAN_DEVS > 1 */ +#else +#error NUM_CAN_DEVS is 0. It needs to be at least 1 +#endif /* NUM_CAN_DEVS > 0 */ + + + for (i=0; i < NUM_CAN_DEVS; i++) { + + /* clear rx buffers */ + rxMsgBufHead[i] = 0; + rxMsgBufTail[i] = 0; + for (j=0; j < RX_CAN_BUF_SIZE; j++) { + rxMsgBuf[i][j].ctrl0 = 0x55; /* all flags are cleared */ + rxMsgBuf[i][j].ctrl1 = 0x55; /* all flags are cleared */ + } + + candev[i]->ctrl = I82527_CTRL_CCE | /* Enable cfg reg writes */ + I82527_CTRL_INIT; /* Disable external xfers */ + + candev[i]->cir = I82527_CIR_DMC; /* Divide memory clock by 2 */ + + + /* We want 250 kbps so assuming an input clock rate of 10 MHz: + * DSC = 0 => SCLK = 10 MHz, tSCLK = 100ns + * BRP = 1 => tq = 200ns + * tSYNC_SEG = 1 tq + * tSEG1 = TSEG1+1 = 14+1 = 15 + * tSEG2 = TSEG2+1 = 3+1 = 4 + * + * bittime = tSYNC_SEG + tSEG1 + tSEG2 + * = 1 + 15 + 4 = 20 + * baudrate = 1/(bittime * tq) = 1/(20 * 200ns) = 1/(4000ns) = 250 kbps + */ + candev[i]->btr0 = 0xc1; /* Baud rate prescaler=0, Sync jump width=3 */ + + candev[i]->btr1 = I82527_BTR1_SPL | /* go for noise immunity */ + (0x3 << 4) | /* TSEG2 = 3 */ + (0xe); /* TSEG1 = 14 */ + + candev[i]->gms = 0xffff; /* addresses must match exactly */ + candev[i]->gml = 0xffffffff; /* addresses must match exactly */ + + candev[i]->mlm = 0x0; /* all addresses accepted */ + + candev[i]->p2conf = 0xff; /* make all outputs */ + + candev[i]->msg1.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ + candev[i]->msg1.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ + I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ + I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ + I82527_MSG_CTRL_INTPND_CLR; + + candev[i]->msg2.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ + candev[i]->msg2.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ + I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ + I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ + I82527_MSG_CTRL_INTPND_CLR; + + candev[i]->msg3.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ + candev[i]->msg3.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ + I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ + I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ + I82527_MSG_CTRL_INTPND_CLR; + + candev[i]->msg4.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ + candev[i]->msg4.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ + I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ + I82527_MSG_CTRL_RXIE_CLR | /* no rx interrupts */ + I82527_MSG_CTRL_INTPND_CLR; + + candev[i]->msg5.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ + candev[i]->msg5.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ + I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ + I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ + I82527_MSG_CTRL_INTPND_CLR; + + candev[i]->msg6.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ + candev[i]->msg6.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ + I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ + I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ + I82527_MSG_CTRL_INTPND_CLR; + + candev[i]->msg7.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ + candev[i]->msg7.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ + I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ + I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ + I82527_MSG_CTRL_INTPND_CLR; + + candev[i]->msg8.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ + candev[i]->msg8.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ + I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ + I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ + I82527_MSG_CTRL_INTPND_CLR; + + candev[i]->msg9.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ + candev[i]->msg9.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ + I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ + I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ + I82527_MSG_CTRL_INTPND_CLR; + + candev[i]->msg10.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ + candev[i]->msg10.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ + I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ + I82527_MSG_CTRL_RXIE_CLR | /* no rx interrupts */ + I82527_MSG_CTRL_INTPND_CLR; + + candev[i]->msg11.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ + candev[i]->msg11.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ + I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ + I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ + I82527_MSG_CTRL_INTPND_CLR; + + candev[i]->msg12.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ + candev[i]->msg12.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ + I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ + I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ + I82527_MSG_CTRL_INTPND_CLR; + + candev[i]->msg13.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ + candev[i]->msg13.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ + I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ + I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ + I82527_MSG_CTRL_INTPND_CLR; + + candev[i]->msg14.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */ + candev[i]->msg14.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ + I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ + I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ + I82527_MSG_CTRL_INTPND_CLR; + + candev[i]->msg15.cfg = 0 ; /* dir is rcv */ + candev[i]->msg15.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */ + I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */ + I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */ + I82527_MSG_CTRL_INTPND_CLR; + candev[i]->msg15.ctrl1 = I82527_MSG_CTRL_RMTPND_CLR | + I82527_MSG_CTRL_TXRQ_CLR | + I82527_MSG_CTRL_MSGLST_CLR | + I82527_MSG_CTRL_NEWDAT_CLR; + + } + + if ((status=rtems_io_register_name ("/dev/can0", major, 0)) != + RTEMS_SUCCESSFUL) { + rtems_fatal_error_occurred (status); + } + if ((status=rtems_io_register_name ("/dev/can1", major, 1)) != + RTEMS_SUCCESSFUL) { + rtems_fatal_error_occurred (status); + } + if ((status=rtems_io_register_name ("/dev/can2", major, 2)) != + RTEMS_SUCCESSFUL) { + rtems_fatal_error_occurred (status); + } + return RTEMS_SUCCESSFUL; +} + +rtems_device_driver canbus_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + /* msg is in use, rx interrupts are enabled */ + candev[minor]->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_MSGVAL_SET | + I82527_MSG_CTRL_RXIE_SET); + + candev[minor]->ctrl |= I82527_CTRL_IE; + candev[minor]->ctrl &= ~(I82527_CTRL_CCE | I82527_CTRL_INIT); + switch (minor) { + case 0: m860.simask |= M860_SIMASK_IRM3; break; + case 1: m860.simask |= M860_SIMASK_IRM4; break; + case 2: m860.simask |= M860_SIMASK_IRM2; break; + default: return; + } + + return RTEMS_SUCCESSFUL; +} + +rtems_device_driver canbus_close( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + /* msg is not in use, rx & txinterrupts are disbled */ + candev[minor]->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_MSGVAL_CLR | + I82527_MSG_CTRL_RXIE_CLR | + I82527_MSG_CTRL_TXIE_CLR); + + /* Take transceiver off the bus, enable cfg. reg. writes */ + candev[minor]->ctrl |= (I82527_CTRL_CCE | I82527_CTRL_INIT); + + return RTEMS_SUCCESSFUL; +} + + +rtems_device_driver canbus_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + i82527_msg_t *msg; + int i; + int tmpHead; + + msg = arg; + tmpHead = rxMsgBufHead[minor]; + + while (1){ + if ((tmpHead == rxMsgBufTail[minor]) && + !(rxMsgBuf[minor][tmpHead].ctrl1 & I82527_MSG_CTRL_NEWDAT)) { + break; + } + if (rxMsgBuf[minor][tmpHead].ctrl1 & I82527_MSG_CTRL_NEWDAT) { + int pkt_len; + msg->ctrl0 = rxMsgBuf[minor][tmpHead].ctrl0; + msg->ctrl1 = rxMsgBuf[minor][tmpHead].ctrl1; + msg->arb = rxMsgBuf[minor][tmpHead].arb; + msg->cfg = rxMsgBuf[minor][tmpHead].cfg; + + pkt_len = (msg->cfg >> 4) & 0xf; + for (i=0; i<pkt_len; i++) { + msg->data[i] = rxMsgBuf[minor][tmpHead].data[i]; + } + rxMsgBuf[minor][tmpHead].ctrl1 = 0xff & I82527_MSG_CTRL_NEWDAT_CLR; + + tmpHead++; + if (tmpHead == RX_CAN_BUF_SIZE) { + tmpHead = 0; + } + rxMsgBufHead[minor] = tmpHead; + + return RTEMS_SUCCESSFUL; + + } + + tmpHead++; + if (tmpHead == RX_CAN_BUF_SIZE) { + tmpHead = 0; + } + if (tmpHead == rxMsgBufHead[minor]) { + break; + } + } + + return RTEMS_UNSATISFIED; + +} + +rtems_device_driver canbus_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + i82527_msg_t *msg; + int i; + + msg = arg; + while(candev[minor]->msg1.ctrl1 & I82527_MSG_CTRL_TXRQ){ + continue; + } + candev[minor]->msg1.ctrl1 = 0xff & I82527_MSG_CTRL_CPUUPD_SET; + + candev[minor]->msg1.cfg = msg->cfg; + candev[minor]->msg1.arb = msg->arb; + + for (i=0; i < ((msg->cfg >> 4) & 0xff); i++) { + candev[minor]->msg1.data[i] = msg->data[i]; + } + + candev[minor]->msg1.ctrl0 = 0xff & (I82527_MSG_CTRL_INTPND_CLR | + I82527_MSG_CTRL_MSGVAL_SET | + I82527_MSG_CTRL_TXIE_CLR); + candev[minor]->msg1.cfg |= I82527_MSG_CFG_DIR; + candev[minor]->msg1.ctrl1 = 0xff & (I82527_MSG_CTRL_NEWDAT_SET | + I82527_MSG_CTRL_CPUUPD_CLR | + I82527_MSG_CTRL_TXRQ_SET); + + + + return RTEMS_SUCCESSFUL; +} +rtems_device_driver canbus_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + return RTEMS_SUCCESSFUL; +} + + +/* part of old canbus_read */ +#if 0 + for (i=0; i < RX_CAN_BUF_SIZE) { + if (rxMsgBuf[minor][i].ctrl1 & I82527_MSG_CTRL_NEWDAT) + break; + } + + if (i < RX_CAN_BUF_SIZE) { + int pkt_len; + int j; + msg.arb = rxMsgBuf[minor][i].arb; + msg.cfg = rxMsgBuf[minor][i].cfg; + + pkt_len = (msg.cfg >> 4) & 0xf; + + for (j=0; j < pkt_len; j++) + msg.data[j] = rxMsgBuf[minor][i].data[j]; + + + /* wait until there is a msg */ + while (!(candev->msg15.ctrl1 & I82527_MSG_CTRL_NEWDAT)) + continue; + + msg->ctrl1 = candev->msg15.ctrl1; + msg->cfg = candev->msg15.cfg; + msg->arb = candev->msg15.arb; + + for (i=0; i < ((candev->msg15.cfg >> 4) & 0xff); i++) { + msg->data[i] = candev->msg15.data[i]; + } + + candev->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_MSGVAL_SET | + I82527_MSG_CTRL_INTPND_CLR); + candev->msg15.ctrl1 = 0xff & (I82527_MSG_CTRL_NEWDAT_CLR | + I82527_MSG_CTRL_RMTPND_CLR); + + candev->status = 0x0; + + + return RTEMS_SUCCESSFUL; +#endif + + diff --git a/c/src/lib/libbsp/powerpc/eth_comm/console/Makefile.in b/c/src/lib/libbsp/powerpc/eth_comm/console/Makefile.in new file mode 100644 index 0000000000..d3ddaf5053 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/console/Makefile.in @@ -0,0 +1,54 @@ +# +# $Id: +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +PGM=${ARCH}/console.rel + +# C source names, if any, go here -- minus the .c +C_PIECES=console +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +SRCS=$(C_FILES) $(H_FILES) +OBJS=$(C_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile +install: all diff --git a/c/src/lib/libbsp/powerpc/eth_comm/console/console.c b/c/src/lib/libbsp/powerpc/eth_comm/console/console.c new file mode 100644 index 0000000000..b857c0e280 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/console/console.c @@ -0,0 +1,233 @@ +#define I_WANT_TERMIOS +/* + * BSP specific Serial I/O Functions for the eth-comm BSP + * + * This file contains the BSP specific functions for + * performing serial I/O. These are the functions + * RTEMS uses (the 6 listed in the device driver + * structure) + * + * The SCCs and SMCs are assigned as follows + * + * Channel Device Minor Termios + * SMC1 /dev/tty0 0 no + * SMC2 /dev/tty1 1 no + * SCC1 ethernet + * SCC2 /dev/console 3 yes + * SCC3 /dev/tty3 4 no + * SCC4 /dev/tty4 5 no + * + * FIXME: This should use termios for /dev/console, but it doesn't + * appear to work correctly yet. On startup, with termios enabled, + * the board hangs for a few seconds before running correctly + * + * Author: Jay Monkman (jmonkman@frasca.com) + * Copyright (C) 1998 by Frasca International, Inc. + * + */ +#include <rtems/libio.h> +#include <mpc860.h> +#include <mpc860/console.h> +#include <termios.h> + +rtems_device_driver console_initialize(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg) +{ + rtems_status_code status; + rtems_isr_entry old_handler; + rtems_status_code sc; + +#ifdef I_WANT_TERMIOS + /* + * Set up TERMIOS (for /dev/console) + */ + rtems_termios_initialize(); +#endif + + /* + * Set up Buffer Descriptors + */ + m860_console_initialize(); + + /* + * Do device-specific initialization + */ + m860_scc_initialize(2); /* /dev/console */ + m860_scc_initialize(3); /* /dev/tty3 */ + m860_scc_initialize(4); /* /dev/tty4 */ + m860_smc_initialize(1); /* /dev/tty0 */ + m860_smc_initialize(2); /* /dev/tty1 */ + + sc = rtems_interrupt_catch (m860_scc2_console_interrupt_handler, + PPC_IRQ_CPM_SCC2, + &old_handler); + sc = rtems_interrupt_catch (m860_scc3_console_interrupt_handler, + PPC_IRQ_CPM_SCC3, + &old_handler); + sc = rtems_interrupt_catch (m860_scc4_console_interrupt_handler, + PPC_IRQ_CPM_SCC4, + &old_handler); + sc = rtems_interrupt_catch (m860_smc1_console_interrupt_handler, + PPC_IRQ_CPM_SMC1, + &old_handler); + sc = rtems_interrupt_catch (m860_smc2_console_interrupt_handler, + PPC_IRQ_CPM_SMC2, + &old_handler); + + /* + * Register the devices + */ + status = rtems_io_register_name ("/dev/console", major, SCC2_MINOR); + if (status != RTEMS_SUCCESSFUL) + rtems_fatal_error_occurred (status); + status = rtems_io_register_name ("/dev/tty0", major, SMC1_MINOR); + if (status != RTEMS_SUCCESSFUL) + rtems_fatal_error_occurred (status); + status = rtems_io_register_name ("/dev/tty1", major, SMC2_MINOR); + if (status != RTEMS_SUCCESSFUL) + rtems_fatal_error_occurred (status); + status = rtems_io_register_name ("/dev/tty3", major, SCC3_MINOR); + if (status != RTEMS_SUCCESSFUL) + rtems_fatal_error_occurred (status); + status = rtems_io_register_name ("/dev/tty4", major, SCC4_MINOR); + if (status != RTEMS_SUCCESSFUL) + rtems_fatal_error_occurred (status); + return RTEMS_SUCCESSFUL; +} + +rtems_device_driver console_open(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg) +{ + volatile m860SCCRegisters_t *sccregs; + +#ifdef I_WANT_TERMIOS + static const rtems_termios_callbacks sccPollCallbacks = { + NULL, /* firstOpen */ + NULL, /* lastClose */ + m860_char_poll_read, /* pollRead */ + m860_char_poll_write, /* write */ + m860_scc_set_attributes, /* setAttributes */ + NULL, /* stopRemoteTx */ + NULL, /* startRemoteTx */ + 0 /* outputUsesInterrupts */ + }; +#endif /* I_WANT_TERMIOS */ + + sccregs = 0; + + switch (minor) { + case 0: + m860.smc1.smcm = 1; /* Enable SMC1 RX interrupts */ + m860.cimr |= 1UL << 4; /* Enable SMC1 interrupts */ + break; + case 1: + m860.smc2.smcm = 1; /* Enable SMC2 RX interrupts */ + m860.cimr |= 1UL << 3; /* Enable SMC2 interrupts */ + break; + case 2: + m860.cimr |= 1UL << 30; /* Enable SCC1 interrupts */ + sccregs = &m860.scc1; + break; + case 3: +#ifndef I_WANT_TERMIOS + m860.cimr |= 1UL << 29; /* Enable SCC2 interrupts */ +#endif /* I_WANT_TERMIOS */ + sccregs = &m860.scc2; + break; + case 4: + m860.cimr |= 1UL << 28; /* Enable SCC3 interrupts */ + sccregs = &m860.scc3; + break; + case 5: + m860.cimr |= 1UL << 27; /* Enable SCC4 interrupts */ + sccregs = &m860.scc4; + break; + default: + rtems_panic ("CONSOLE: bad minor number"); + } + + if (sccregs) + sccregs->sccm=0x3; + +#ifdef I_WANT_TERMIOS + if (minor == SCC2_MINOR) { + return rtems_termios_open (major, minor, arg, &sccPollCallbacks); + } + else { + return RTEMS_SUCCESSFUL; + } +#else + return RTEMS_SUCCESSFUL; +#endif +} + +rtems_device_driver console_close(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg) +{ +#ifdef I_WANT_TERMIOS + if (minor == SCC2_MINOR) { + return rtems_termios_close (arg); + } + else { + return RTEMS_SUCCESSFUL; + } +#else + return RTEMS_SUCCESSFUL; +#endif +} + +rtems_device_driver console_read(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg) +{ +#ifdef I_WANT_TERMIOS + if (minor == SCC2_MINOR) { + return rtems_termios_read(arg); + } + else { + return m860_console_read(major, minor, arg); + } +#else + return m860_console_read(major, minor, arg); +#endif +} + +rtems_device_driver console_write(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg) +{ +#ifdef I_WANT_TERMIOS + if (minor == SCC2_MINOR) { + return rtems_termios_write(arg); + } + else { + return m860_console_write(major, minor, arg); + } +#else + return m860_console_write(major, minor, arg); +#endif +} + +/* + * Handle ioctl request. + * Should set hardware line speed, bits/char, etc. + */ +rtems_device_driver console_control(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg) +{ +#ifdef I_WANT_TERMIOS + if (minor == SCC2_MINOR) { + return rtems_termios_ioctl (arg); + } + else { + return RTEMS_SUCCESSFUL; + } +#else + return RTEMS_SUCCESSFUL; +#endif +} + diff --git a/c/src/lib/libbsp/powerpc/eth_comm/include/Makefile.in b/c/src/lib/libbsp/powerpc/eth_comm/include/Makefile.in new file mode 100644 index 0000000000..7fda2ca6d4 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/include/Makefile.in @@ -0,0 +1,33 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +H_FILES = $(srcdir)/bsp.h $(srcdir)/coverhd.h $(srcdir)/canbus.h $(srcdir)/info.h + +# +# Equate files are for including from assembly preprocessed by +# gm4 or gasp. No examples are provided except for those for +# other CPUs. The best way to generate them would be to +# provide a program which generates the constants used based +# on the C equivalents. +# + +EQ_FILES = + +SRCS=$(H_FILES) $(EQ_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +all: $(SRCS) + $(INSTALL) -m 444 $(H_FILES) $(PROJECT_INCLUDE) + $(INSTALL) -m 444 $(EQ_FILES) $(PROJECT_INCLUDE) diff --git a/c/src/lib/libbsp/powerpc/eth_comm/include/bsp.h b/c/src/lib/libbsp/powerpc/eth_comm/include/bsp.h new file mode 100644 index 0000000000..c6f774d679 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/include/bsp.h @@ -0,0 +1,116 @@ +/* bsp.h + * + * This include file contains all board IO definitions. + * + * XXX : put yours in here + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef __NO_BSP_h +#define __NO_BSP_h + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rtems.h> +#include <console.h> +#include <clockdrv.h> + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; +extern int rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_enet_driver_attach + +/* + * We need to decide how much memory will be non-cacheable. This + * will mainly be memory that will be used in DMA (network and serial + * buffers). + */ +#define NOCACHE_MEM_SIZE 512*1024 + +/* + * Define the time limits for RTEMS Test Suite test durations. + * Long test and short test duration limits are provided. These + * values are in seconds and need to be converted to ticks for the + * application. + * + */ + +#define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ +#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), PPC_IRQ_SCALL, 1 ) + +#define Cause_tm27_intr() asm volatile ("sc") + +#define Clear_tm27_intr() + +#define Lower_tm27_intr() + +/* Constants */ + +#define RAM_START 0 +#define RAM_END 0x100000 + +/* miscellaneous stuff assumed to exist */ + +extern rtems_configuration_table BSP_Configuration; + +/* + * Device Driver Table Entries + */ + +/* + * NOTE: Use the standard Console driver entry + */ + +/* + * NOTE: Use the standard Clock driver entry + */ + +/* + * How many libio files we want + */ + +#define BSP_LIBIO_MAX_FDS 20 + +/* functions */ + +void bsp_cleanup( void ); + +void M860ExecuteRISC( rtems_unsigned16 command ); +void *M860AllocateBufferDescriptors( int count ); +void *M860AllocateRiscTimers( int count ); +extern char M860DefaultWatchdogFeeder; + +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/powerpc/eth_comm/include/canbus.h b/c/src/lib/libbsp/powerpc/eth_comm/include/canbus.h new file mode 100644 index 0000000000..bcac59343c --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/include/canbus.h @@ -0,0 +1,172 @@ +/* canbus.h + * + * This include file contains all canbus IO definitions + * + * Written by Jay Monkman (jmonkman@frasca.com) + * + * COPYRIGHT (c) 1998 + * Frasca International, Inc. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#ifndef __CANBUS_H_ +#define __CANBUS_H_ + +#include <rtems.h> + +typedef struct i82527_msg_t_ { + rtems_unsigned8 ctrl0 __attribute__ ((packed)); /* Control 0 register */ + rtems_unsigned8 ctrl1 __attribute__ ((packed)); /* Control 1 register */ + rtems_unsigned32 arb __attribute__ ((packed)); /* Arbitration reg */ + rtems_unsigned8 cfg __attribute__ ((packed)); /* Message config reg */ + rtems_unsigned8 data[8] __attribute__ ((packed)); /* Actual message */ +} i82527_msg_t; + +typedef struct i82527_t_ { + rtems_unsigned8 ctrl __attribute__ ((packed)); /* Control register */ + rtems_unsigned8 status __attribute__ ((packed)); /* Status register */ + rtems_unsigned8 cir __attribute__ ((packed)); /* CPU interface reg */ + rtems_unsigned8 _res0 __attribute__ ((packed)); + rtems_unsigned16 hsr __attribute__ ((packed)); /* High speed read */ + rtems_unsigned16 gms __attribute__ ((packed)); /* Global Mask - std */ + rtems_unsigned32 gml __attribute__ ((packed)); /* Global Mask - long */ + rtems_unsigned32 mlm __attribute__ ((packed)); /* Mask last message */ + i82527_msg_t msg1 __attribute__ ((packed)); /* Message 1 */ + rtems_unsigned8 clkout __attribute__ ((packed)); /* CLKOUT register */ + i82527_msg_t msg2 __attribute__ ((packed)); /* Message 2 */ + rtems_unsigned8 bcr __attribute__ ((packed)); /* Bus config register */ + i82527_msg_t msg3 __attribute__ ((packed)); /* Message 3 */ + rtems_unsigned8 btr0 __attribute__ ((packed)); /* Bit timing reg 0 */ + i82527_msg_t msg4 __attribute__ ((packed)); /* Message 4 */ + rtems_unsigned8 btr1 __attribute__ ((packed)); /* Bit timing reg 1 */ + i82527_msg_t msg5 __attribute__ ((packed)); /* Message 5 */ + rtems_unsigned8 intr __attribute__ ((packed)); /* Interrupt register */ + i82527_msg_t msg6 __attribute__ ((packed)); /* Message 6 */ + rtems_unsigned8 _res1 __attribute__ ((packed)); + i82527_msg_t msg7 __attribute__ ((packed)); /* Message 7 */ + rtems_unsigned8 _res2 __attribute__ ((packed)); + i82527_msg_t msg8 __attribute__ ((packed)); /* Message 8 */ + rtems_unsigned8 _res3 __attribute__ ((packed)); + i82527_msg_t msg9 __attribute__ ((packed)); /* Message 9 */ + rtems_unsigned8 p1conf __attribute__ ((packed)); /* Port 1 config */ + i82527_msg_t msg10 __attribute__ ((packed)); /* Message 10 */ + rtems_unsigned8 p2conf __attribute__ ((packed)); /* Port 2 config */ + i82527_msg_t msg11 __attribute__ ((packed)); /* Message 11 */ + rtems_unsigned8 p1in __attribute__ ((packed)); /* Port 1 in */ + i82527_msg_t msg12 __attribute__ ((packed)); /* Message 12 */ + rtems_unsigned8 p2in __attribute__ ((packed)); /* Port 2 in */ + i82527_msg_t msg13 __attribute__ ((packed)); /* Message 13 */ + rtems_unsigned8 p1out __attribute__ ((packed)); /* Port 1 out */ + i82527_msg_t msg14 __attribute__ ((packed)); /* Message 14 */ + rtems_unsigned8 p2out __attribute__ ((packed)); /* Port 2 out */ + i82527_msg_t msg15 __attribute__ ((packed)); /* Message 15 */ + rtems_unsigned8 sra __attribute__ ((packed)); /* Serial reset address */ +} i82527_t; + +#define I82527_CTRL_CCE (1<<6) +#define I82527_CTRL_EIE (1<<3) +#define I82527_CTRL_SIE (1<<2) +#define I82527_CTRL_IE (1<<1) +#define I82527_CTRL_INIT (1) +#define I82527_STATUS_BOFF (1<<7) +#define I82527_STATUS_WARN (1<<6) +#define I82527_STATUS_WAKE (1<<5) +#define I82527_STATUS_RXOK (1<<4) +#define I82527_STATUS_TXOK (1<<3) +#define I82527_STATUS_LEC (7) +#define I82527_STATUS_LEC_NONE 0 +#define I82527_STATUS_LEC_STUFF 1 +#define I82527_STATUS_LEC_FORM 2 +#define I82527_STATUS_LEC_ACK 3 +#define I82527_STATUS_LEC_BIT1 4 +#define I82527_STATUS_LEC_BIT0 5 +#define I82527_STATUS_LEC_CRC 6 +#define I82527_CIR_RSTSTAT (1<<7) +#define I82527_CIR_DSC (1<<6) +#define I82527_CIR_DMC (1<<5) +#define I82527_CIR_PWD (1<<4) +#define I82527_CIR_SLEEP (1<<3) +#define I82527_CIR_MUX (1<<2) +#define I82527_CIR_CEN (1) +#define I82527_CLKOUT_SL1 (1<<5) +#define I82527_CLKOUT_SLO (1<<4) +#define I82527_BCR_COBY (1<<6) +#define I82527_BCR_POL (1<<5) +#define I82527_DCT1 (1<<3) +#define I82527_DCR1 (1<<1) +#define I82527_DCR0 (1) +#define I82527_BTR1_SPL (1<<7) +#define I82527_MSG_CTRL_MSGVAL (2<<6) +#define I82527_MSG_CTRL_MSGVAL_NC (3<<6) +#define I82527_MSG_CTRL_MSGVAL_SET (2<<6) +#define I82527_MSG_CTRL_MSGVAL_CLR (1<<6) +#define I82527_MSG_CTRL_TXIE (2<<4) +#define I82527_MSG_CTRL_TXIE_NC (3<<4) +#define I82527_MSG_CTRL_TXIE_SET (2<<4) +#define I82527_MSG_CTRL_TXIE_CLR (1<<4) +#define I82527_MSG_CTRL_RXIE (2<<2) +#define I82527_MSG_CTRL_RXIE_NC (3<<2) +#define I82527_MSG_CTRL_RXIE_SET (2<<2) +#define I82527_MSG_CTRL_RXIE_CLR (1<<2) +#define I82527_MSG_CTRL_INTPND (2) +#define I82527_MSG_CTRL_INTPND_NC (3) +#define I82527_MSG_CTRL_INTPND_SET (2) +#define I82527_MSG_CTRL_INTPND_CLR (1) +#define I82527_MSG_CTRL_RMTPND (2<<6) +#define I82527_MSG_CTRL_RMTPND_NC (3<<6) +#define I82527_MSG_CTRL_RMTPND_SET (2<<6) +#define I82527_MSG_CTRL_RMTPND_CLR (1<<6) +#define I82527_MSG_CTRL_TXRQ (2<<4) +#define I82527_MSG_CTRL_TXRQ_NC (3<<4) +#define I82527_MSG_CTRL_TXRQ_SET (2<<4) +#define I82527_MSG_CTRL_TXRQ_CLR (1<<4) +#define I82527_MSG_CTRL_MSGLST (2<<2) +#define I82527_MSG_CTRL_MSGLST_NC (3<<2) +#define I82527_MSG_CTRL_MSGLST_SET (2<<2) +#define I82527_MSG_CTRL_MSGLST_CLR (1<<2) +#define I82527_MSG_CTRL_CPUUPD (2<<2) +#define I82527_MSG_CTRL_CPUUPD_NC (3<<2) +#define I82527_MSG_CTRL_CPUUPD_SET (2<<2) +#define I82527_MSG_CTRL_CPUUPD_CLR (1<<2) +#define I82527_MSG_CTRL_NEWDAT (2) +#define I82527_MSG_CTRL_NEWDAT_NC (3) +#define I82527_MSG_CTRL_NEWDAT_SET (2) +#define I82527_MSG_CTRL_NEWDAT_CLR (1) +#define I82527_MSG_CFG_DIR (1<<3) +#define I82527_MSG_CFG_XTD (1<<2) + +extern i82527_t canbus0; +extern i82527_t canbus1; +extern i82527_t canbus2; + + +rtems_device_driver canbus_initialize(rtems_device_major_number, + rtems_device_minor_number, + void *); +rtems_device_driver canbus_open(rtems_device_major_number, + rtems_device_minor_number, + void *); +rtems_device_driver canbus_close(rtems_device_major_number, + rtems_device_minor_number, + void *); +rtems_device_driver canbus_read(rtems_device_major_number, + rtems_device_minor_number, + void *); +rtems_device_driver canbus_write(rtems_device_major_number, + rtems_device_minor_number, + void *); +rtems_device_driver canbus_control(rtems_device_major_number, + rtems_device_minor_number, + void *); + + +#define CANBUS_DRIVER_TABLE_ENTRY \ + { canbus_initialize, canbus_open, canbus_close, \ + canbus_read, canbus_write, canbus_control } + +#endif /* __CANBUS_H_ */ diff --git a/c/src/lib/libbsp/powerpc/eth_comm/include/coverhd.h b/c/src/lib/libbsp/powerpc/eth_comm/include/coverhd.h new file mode 100644 index 0000000000..9f0911fe8a --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/include/coverhd.h @@ -0,0 +1,115 @@ +/* coverhd.h + * + * This include file has defines to represent the overhead associated + * with calling a particular directive from C. These are used in the + * Timing Test Suite to ignore the overhead required to pass arguments + * to directives. On some CPUs and/or target boards, this overhead + * is significant and makes it difficult to distinguish internal + * RTEMS execution time from that used to call the directive. + * This file should be updated after running the C overhead timing + * test. Once this update has been performed, the RTEMS Time Test + * Suite should be rebuilt to account for these overhead times in the + * timing results. + * + * NOTE: If these are all zero, then the times reported include + * all calling overhead including passing of arguments. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef __COVERHD_h +#define __COVERHD_h + +#ifdef __cplusplus +extern "C" { +#endif + +#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0 +#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0 +#define CALLING_OVERHEAD_TASK_CREATE 0 +#define CALLING_OVERHEAD_TASK_IDENT 0 +#define CALLING_OVERHEAD_TASK_START 0 +#define CALLING_OVERHEAD_TASK_RESTART 0 +#define CALLING_OVERHEAD_TASK_DELETE 0 +#define CALLING_OVERHEAD_TASK_SUSPEND 0 +#define CALLING_OVERHEAD_TASK_RESUME 0 +#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0 +#define CALLING_OVERHEAD_TASK_MODE 0 +#define CALLING_OVERHEAD_TASK_GET_NOTE 0 +#define CALLING_OVERHEAD_TASK_SET_NOTE 0 +#define CALLING_OVERHEAD_TASK_WAKE_WHEN 2 +#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0 +#define CALLING_OVERHEAD_INTERRUPT_CATCH 0 +#define CALLING_OVERHEAD_CLOCK_GET 2 +#define CALLING_OVERHEAD_CLOCK_SET 2 +#define CALLING_OVERHEAD_CLOCK_TICK 0 + +#define CALLING_OVERHEAD_TIMER_CREATE 0 +#define CALLING_OVERHEAD_TIMER_IDENT 0 +#define CALLING_OVERHEAD_TIMER_DELETE 0 +#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0 +#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 2 +#define CALLING_OVERHEAD_TIMER_RESET 0 +#define CALLING_OVERHEAD_TIMER_CANCEL 0 +#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0 +#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 +#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 +#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 +#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0 + +#define CALLING_OVERHEAD_EVENT_SEND 0 +#define CALLING_OVERHEAD_EVENT_RECEIVE 0 +#define CALLING_OVERHEAD_SIGNAL_CATCH 0 +#define CALLING_OVERHEAD_SIGNAL_SEND 0 +#define CALLING_OVERHEAD_PARTITION_CREATE 0 +#define CALLING_OVERHEAD_PARTITION_IDENT 0 +#define CALLING_OVERHEAD_PARTITION_DELETE 0 +#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0 +#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0 +#define CALLING_OVERHEAD_REGION_CREATE 0 +#define CALLING_OVERHEAD_REGION_IDENT 0 +#define CALLING_OVERHEAD_REGION_DELETE 0 +#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0 +#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 +#define CALLING_OVERHEAD_PORT_CREATE 0 +#define CALLING_OVERHEAD_PORT_IDENT 0 +#define CALLING_OVERHEAD_PORT_DELETE 0 +#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 +#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0 + +#define CALLING_OVERHEAD_IO_INITIALIZE 0 +#define CALLING_OVERHEAD_IO_OPEN 0 +#define CALLING_OVERHEAD_IO_CLOSE 0 +#define CALLING_OVERHEAD_IO_READ 0 +#define CALLING_OVERHEAD_IO_WRITE 0 +#define CALLING_OVERHEAD_IO_CONTROL 0 +#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0 +#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0 + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/powerpc/eth_comm/include/info.h b/c/src/lib/libbsp/powerpc/eth_comm/include/info.h new file mode 100644 index 0000000000..881f962995 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/include/info.h @@ -0,0 +1,90 @@ +/* info.h - Defines board info block structure and macros for + * handling elements of struct for ethernet comm board + * + * Written by Jay Monkman 7/21/98 + * Copyright Frasca International, Inc 1998 + */ + +#ifndef __info_h__ +#define __info_h__ + +typedef struct BoardInfoBlock_ { + rtems_unsigned16 size; /* size of info block in bytes */ + rtems_unsigned8 eth_id[6]; /* ethernet id of ethernet interface */ + rtems_unsigned32 cpu_spd; /* cpu speed in Hz */ + rtems_unsigned32 flash_size; /* size of flash memory in bytes */ + rtems_unsigned32 ram_size; /* size of ram in bytes */ + rtems_unsigned32 version; /* version of firmare (x.y format) */ + rtems_unsigned32 if429; /* mask for arinc429 interface */ + rtems_unsigned32 ifcsdb; /* mask for csdb interface */ + rtems_unsigned16 if232; /* mask for rs232 interface */ + rtems_unsigned8 ifcan; /* mask for canbus interface */ + rtems_unsigned8 if568; /* mask for arinc568 interface */ + rtems_unsigned8 fpn[16]; /* Frasca part number in ASCII */ + rtems_unsigned16 rev; /* Board revision */ + rtems_unsigned32 ip_num; /* Board IP number */ + +} boardinfo_t; + +#define IFACE_ARINC429_TX0 0x00000001; +#define IFACE_ARINC429_RX0 0x00000002; +#define IFACE_ARINC429_TX1 0x00000004; +#define IFACE_ARINC429_RX1 0x00000008; +#define IFACE_ARINC429_TX2 0x00000010; +#define IFACE_ARINC429_RX2 0x00000020; +#define IFACE_ARINC429_TX3 0x00000040; +#define IFACE_ARINC429_RX3 0x00000080; +#define IFACE_ARINC429_TX4 0x00000100; +#define IFACE_ARINC429_RX4 0x00000200; +#define IFACE_ARINC429_TX5 0x00000400; +#define IFACE_ARINC429_RX5 0x00000800; +#define IFACE_ARINC429_TX6 0x00001000; +#define IFACE_ARINC429_RX6 0x00002000; +#define IFACE_ARINC429_TX7 0x00004000; +#define IFACE_ARINC429_RX7 0x00008000; + +#define IFACE_ARINC568_TX0 0x0001; +#define IFACE_ARINC568_RX0 0x0002; +#define IFACE_ARINC568_TX1 0x0004; +#define IFACE_ARINC568_RX1 0x0008; + +#define IFACE_CSDB_TX0 0x00000001; +#define IFACE_CSDB_RX0 0x00000002; +#define IFACE_CSDB_TX1 0x00000004; +#define IFACE_CSDB_RX1 0x00000008; +#define IFACE_CSDB_TX2 0x00000010; +#define IFACE_CSDB_RX2 0x00000020; +#define IFACE_CSDB_TX3 0x00000040; +#define IFACE_CSDB_RX3 0x00000080; +#define IFACE_CSDB_TX4 0x00000100; +#define IFACE_CSDB_RX4 0x00000200; +#define IFACE_CSDB_TX5 0x00000400; +#define IFACE_CSDB_RX5 0x00000800; +#define IFACE_CSDB_TX6 0x00001000; +#define IFACE_CSDB_RX6 0x00002000; +#define IFACE_CSDB_TX7 0x00004000; +#define IFACE_CSDB_RX7 0x00008000; +#define IFACE_CSDB_TX8 0x00010000; +#define IFACE_CSDB_RX8 0x00020000; + +#define IFACE_CAN_TX0 0x0001; +#define IFACE_CAN_RX0 0x0002; +#define IFACE_CAN_TX1 0x0004; +#define IFACE_CAN_RX1 0x0008; +#define IFACE_CAN_TX2 0x0010; +#define IFACE_CAN_RX2 0x0020; + +#define IFACE_RS232_TX0 0x0001; +#define IFACE_RS232_RX0 0x0002; +#define IFACE_RS232_TX1 0x0004; +#define IFACE_RS232_RX1 0x0008; +#define IFACE_RS232_TX2 0x0010; +#define IFACE_RS232_RX2 0x0020; +#define IFACE_RS232_TX3 0x0040; +#define IFACE_RS232_RX3 0x0080; +#define IFACE_RS232_TX4 0x0100; +#define IFACE_RS232_RX4 0x0200; + + + +#endif /* __info_h__*/ diff --git a/c/src/lib/libbsp/powerpc/eth_comm/network/Makefile.in b/c/src/lib/libbsp/powerpc/eth_comm/network/Makefile.in new file mode 100644 index 0000000000..59728b648d --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/network/Makefile.in @@ -0,0 +1,55 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +PGM=${ARCH}/network.rel + +# C source names, if any, go here -- minus the .c +C_PIECES=network +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +SRCS=$(C_FILES) $(H_FILES) +OBJS=$(C_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += -D_COMPILING_BSD_KERNEL_ -DKERNEL -DINET -DNFS \ + -DDIAGNOSTIC -DBOOTP_COMPAT +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile +install: all diff --git a/c/src/lib/libbsp/powerpc/eth_comm/network/README b/c/src/lib/libbsp/powerpc/eth_comm/network/README new file mode 100644 index 0000000000..8e14552641 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/network/README @@ -0,0 +1,294 @@ +# +# $Id$ +# + +# +# This package requires a version of GCC that supports the `-mcpu32' option. +# + +# +# Please send any comments, improvements, or bug reports to: +# W. Eric Norum +# Saskatchewan Accelerator Laboratory +# 107 North Road +# University of Saskatchewan +# Saskatoon, Saskatchewan, CANADA +# S7N 5C6 +# eric@skatter.usask.ca +# + +# +# This board support package works with several different versions of +# MC68360 systems. The choice of hardware is made at the final link-edit +# phase by setting the Makefile CLAGS_LD definition appropriately. +# +# Decisions made at compile time include: +# - If the CPU is a member of the 68040 family, the BSP is +# compiled for a generic 68040/68360 system as described +# in Chapter 9 of the MC68360 User's Manual. +# - If the preprocessor symbol M68360_ATLAS_HSB is defined, +# the BSP is compiled for an Atlas HSB card. +# - Otherwise, the BSP is compiled for a generic 68360 system +# as described in Chapter 9 of the MC68360 User's Manual. +# +# Decisions to be made a link-edit time are: +# - The size of the memory allocator heap. The default value is +# 64 kbytes. If the network package is used the heap +# should be at least 256 kbytes. If your network is large, or +# busy, the heap should be even larger. +# To choose a heap size of 256 kbytes, +# CFLAGS_LD += -Wl,--defsym -Wl,HeapSize=0x40000 + +BSP NAME: gen68360 or gen68360_040 +BOARD: Generic 68360 as described in Motorola MC68360 User's Manual +BOARD: Atlas Computer Equipment Inc. High Speed Bridge (HSB) +BOARD: Atlas Computer Equipment Inc. Advanced Communication Engine (ACE) +BOARD: Arnewsh SBC360 68040/68360 card +BUS: none +CPU FAMILY: Motorola CPU32+, Motorola 68040 +COPROCESSORS: none +MODE: not applicable + +DEBUG MONITOR: none (Hardware provides BDM) + +PERIPHERALS +=========== +TIMERS: PIT, Watchdog, 4 general purpose, 16 RISC + RESOLUTION: one microsecond +SERIAL PORTS: 4 SCC, 2 SMC, 1 SPI +REAL-TIME CLOCK: +DMA: Each serial port, 2 general purpose +VIDEO: none +SCSI: none +NETWORKING: Ethernet on SCC1. + +DRIVER INFORMATION +================== +CLOCK DRIVER: Programmable Interval Timer +IOSUPP DRIVER: Serial Management Controller 1 +SHMSUPP: none +TIMER DRIVER: Timer 1 + +STDIO +===== +PORT: SMC1 +ELECTRICAL: EIA-232 (if board supplies level shifter) +BAUD: 9600 +BITS PER CHARACTER: 8 +PARITY: None +STOP BITS: 1 + +NOTES +===== + +Board description +----------------- +clock rate: 25 MHz +bus width: 8-bit PROM, 32-bit DRAM +ROM: To 1 MByte, 180 nsec (3 wait states), chip select 0 +RAM: 1 to 16 MByte DRAM SIMM, 60 nsec (0 wait states), parity or nonparity + +Host System +----------- +OPENSTEP 4.2 (Intel and Motorola), Solaris 2.5, Linux 2.0.29 + +Verification (Standalone 68360) +------------------------------- +Single processor tests: Passed +Multi-processort tests: not applicable +Timing tests: + Context Switch + + context switch: self 10 + context switch: to another task 11 + context switch: no floating point contexts 40 + fp context switch: restore 1st FP task 41 + fp context switch: save initialized, restore initialized 14 + fp context switch: save idle, restore initialized 14 + fp context switch: save idle, restore idle 43 + + Task Manager + + rtems_task_create 133 + rtems_task_ident 351 + rtems_task_start 77 + rtems_task_restart: calling task 93 + rtems_task_restart: suspended task -- returns to caller 90 + rtems_task_restart: blocked task -- returns to caller 120 + rtems_task_restart: ready task -- returns to caller 92 + rtems_task_restart: suspended task -- preempts caller 121 + rtems_task_restart: blocked task -- preempts caller 143 + rtems_task_restart: ready task -- preempts caller 138 + rtems_task_delete: calling task 158 + rtems_task_delete: suspended task 129 + rtems_task_delete: blocked task 134 + rtems_task_delete: ready task 136 + rtems_task_suspend: calling task 71 + rtems_task_suspend: returns to caller 47 + rtems_task_resume: task readied -- returns to caller 48 + rtems_task_resume: task readied -- preempts caller 67 + rtems_task_set_priority: obtain current priority 36 + rtems_task_set_priority: returns to caller 65 + rtems_task_set_priority: preempts caller 102 + rtems_task_mode: obtain current mode 13 + rtems_task_mode: no reschedule 15 + rtems_task_mode: reschedule -- returns to caller 22 + rtems_task_mode: reschedule -- preempts caller 61 + rtems_task_get_note 38 + rtems_task_set_note 37 + rtems_task_wake_after: yield -- returns to caller 22 + rtems_task_wake_after: yields -- preempts caller 56 + rtems_task_wake_when 110 + + Interrupt Manager + + interrupt entry overhead: returns to nested interrupt 8 + interrupt entry overhead: returns to interrupted task 8 + interrupt entry overhead: returns to preempting task 8 + interrupt exit overhead: returns to nested interrupt 7 + interrupt exit overhead: returns to interrupted task 8 + interrupt exit overhead: returns to preempting task 52 + + Clock Manager + + rtems_clock_set 82 + rtems_clock_get 2 + rtems_clock_tick 15 + + Timer Manager + + rtems_timer_create 33 + rtems_timer_ident 343 + rtems_timer_delete: inactive 47 + rtems_timer_delete: active 50 + rtems_timer_fire_after: inactive 59 + rtems_timer_fire_after: active 63 + rtems_timer_fire_when: inactive 83 + rtems_timer_fire_when: active 83 + rtems_timer_reset: inactive 55 + rtems_timer_reset: active 58 + rtems_timer_cancel: inactive 35 + rtems_timer_cancel: active 38 + + Semaphore Manager + + rtems_semaphore_create 62 + rtems_semaphore_ident 368 + rtems_semaphore_delete 61 + rtems_semaphore_obtain: available 42 + rtems_semaphore_obtain: not available -- NO_WAIT 42 + rtems_semaphore_obtain: not available -- caller blocks 105 + rtems_semaphore_release: no waiting tasks 46 + rtems_semaphore_release: task readied -- returns to caller 64 + rtems_semaphore_release: task readied -- preempts caller 84 + + Message Queue Manager + + rtems_message_queue_create 240 + rtems_message_queue_ident 342 + rtems_message_queue_delete 79 + rtems_message_queue_send: no waiting tasks 93 + rtems_message_queue_send: task readied -- returns to caller 96 + rtems_message_queue_send: task readied -- preempts caller 116 + rtems_message_queue_urgent: no waiting tasks 93 + rtems_message_queue_urgent: task readied -- returns to caller 97 + rtems_message_queue_urgent: task readied -- preempts caller 117 + rtems_message_queue_broadcast: no waiting tasks 54 + rtems_message_queue_broadcast: task readied -- returns to caller 106 + rtems_message_queue_broadcast: task readied -- preempts caller 126 + rtems_message_queue_receive: available 79 + rtems_message_queue_receive: not available -- NO_WAIT 48 + rtems_message_queue_receive: not available -- caller blocks 111 + rtems_message_queue_flush: no messages flushed 35 + rtems_message_queue_flush: messages flushed 44 + + Event Manager + + rtems_event_send: no task readied 30 + rtems_event_send: task readied -- returns to caller 59 + rtems_event_send: task readied -- preempts caller 81 + rtems_event_receive: obtain current events 1 + rtems_event_receive: available 34 + rtems_event_receive: not available -- NO_WAIT 31 + rtems_event_receive: not available -- caller blocks 84 + + Signal Manager + + rtems_signal_catch 24 + rtems_signal_send: returns to caller 42 + rtems_signal_send: signal to self 47 + exit ASR overhead: returns to calling task 33 + exit ASR overhead: returns to preempting task 58 + + Partition Manager + + rtems_partition_create 78 + rtems_partition_ident 342 + rtems_partition_delete 46 + rtems_partition_get_buffer: available 40 + rtems_partition_get_buffer: not available 39 + rtems_partition_return_buffer 47 + + Region Manager + + rtems_region_create 65 + rtems_region_ident 349 + rtems_region_delete 45 + rtems_region_get_segment: available 55 + rtems_region_get_segment: not available -- NO_WAIT 52 + rtems_region_get_segment: not available -- caller blocks 119 + rtems_region_return_segment: no waiting tasks 57 + rtems_region_return_segment: task readied -- returns to caller 106 + rtems_region_return_segment: task readied -- preempts caller 127 + + Dual-Ported Memory Manager + + rtems_port_create 40 + rtems_port_ident 342 + rtems_port_delete 44 + rtems_port_internal_to_external 32 + rtems_port_external_to_internal 32 + + IO Manager + + rtems_io_initialize 4 + rtems_io_open 1 + rtems_io_close 1 + rtems_io_read 1 + rtems_io_write 1 + rtems_io_control 1 + + Rate Monotonic Manager + + rtems_rate_monotonic_create 39 + rtems_rate_monotonic_ident 343 + rtems_rate_monotonic_cancel 43 + rtems_rate_monotonic_delete: active 54 + rtems_rate_monotonic_delete: inactive 52 + rtems_rate_monotonic_period: obtain status 37 + rtems_rate_monotonic_period: initiate period -- returns to caller 58 + rtems_rate_monotonic_period: conclude periods -- caller blocks 75 + +Porting +------- +This board support package is written for a 68360 system similar to that +described in chapter 9 of the Motorola MC68360 Quad Integrated Communication +Processor Users' Manual. The salient features of this hardware are: + + 25 MHz external clock + DRAM address multiplexing provided by 68360 + 8-bit 180nsec PROM to CS0* + 4 MBytes of 60 nsec parity DRAM (1Mx36) to RAS1*/CAS1* + Console serial port on SMC1 + Ethernet interface on SCC1 + +The board support package has been tested with: + A home-built 68360 board + An ACE360A and an HSB board produced by: + Atlas Computer Equipment + 703 Colina Lane + Santa Barbara, CA 93103 + A 68040/68360 board (SBC360) produced by: + Arnewsh Inc. + P.O. Box 270352 + Fort Collins, CO 80527-0352 diff --git a/c/src/lib/libbsp/powerpc/eth_comm/network/network.c b/c/src/lib/libbsp/powerpc/eth_comm/network/network.c new file mode 100644 index 0000000000..f9211c45b0 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/network/network.c @@ -0,0 +1,1620 @@ +/* + * RTEMS/KA9Q driver for MPC860 SCC1 Ethernet + * + * Modified for MPC860 by Jay Monkman (jmonkman@frasca.com) + * + * This supports ethernet on either SCC1 or the FEC of the MPC860T. + * Right now, we only do 10 Mbps, even with the FEC. The function + * rtems_m860_enet_driver_attach determines which one to use. Currently, + * only one may be used at a time. + * + * W. Eric Norum + * Saskatchewan Accelerator Laboratory + * University of Saskatchewan + * Saskatoon, Saskatchewan, CANADA + * eric@skatter.usask.ca + * + * $Id$ + */ +#include <bsp.h> +#include <mpc860.h> +#include <stdio.h> +#include <rtems/error.h> +#include <rtems/rtems_bsdnet.h> + +#include <sys/param.h> +#include <sys/mbuf.h> +#include <sys/socket.h> +#include <sys/sockio.h> + +#include <net/if.h> + +#include <netinet/in.h> +#include <netinet/if_ether.h> + +/* + * Number of interfaces supported by this driver + */ +#define NIFACES 1 + +/* + * Default number of buffer descriptors set aside for this driver. + * The number of transmit buffer descriptors has to be quite large + * since a single frame often uses four or more buffer descriptors. + */ +#define RX_BUF_COUNT 32 +#define TX_BUF_COUNT 8 +#define TX_BD_PER_BUF 4 + +/* + * RTEMS event used by interrupt handler to signal daemons. + * This must *not* be the same event used by the KA9Q task synchronization. + */ +#define INTERRUPT_EVENT RTEMS_EVENT_1 + +/* + * RTEMS event used to start transmit daemon. + * This must not be the same as INTERRUPT_EVENT. + */ +#define START_TRANSMIT_EVENT RTEMS_EVENT_2 + +/* + * Receive buffer size -- Allow for a full ethernet packet plus a pointer + */ +#define RBUF_SIZE 1520 + +#if (MCLBYTES < RBUF_SIZE) +# error "Driver must have MCLBYTES > RBUF_SIZE" +#endif + +/* + * Per-device data + */ +struct m860_enet_struct { + struct arpcom arpcom; + struct mbuf **rxMbuf; + struct mbuf **txMbuf; + int acceptBroadcast; + int rxBdCount; + int txBdCount; + int txBdHead; + int txBdTail; + int txBdActiveCount; + m860BufferDescriptor_t *rxBdBase; + m860BufferDescriptor_t *txBdBase; + rtems_id rxDaemonTid; + rtems_id txDaemonTid; + + /* + * Statistics + */ + unsigned long rxInterrupts; + unsigned long rxNotFirst; + unsigned long rxNotLast; + unsigned long rxGiant; + unsigned long rxNonOctet; + unsigned long rxRunt; + unsigned long rxBadCRC; + unsigned long rxOverrun; + unsigned long rxCollision; + + unsigned long txInterrupts; + unsigned long txDeferred; + unsigned long txHeartbeat; + unsigned long txLateCollision; + unsigned long txRetryLimit; + unsigned long txUnderrun; + unsigned long txLostCarrier; + unsigned long txRawWait; +}; +static struct m860_enet_struct enet_driver[NIFACES]; + +/* + * SCC1 interrupt handler + */ +static rtems_isr +m860_scc1_interrupt_handler (rtems_vector_number v) +{ + /* + * Frame received? + */ + if ((m860.scc1.sccm & 0x8) && (m860.scc1.scce & 0x8)) { + m860.scc1.scce = 0x8; + /* I don't think the next line is needed. It was in + * the 68360 stuff, though. + * m860.scc1.sccm &= ~0x8; + */ + enet_driver[0].rxInterrupts++; + rtems_event_send (enet_driver[0].rxDaemonTid, INTERRUPT_EVENT); + } + + /* + * Buffer transmitted or transmitter error? + */ + if ((m860.scc1.sccm & 0x12) && (m860.scc1.scce & 0x12)) { + m860.scc1.scce = 0x12; + /* I don't think the next line is needed. It was in + * the 68360 stuff, though. + * m860.scc1.sccm &= ~0x12; + */ + enet_driver[0].txInterrupts++; + rtems_event_send (enet_driver[0].txDaemonTid, INTERRUPT_EVENT); + } + m860.cisr = 1UL << 30; /* Clear SCC1 interrupt-in-service bit */ +} + +/* + * FEC interrupt handler + */ +static rtems_isr +m860_fec_interrupt_handler (rtems_vector_number v) +{ + /* + * Frame received? + */ + if (m860.fec.ievent & M860_FEC_IEVENT_RFINT) { + m860.fec.ievent = M860_FEC_IEVENT_RFINT; + enet_driver[0].rxInterrupts++; + rtems_event_send (enet_driver[0].rxDaemonTid, INTERRUPT_EVENT); + } + + /* + * Buffer transmitted or transmitter error? + */ + if (m860.fec.ievent & M860_FEC_IEVENT_TFINT) { + m860.fec.ievent = M860_FEC_IEVENT_TFINT; + enet_driver[0].txInterrupts++; + rtems_event_send (enet_driver[0].txDaemonTid, INTERRUPT_EVENT); + } +} + +/* + * Initialize the ethernet hardware + */ +static void +m860_scc_initialize_hardware (struct m860_enet_struct *sc) +{ + int i; + unsigned char *hwaddr; + rtems_status_code status; + rtems_isr_entry old_handler; + + /* + * Configure port A CLK1, CLK2, TXD1 and RXD1 pins + */ + m860.papar |= 0x303; + m860.padir &= ~0x303; + m860.paodr &= ~0x303; + + /* + * Configure port C CTS1* and CD1* pins, and PC4-PC7 + * + */ + m860.pcpar &= ~0x30; + m860.pcdir |= 0x0f00; + m860.pcdir &= ~0x30; + m860.pcso |= 0x30; + m860.pcdat &= ~0x0f00; /* Clear LOOP */ + m860.pcdat |= 0x0700; /* Set FULDL, TPSQEL, TPAPCE */ + + /* + * Connect CLK1 and CLK2 to SCC1 + */ + m860.sicr &= ~0xFF; + m860.sicr |= (5 << 3) | 4; + + /* + * Initialize SDMA configuration register + */ + m860.sdcr = 1; + + /* + * Allocate mbuf pointers + */ + sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, + M_MBUF, M_NOWAIT); + sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, + M_MBUF, M_NOWAIT); + if (!sc->rxMbuf || !sc->txMbuf) + rtems_panic ("No memory for mbuf pointers"); + + /* + * Set receiver and transmitter buffer descriptor bases + */ + sc->rxBdBase = M860AllocateBufferDescriptors(sc->rxBdCount); + sc->txBdBase = M860AllocateBufferDescriptors(sc->txBdCount); + m860.scc1p.rbase = (char *)sc->rxBdBase - (char *)&m860; + m860.scc1p.tbase = (char *)sc->txBdBase - (char *)&m860; + + /* + * Send "Init parameters" command + */ + M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC1); + + /* + * Set receive and transmit function codes + */ + m860.scc1p.rfcr = M860_RFCR_MOT | M860_RFCR_DMA_SPACE(0); + m860.scc1p.tfcr = M860_TFCR_MOT | M860_TFCR_DMA_SPACE(0); + + /* + * Set maximum receive buffer length + */ + m860.scc1p.mrblr = RBUF_SIZE; + + /* + * Set CRC parameters + */ + m860.scc1p.un.ethernet.c_pres = 0xFFFFFFFF; + m860.scc1p.un.ethernet.c_mask = 0xDEBB20E3; + + /* + * Clear diagnostic counters + */ + m860.scc1p.un.ethernet.crcec = 0; + m860.scc1p.un.ethernet.alec = 0; + m860.scc1p.un.ethernet.disfc = 0; + + /* + * Set pad value + */ + m860.scc1p.un.ethernet.pads = 0x8888; + + /* + * Set retry limit + */ + m860.scc1p.un.ethernet.ret_lim = 15; + + /* + * Set maximum and minimum frame length + */ + m860.scc1p.un.ethernet.mflr = 1518; + m860.scc1p.un.ethernet.minflr = 64; + m860.scc1p.un.ethernet.maxd1 = RBUF_SIZE; + m860.scc1p.un.ethernet.maxd2 = RBUF_SIZE; + + /* + * Clear group address hash table + */ + m860.scc1p.un.ethernet.gaddr1 = 0; + m860.scc1p.un.ethernet.gaddr2 = 0; + m860.scc1p.un.ethernet.gaddr3 = 0; + m860.scc1p.un.ethernet.gaddr4 = 0; + + /* + * Set our physical address + */ + hwaddr = sc->arpcom.ac_enaddr; + + m860.scc1p.un.ethernet.paddr_h = (hwaddr[5] << 8) | hwaddr[4]; + m860.scc1p.un.ethernet.paddr_m = (hwaddr[3] << 8) | hwaddr[2]; + m860.scc1p.un.ethernet.paddr_l = (hwaddr[1] << 8) | hwaddr[0]; + + /* + * Aggressive retry + */ + m860.scc1p.un.ethernet.p_per = 0; + + /* + * Clear individual address hash table + */ + m860.scc1p.un.ethernet.iaddr1 = 0; + m860.scc1p.un.ethernet.iaddr2 = 0; + m860.scc1p.un.ethernet.iaddr3 = 0; + m860.scc1p.un.ethernet.iaddr4 = 0; + + /* + * Clear temp address + */ + m860.scc1p.un.ethernet.taddr_l = 0; + m860.scc1p.un.ethernet.taddr_m = 0; + m860.scc1p.un.ethernet.taddr_h = 0; + + /* + * Set up receive buffer descriptors + */ + for (i = 0 ; i < sc->rxBdCount ; i++) { + (sc->rxBdBase + i)->status = 0; + } + + /* + * Set up transmit buffer descriptors + */ + for (i = 0 ; i < sc->txBdCount ; i++) { + (sc->txBdBase + i)->status = 0; + sc->txMbuf[i] = NULL; + } + sc->txBdHead = sc->txBdTail = 0; + sc->txBdActiveCount = 0; + + /* + * Clear any outstanding events + */ + m860.scc1.scce = 0xFFFF; + + /* + * Set up interrupts + */ + status = rtems_interrupt_catch (m860_scc1_interrupt_handler, + PPC_IRQ_CPM_SCC1, + &old_handler); + if (status != RTEMS_SUCCESSFUL) { + rtems_panic ("Can't attach M860 SCC1 interrupt handler: %s\n", + rtems_status_text (status)); + } + m860.scc1.sccm = 0; /* No interrupts unmasked till necessary */ + m860.cimr |= (1UL << 30); /* Enable SCC1 interrupt */ + + /* + * Set up General SCC Mode Register + * Ethernet configuration + */ + m860.scc1.gsmr_h = 0x0; + m860.scc1.gsmr_l = 0x1088000c; + + /* + * Set up data synchronization register + * Ethernet synchronization pattern + */ + m860.scc1.dsr = 0xd555; + + /* + * Set up protocol-specific mode register + * No Heartbeat check + * No force collision + * Discard short frames + * Individual address mode + * Ethernet CRC + * Not promisuous + * Ignore/accept broadcast packets as specified + * Normal backoff timer + * No loopback + * No input sample at end of frame + * 64-byte limit for late collision + * Wait 22 bits before looking for start of frame delimiter + * Disable full-duplex operation + */ + m860.scc1.psmr = 0x080A | (sc->acceptBroadcast ? 0 : 0x100); + + /* + * Enable the TENA (RTS1*) pin + */ + m860.pcpar |= 0x1; + m860.pcdir &= ~0x1; + + + /* + * Set up interrupts + * FIXME: DANGER: WARNING: + * CICR and SIMASK must be set in any module that uses + * the CPM. Currently those are console-generic.c and + * network.c. If the registers are not set the same + * in both places, strange things may happen. + * If they are only set in one place, then an application + * that used the other module won't work correctly. + * Put this comment in each module that sets these 2 registers + */ + m860.cicr = 0x00e43e80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, + SCdP=SCC4, IRL=1, HP=SCC1, IEN=1 */ + m860.simask |= M860_SIMASK_LVM1; + + /* + * Enable receiver and transmitter + */ + m860.scc1.gsmr_l = 0x1088003c; +} + +static void +m860_fec_initialize_hardware (struct m860_enet_struct *sc) +{ + int i; + unsigned char *hwaddr; + rtems_status_code status; + rtems_isr_entry old_handler; + + /* + * Issue reset to FEC + */ + m860.fec.ecntrl=0x1; + + /* + * Put ethernet transciever in reset + */ + m860.pgcra |= 0x80; + + /* + * Configure I/O ports + */ + m860.pdpar = 0x1fff; + m860.pddir = 0x1c58; + + /* + * Take ethernet transciever out of reset + */ + m860.pgcra &= ~0x80; + + + /* + * Set SIU interrupt level to LVL2 + * + */ + m860.fec.ivec = 0x02 << 29; + + /* + * Set the TX and RX fifo sizes. For now, we'll split it evenly + */ + /* If you uncomment these, the FEC will not work right. + m860.fec.r_fstart = ((m860.fec.r_bound & 0x3ff) >> 2) & 0x3ff; + m860.fec.x_fstart = 0; + */ + + /* + * Set our physical address + */ + hwaddr = sc->arpcom.ac_enaddr; + + m860.fec.addr_low = (hwaddr[0] << 24) | (hwaddr[1] << 16) | + (hwaddr[2] << 8) | (hwaddr[3] << 0); + m860.fec.addr_high = (hwaddr[4] << 24) | (hwaddr[5] << 16); + + /* + * Clear the hash table + */ + m860.fec.hash_table_high = 0; + m860.fec.hash_table_low = 0; + + /* + * Set up receive buffer size + */ + m860.fec.r_buf_size = 0x5f0; /* set to 1520 */ + + /* + * Allocate mbuf pointers + */ + sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, + M_MBUF, M_NOWAIT); + sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, + M_MBUF, M_NOWAIT); + if (!sc->rxMbuf || !sc->txMbuf) + rtems_panic ("No memory for mbuf pointers"); + + /* + * Set receiver and transmitter buffer descriptor bases + */ + sc->rxBdBase = M860AllocateBufferDescriptors(sc->rxBdCount); + sc->txBdBase = M860AllocateBufferDescriptors(sc->txBdCount); + m860.fec.r_des_start = (int)sc->rxBdBase; + m860.fec.x_des_start = (int)sc->txBdBase; + + /* + * Set up Receive Control Register: + * Not promiscuous mode + * MII mode + * Half duplex + * No loopback + */ + m860.fec.r_cntrl = 0x00000006; + + /* + * Set up Transmit Control Register: + * Half duplex + * No heartbeat + */ + m860.fec.x_cntrl = 0x00000000; + + /* + * Set up DMA function code: + * Big-endian + * DMA functino code = 0 + */ + m860.fec.fun_code = 0x78000000; + + /* + * Initialize SDMA configuration register + * SDMA ignores FRZ + * FEC not aggressive + * FEC arbitration ID = 0 => U-bus arbitration = 6 + * RISC arbitration ID = 1 => U-bus arbitration = 5 + */ + m860.sdcr = 1; + + /* + * Set MII speed to 2.5 MHz for 25 Mhz system clock + */ + m860.fec.mii_speed = 0x0a; + m860.fec.mii_data = 0x58021000; + + /* + * Set up receive buffer descriptors + */ + for (i = 0 ; i < sc->rxBdCount ; i++) + (sc->rxBdBase + i)->status = 0; + + /* + * Set up transmit buffer descriptors + */ + for (i = 0 ; i < sc->txBdCount ; i++) { + (sc->txBdBase + i)->status = 0; + sc->txMbuf[i] = NULL; + } + sc->txBdHead = sc->txBdTail = 0; + sc->txBdActiveCount = 0; + + + + /* + * Mask all FEC interrupts and clear events + */ + m860.fec.imask = M860_FEC_IEVENT_TFINT | + M860_FEC_IEVENT_RFINT; + m860.fec.ievent = ~0; + + /* + * Set up interrupts + */ + status = rtems_interrupt_catch (m860_fec_interrupt_handler, + PPC_IRQ_LVL2, + &old_handler); + if (status != RTEMS_SUCCESSFUL) + rtems_panic ("Can't attach M860 FEC interrupt handler: %s\n", + rtems_status_text (status)); + + m860.simask |= M860_SIMASK_LVM2; + +} + + +/* + * Soak up buffer descriptors that have been sent + * Note that a buffer descriptor can't be retired as soon as it becomes + * ready. The MC68360 Errata (May 96) says that, "If an Ethernet frame is + * made up of multiple buffers, the user should not reuse the first buffer + * descriptor until the last buffer descriptor of the frame has had its + * ready bit cleared by the CPM". + */ +static void +m860Enet_retire_tx_bd (struct m860_enet_struct *sc) +{ + rtems_unsigned16 status; + int i; + int nRetired; + struct mbuf *m, *n; + + i = sc->txBdTail; + nRetired = 0; + while ((sc->txBdActiveCount != 0) + && (((status = (sc->txBdBase + i)->status) & M860_BD_READY) == 0)) { + /* + * See if anything went wrong + */ + if (status & (M860_BD_DEFER | + M860_BD_HEARTBEAT | + M860_BD_LATE_COLLISION | + M860_BD_RETRY_LIMIT | + M860_BD_UNDERRUN | + M860_BD_CARRIER_LOST)) { + /* + * Check for errors which stop the transmitter. + */ + if (status & (M860_BD_LATE_COLLISION | + M860_BD_RETRY_LIMIT | + M860_BD_UNDERRUN)) { + if (status & M860_BD_LATE_COLLISION) + enet_driver[0].txLateCollision++; + if (status & M860_BD_RETRY_LIMIT) + enet_driver[0].txRetryLimit++; + if (status & M860_BD_UNDERRUN) + enet_driver[0].txUnderrun++; + + /* + * Restart the transmitter + */ + /* FIXME: this should get executed only if using the SCC */ + M860ExecuteRISC (M860_CR_OP_RESTART_TX | M860_CR_CHAN_SCC1); + } + if (status & M860_BD_DEFER) + enet_driver[0].txDeferred++; + if (status & M860_BD_HEARTBEAT) + enet_driver[0].txHeartbeat++; + if (status & M860_BD_CARRIER_LOST) + enet_driver[0].txLostCarrier++; + } + nRetired++; + if (status & M860_BD_LAST) { + /* + * A full frame has been transmitted. + * Free all the associated buffer descriptors. + */ + sc->txBdActiveCount -= nRetired; + while (nRetired) { + nRetired--; + m = sc->txMbuf[sc->txBdTail]; + MFREE (m, n); + if (++sc->txBdTail == sc->txBdCount) + sc->txBdTail = 0; + } + } + if (++i == sc->txBdCount) + i = 0; + } +} + +/* + * reader task + */ +static void +scc_rxDaemon (void *arg) +{ + struct m860_enet_struct *sc = (struct m860_enet_struct *)arg; + struct ifnet *ifp = &sc->arpcom.ac_if; + struct mbuf *m; + rtems_unsigned16 status; + m860BufferDescriptor_t *rxBd; + int rxBdIndex; + + /* + * Allocate space for incoming packets and start reception + */ + for (rxBdIndex = 0 ; ;) { + rxBd = sc->rxBdBase + rxBdIndex; + MGETHDR (m, M_WAIT, MT_DATA); + MCLGET (m, M_WAIT); + m->m_pkthdr.rcvif = ifp; + sc->rxMbuf[rxBdIndex] = m; + rxBd->buffer = mtod (m, void *); + rxBd->status = M860_BD_EMPTY | M860_BD_INTERRUPT; + if (++rxBdIndex == sc->rxBdCount) { + rxBd->status |= M860_BD_WRAP; + break; + } + } + + /* + * Input packet handling loop + */ + rxBdIndex = 0; + for (;;) { + rxBd = sc->rxBdBase + rxBdIndex; + + /* + * Wait for packet if there's not one ready + */ + if ((status = rxBd->status) & M860_BD_EMPTY) { + /* + * Clear old events + */ + m860.scc1.scce = 0x8; + + /* + * Wait for packet + * Note that the buffer descriptor is checked + * *before* the event wait -- this catches the + * possibility that a packet arrived between the + * `if' above, and the clearing of the event register. + */ + while ((status = rxBd->status) & M860_BD_EMPTY) { + rtems_event_set events; + + /* + * Unmask RXF (Full frame received) event + */ + m860.scc1.sccm |= 0x8; + + rtems_bsdnet_event_receive (INTERRUPT_EVENT, + RTEMS_WAIT|RTEMS_EVENT_ANY, + RTEMS_NO_TIMEOUT, + &events); + } + } + + /* + * Check that packet is valid + */ + if ((status & (M860_BD_LAST | + M860_BD_FIRST_IN_FRAME | + M860_BD_LONG | + M860_BD_NONALIGNED | + M860_BD_SHORT | + M860_BD_CRC_ERROR | + M860_BD_OVERRUN | + M860_BD_COLLISION)) == + (M860_BD_LAST | + M860_BD_FIRST_IN_FRAME)) { + /* + * Pass the packet up the chain. + * FIXME: Packet filtering hook could be done here. + */ + struct ether_header *eh; + + m = sc->rxMbuf[rxBdIndex]; + m->m_len = m->m_pkthdr.len = rxBd->length - + sizeof(rtems_unsigned32) - + sizeof(struct ether_header); + eh = mtod (m, struct ether_header *); + m->m_data += sizeof(struct ether_header); + ether_input (ifp, eh, m); + + /* + * Allocate a new mbuf + */ + MGETHDR (m, M_WAIT, MT_DATA); + MCLGET (m, M_WAIT); + m->m_pkthdr.rcvif = ifp; + sc->rxMbuf[rxBdIndex] = m; + rxBd->buffer = mtod (m, void *); + } + else { + /* + * Something went wrong with the reception + */ + if (!(status & M860_BD_LAST)) + sc->rxNotLast++; + if (!(status & M860_BD_FIRST_IN_FRAME)) + sc->rxNotFirst++; + if (status & M860_BD_LONG) + sc->rxGiant++; + if (status & M860_BD_NONALIGNED) + sc->rxNonOctet++; + if (status & M860_BD_SHORT) + sc->rxRunt++; + if (status & M860_BD_CRC_ERROR) + sc->rxBadCRC++; + if (status & M860_BD_OVERRUN) + sc->rxOverrun++; + if (status & M860_BD_COLLISION) + sc->rxCollision++; + } + + /* + * Reenable the buffer descriptor + */ + rxBd->status = (status & (M860_BD_WRAP | M860_BD_INTERRUPT)) | + M860_BD_EMPTY; + + /* + * Move to next buffer descriptor + */ + if (++rxBdIndex == sc->rxBdCount) + rxBdIndex = 0; + } +} + +static void +fec_rxDaemon (void *arg) +{ + struct m860_enet_struct *sc = (struct m860_enet_struct *)arg; + struct ifnet *ifp = &sc->arpcom.ac_if; + struct mbuf *m; + rtems_unsigned16 status; + m860BufferDescriptor_t *rxBd; + int rxBdIndex; + + /* + * Allocate space for incoming packets and start reception + */ + for (rxBdIndex = 0 ; ;) { + rxBd = sc->rxBdBase + rxBdIndex; + MGETHDR (m, M_WAIT, MT_DATA); + MCLGET (m, M_WAIT); + m->m_pkthdr.rcvif = ifp; + sc->rxMbuf[rxBdIndex] = m; + rxBd->buffer = mtod (m, void *); + rxBd->status = M860_BD_EMPTY; + m860.fec.r_des_active = 0x1000000; + if (++rxBdIndex == sc->rxBdCount) { + rxBd->status |= M860_BD_WRAP; + break; + } + } + + /* + * Input packet handling loop + */ + rxBdIndex = 0; + for (;;) { + rxBd = sc->rxBdBase + rxBdIndex; + + /* + * Wait for packet if there's not one ready + */ + if ((status = rxBd->status) & M860_BD_EMPTY) { + /* + * Clear old events + */ + m860.fec.ievent = M860_FEC_IEVENT_RFINT; + + /* + * Wait for packet + * Note that the buffer descriptor is checked + * *before* the event wait -- this catches the + * possibility that a packet arrived between the + * `if' above, and the clearing of the event register. + */ + while ((status = rxBd->status) & M860_BD_EMPTY) { + rtems_event_set events; + + /* + * Unmask RXF (Full frame received) event + */ + m860.fec.ievent |= M860_FEC_IEVENT_RFINT; + + rtems_bsdnet_event_receive (INTERRUPT_EVENT, + RTEMS_WAIT|RTEMS_EVENT_ANY, + RTEMS_NO_TIMEOUT, + &events); + } + } + + /* + * Check that packet is valid + */ + if (status & M860_BD_LAST) { + /* + * Pass the packet up the chain. + * FIXME: Packet filtering hook could be done here. + */ + struct ether_header *eh; + + m = sc->rxMbuf[rxBdIndex]; + m->m_len = m->m_pkthdr.len = rxBd->length - + sizeof(rtems_unsigned32) - + sizeof(struct ether_header); + eh = mtod (m, struct ether_header *); + m->m_data += sizeof(struct ether_header); + ether_input (ifp, eh, m); + + /* + * Allocate a new mbuf + */ + MGETHDR (m, M_WAIT, MT_DATA); + MCLGET (m, M_WAIT); + m->m_pkthdr.rcvif = ifp; + sc->rxMbuf[rxBdIndex] = m; + rxBd->buffer = mtod (m, void *); + } + else { + /* + * Something went wrong with the reception + */ + if (!(status & M860_BD_LAST)) + sc->rxNotLast++; + if (status & M860_BD_LONG) + sc->rxGiant++; + if (status & M860_BD_NONALIGNED) + sc->rxNonOctet++; + if (status & M860_BD_SHORT) + sc->rxRunt++; + if (status & M860_BD_CRC_ERROR) + sc->rxBadCRC++; + if (status & M860_BD_OVERRUN) + sc->rxOverrun++; + if (status & M860_BD_COLLISION) + sc->rxCollision++; + } + /* + * Reenable the buffer descriptor + */ + rxBd->status = (status & M860_BD_WRAP) | + M860_BD_EMPTY; + m860.fec.r_des_active = 0x1000000; + /* + * Move to next buffer descriptor + */ + if (++rxBdIndex == sc->rxBdCount) + rxBdIndex = 0; + } +} + +static void +scc_sendpacket (struct ifnet *ifp, struct mbuf *m) +{ + struct m860_enet_struct *sc = ifp->if_softc; + volatile m860BufferDescriptor_t *firstTxBd, *txBd; + struct mbuf *l = NULL; + rtems_unsigned16 status; + int nAdded; + + /* + * Free up buffer descriptors + */ + m860Enet_retire_tx_bd (sc); + + /* + * Set up the transmit buffer descriptors. + * No need to pad out short packets since the + * hardware takes care of that automatically. + * No need to copy the packet to a contiguous buffer + * since the hardware is capable of scatter/gather DMA. + */ + nAdded = 0; + txBd = firstTxBd = sc->txBdBase + sc->txBdHead; + for (;;) { + /* + * Wait for buffer descriptor to become available. + */ + if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { + /* + * Clear old events + */ + m860.scc1.scce = 0x12; + + /* + * Wait for buffer descriptor to become available. + * Note that the buffer descriptors are checked + * *before* * entering the wait loop -- this catches + * the possibility that a buffer descriptor became + * available between the `if' above, and the clearing + * of the event register. + * This is to catch the case where the transmitter + * stops in the middle of a frame -- and only the + * last buffer descriptor in a frame can generate + * an interrupt. + */ + m860Enet_retire_tx_bd (sc); + while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { + rtems_event_set events; + + /* + * Unmask TXB (buffer transmitted) and + * TXE (transmitter error) events. + */ + m860.scc1.sccm |= 0x12; + rtems_bsdnet_event_receive (INTERRUPT_EVENT, + RTEMS_WAIT|RTEMS_EVENT_ANY, + RTEMS_NO_TIMEOUT, + &events); + m860Enet_retire_tx_bd (sc); + } + } + + /* + * Don't set the READY flag till the + * whole packet has been readied. + */ + status = nAdded ? M860_BD_READY : 0; + + /* + * FIXME: Why not deal with empty mbufs at at higher level? + * The IP fragmentation routine in ip_output + * can produce packet fragments with zero length. + * I think that ip_output should be changed to get + * rid of these zero-length mbufs, but for now, + * I'll deal with them here. + */ + if (m->m_len) { + /* + * Fill in the buffer descriptor + */ + txBd->buffer = mtod (m, void *); + txBd->length = m->m_len; + sc->txMbuf[sc->txBdHead] = m; + nAdded++; + if (++sc->txBdHead == sc->txBdCount) { + status |= M860_BD_WRAP; + sc->txBdHead = 0; + } + l = m; + m = m->m_next; + } + else { + /* + * Just toss empty mbufs + */ + struct mbuf *n; + MFREE (m, n); + m = n; + if (l != NULL) + l->m_next = m; + } + + /* + * Set the transmit buffer status. + * Break out of the loop if this mbuf is the last in the frame. + */ + if (m == NULL) { + if (nAdded) { + status |= M860_BD_PAD | M860_BD_LAST | M860_BD_TX_CRC | M860_BD_INTERRUPT; + txBd->status = status; + firstTxBd->status |= M860_BD_READY; + sc->txBdActiveCount += nAdded; + } + break; + } + txBd->status = status; + txBd = sc->txBdBase + sc->txBdHead; + } +} + +static void +fec_sendpacket (struct ifnet *ifp, struct mbuf *m) +{ + struct m860_enet_struct *sc = ifp->if_softc; + volatile m860BufferDescriptor_t *firstTxBd, *txBd; + /* struct mbuf *l = NULL; */ + rtems_unsigned16 status; + int nAdded; + + /* + * Free up buffer descriptors + */ + m860Enet_retire_tx_bd (sc); + + /* + * Set up the transmit buffer descriptors. + * No need to pad out short packets since the + * hardware takes care of that automatically. + * No need to copy the packet to a contiguous buffer + * since the hardware is capable of scatter/gather DMA. + */ + nAdded = 0; + txBd = firstTxBd = sc->txBdBase + sc->txBdHead; + for (;;) { + /* + * Wait for buffer descriptor to become available. + */ + if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { + /* + * Clear old events + */ + m860.fec.ievent = M860_FEC_IEVENT_TFINT; + + /* + * Wait for buffer descriptor to become available. + * Note that the buffer descriptors are checked + * *before* * entering the wait loop -- this catches + * the possibility that a buffer descriptor became + * available between the `if' above, and the clearing + * of the event register. + * This is to catch the case where the transmitter + * stops in the middle of a frame -- and only the + * last buffer descriptor in a frame can generate + * an interrupt. + */ + m860Enet_retire_tx_bd (sc); + while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { + rtems_event_set events; + + /* + * Unmask TXB (buffer transmitted) and + * TXE (transmitter error) events. + */ + m860.fec.ievent |= M860_FEC_IEVENT_TFINT; + rtems_bsdnet_event_receive (INTERRUPT_EVENT, + RTEMS_WAIT|RTEMS_EVENT_ANY, + RTEMS_NO_TIMEOUT, + &events); + m860Enet_retire_tx_bd (sc); + } + } + + /* + * Don't set the READY flag till the + * whole packet has been readied. + */ + status = nAdded ? M860_BD_READY : 0; + + /* + * FIXME: Why not deal with empty mbufs at at higher level? + * The IP fragmentation routine in ip_output + * can produce packet fragments with zero length. + * I think that ip_output should be changed to get + * rid of these zero-length mbufs, but for now, + * I'll deal with them here. + */ + if (m->m_len) { + /* + * Fill in the buffer descriptor + */ + txBd->buffer = mtod (m, void *); + txBd->length = m->m_len; + sc->txMbuf[sc->txBdHead] = m; + nAdded++; + if (++sc->txBdHead == sc->txBdCount) { + status |= M860_BD_WRAP; + sc->txBdHead = 0; + } + /* l = m;*/ + m = m->m_next; + } + else { + /* + * Just toss empty mbufs + */ + struct mbuf *n; + MFREE (m, n); + m = n; + /* + if (l != NULL) + l->m_next = m; + */ + } + + /* + * Set the transmit buffer status. + * Break out of the loop if this mbuf is the last in the frame. + */ + if (m == NULL) { + if (nAdded) { + status |= M860_BD_LAST | M860_BD_TX_CRC; + txBd->status = status; + firstTxBd->status |= M860_BD_READY; + m860.fec.x_des_active = 0x1000000; + sc->txBdActiveCount += nAdded; + } + break; + } + txBd->status = status; + txBd = sc->txBdBase + sc->txBdHead; + } +} + +/* + * Driver transmit daemon + */ +void +scc_txDaemon (void *arg) +{ + struct m860_enet_struct *sc = (struct m860_enet_struct *)arg; + struct ifnet *ifp = &sc->arpcom.ac_if; + struct mbuf *m; + rtems_event_set events; + + for (;;) { + /* + * Wait for packet + */ + rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, RTEMS_EVENT_ANY | RTEMS_WAIT, RTEMS_NO_TIMEOUT, &events); + + /* + * Send packets till queue is empty + */ + for (;;) { + /* + * Get the next mbuf chain to transmit. + */ + IF_DEQUEUE(&ifp->if_snd, m); + if (!m) + break; + scc_sendpacket (ifp, m); + } + ifp->if_flags &= ~IFF_OACTIVE; + } +} + +void +fec_txDaemon (void *arg) +{ + struct m860_enet_struct *sc = (struct m860_enet_struct *)arg; + struct ifnet *ifp = &sc->arpcom.ac_if; + struct mbuf *m; + rtems_event_set events; + + for (;;) { + /* + * Wait for packet + */ + rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, + RTEMS_EVENT_ANY | RTEMS_WAIT, + RTEMS_NO_TIMEOUT, + &events); + + /* + * Send packets till queue is empty + */ + for (;;) { + /* + * Get the next mbuf chain to transmit. + */ + IF_DEQUEUE(&ifp->if_snd, m); + if (!m) + break; + fec_sendpacket (ifp, m); + } + ifp->if_flags &= ~IFF_OACTIVE; + } +} + +/* + * Send packet (caller provides header). + */ +static void +m860_enet_start (struct ifnet *ifp) +{ + struct m860_enet_struct *sc = ifp->if_softc; + + rtems_event_send (sc->txDaemonTid, START_TRANSMIT_EVENT); + ifp->if_flags |= IFF_OACTIVE; +} + +/* + * Initialize and start the device + */ +static void +scc_init (void *arg) +{ + struct m860_enet_struct *sc = arg; + struct ifnet *ifp = &sc->arpcom.ac_if; + + if (sc->txDaemonTid == 0) { + + /* + * Set up SCC hardware + */ + m860_scc_initialize_hardware (sc); + + /* + * Start driver tasks + */ + sc->txDaemonTid = rtems_bsdnet_newproc ("SCtx", 4096, scc_txDaemon, sc); + sc->rxDaemonTid = rtems_bsdnet_newproc ("SCrx", 4096, scc_rxDaemon, sc); + + } + + /* + * Set flags appropriately + */ + if (ifp->if_flags & IFF_PROMISC) + m860.scc1.psmr |= 0x200; + else + m860.scc1.psmr &= ~0x200; + + /* + * Tell the world that we're running. + */ + ifp->if_flags |= IFF_RUNNING; + + /* + * Enable receiver and transmitter + */ + m860.scc1.gsmr_l |= 0x30; +} + +static void +fec_init (void *arg) +{ + struct m860_enet_struct *sc = arg; + struct ifnet *ifp = &sc->arpcom.ac_if; + + if (sc->txDaemonTid == 0) { + + /* + * Set up SCC hardware + */ + m860_fec_initialize_hardware (sc); + + /* + * Start driver tasks + */ + sc->txDaemonTid = rtems_bsdnet_newproc ("SCtx", 4096, fec_txDaemon, sc); + sc->rxDaemonTid = rtems_bsdnet_newproc ("SCrx", 4096, fec_rxDaemon, sc); + + } + + /* + * Set flags appropriately + */ + if (ifp->if_flags & IFF_PROMISC) + m860.fec.r_cntrl |= 0x8; + else + m860.fec.r_cntrl &= ~0x8; + + + /* + * Tell the world that we're running. + */ + ifp->if_flags |= IFF_RUNNING; + + /* + * Enable receiver and transmitter + */ + m860.fec.ecntrl = 0x2; +} + + +/* + * Stop the device + */ +static void +scc_stop (struct m860_enet_struct *sc) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + + ifp->if_flags &= ~IFF_RUNNING; + + /* + * Shut down receiver and transmitter + */ + m860.scc1.gsmr_l &= ~0x30; +} + +static void +fec_stop (struct m860_enet_struct *sc) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + + ifp->if_flags &= ~IFF_RUNNING; + + /* + * Shut down receiver and transmitter + */ + m860.fec.ecntrl = 0x0; +} + +/* + * Show interface statistics + */ +static void +enet_stats (struct m860_enet_struct *sc) +{ + printf (" Rx Interrupts:%-8lu", sc->rxInterrupts); + printf (" Not First:%-8lu", sc->rxNotFirst); + printf (" Not Last:%-8lu\n", sc->rxNotLast); + printf (" Giant:%-8lu", sc->rxGiant); + printf (" Runt:%-8lu", sc->rxRunt); + printf (" Non-octet:%-8lu\n", sc->rxNonOctet); + printf (" Bad CRC:%-8lu", sc->rxBadCRC); + printf (" Overrun:%-8lu", sc->rxOverrun); + printf (" Collision:%-8lu\n", sc->rxCollision); + printf (" Discarded:%-8lu\n", (unsigned long)m860.scc1p.un.ethernet.disfc); + + printf (" Tx Interrupts:%-8lu", sc->txInterrupts); + printf (" Deferred:%-8lu", sc->txDeferred); + printf (" Missed Hearbeat:%-8lu\n", sc->txHeartbeat); + printf (" No Carrier:%-8lu", sc->txLostCarrier); + printf ("Retransmit Limit:%-8lu", sc->txRetryLimit); + printf (" Late Collision:%-8lu\n", sc->txLateCollision); + printf (" Underrun:%-8lu", sc->txUnderrun); + printf (" Raw output wait:%-8lu\n", sc->txRawWait); +} + +/* + * Driver ioctl handler + */ +static int +scc_ioctl (struct ifnet *ifp, int command, caddr_t data) +{ + struct m860_enet_struct *sc = ifp->if_softc; + int error = 0; + + switch (command) { + case SIOCGIFADDR: + case SIOCSIFADDR: + ether_ioctl (ifp, command, data); + break; + + case SIOCSIFFLAGS: + switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { + case IFF_RUNNING: + scc_stop (sc); + break; + + case IFF_UP: + scc_init (sc); + break; + + case IFF_UP | IFF_RUNNING: + scc_stop (sc); + scc_init (sc); + break; + + default: + break; + } + break; + + case SIO_RTEMS_SHOW_STATS: + enet_stats (sc); + break; + + /* + * FIXME: All sorts of multicast commands need to be added here! + */ + default: + error = EINVAL; + break; + } + return error; +} + +static int +fec_ioctl (struct ifnet *ifp, int command, caddr_t data) +{ + struct m860_enet_struct *sc = ifp->if_softc; + int error = 0; + + switch (command) { + case SIOCGIFADDR: + case SIOCSIFADDR: + ether_ioctl (ifp, command, data); + break; + + case SIOCSIFFLAGS: + switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { + case IFF_RUNNING: + fec_stop (sc); + break; + + case IFF_UP: + fec_init (sc); + break; + + case IFF_UP | IFF_RUNNING: + fec_stop (sc); + fec_init (sc); + break; + + default: + break; + } + break; + + case SIO_RTEMS_SHOW_STATS: + enet_stats (sc); + break; + + /* + * FIXME: All sorts of multicast commands need to be added here! + */ + default: + error = EINVAL; + break; + } + return error; +} + +/* + * Attach an SCC driver to the system + */ +int +rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) +{ + struct m860_enet_struct *sc; + struct ifnet *ifp; + int mtu; + int i; + + /* + * Find a free driver + */ + for (i = 0 ; i < NIFACES ; i++) { + sc = &enet_driver[i]; + ifp = &sc->arpcom.ac_if; + if (ifp->if_softc == NULL) + break; + } + if (i >= NIFACES) { + printf ("Too many SCC drivers.\n"); + return 0; + } + + /* + * Process options + */ + if (config->hardware_address) { + memcpy (sc->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN); + } + else { + sc->arpcom.ac_enaddr[0] = 0x44; + sc->arpcom.ac_enaddr[1] = 0x22; + sc->arpcom.ac_enaddr[2] = 0x33; + sc->arpcom.ac_enaddr[3] = 0x33; + sc->arpcom.ac_enaddr[4] = 0x22; + sc->arpcom.ac_enaddr[5] = 0x44; + } + if (config->mtu) + mtu = config->mtu; + else + mtu = ETHERMTU; + if (config->rbuf_count) + sc->rxBdCount = config->rbuf_count; + else + sc->rxBdCount = RX_BUF_COUNT; + if (config->xbuf_count) + sc->txBdCount = config->xbuf_count; + else + sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF; + sc->acceptBroadcast = !config->ignore_broadcast; + + /* + * Set up network interface values + */ + ifp->if_softc = sc; + ifp->if_unit = i + 1; + ifp->if_name = "eth"; + ifp->if_mtu = mtu; + ifp->if_init = scc_init; + ifp->if_ioctl = scc_ioctl; + ifp->if_start = m860_enet_start; + ifp->if_output = ether_output; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; + if (ifp->if_snd.ifq_maxlen == 0) + ifp->if_snd.ifq_maxlen = ifqmaxlen; + + /* + * Attach the interface + */ + if_attach (ifp); + ether_ifattach (ifp); + return 1; +}; + +int +rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config) +{ + struct m860_enet_struct *sc; + struct ifnet *ifp; + int mtu; + + /* + * Find a free driver + */ + sc = &enet_driver[0]; + ifp = &sc->arpcom.ac_if; + if (ifp->if_softc != NULL) + return 0; + + + /* + * Process options + */ + if (config->hardware_address) { + memcpy (sc->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN); + } + else { + sc->arpcom.ac_enaddr[0] = 0x44; + sc->arpcom.ac_enaddr[1] = 0x22; + sc->arpcom.ac_enaddr[2] = 0x33; + sc->arpcom.ac_enaddr[3] = 0x33; + sc->arpcom.ac_enaddr[4] = 0x22; + sc->arpcom.ac_enaddr[5] = 0x44; + } + if (config->mtu) + mtu = config->mtu; + else + mtu = ETHERMTU; + if (config->rbuf_count) + sc->rxBdCount = config->rbuf_count; + else + sc->rxBdCount = RX_BUF_COUNT; + if (config->xbuf_count) + sc->txBdCount = config->xbuf_count; + else + sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF; + sc->acceptBroadcast = !config->ignore_broadcast; + + /* + * Set up network interface values + */ + ifp->if_softc = sc; + ifp->if_unit = 1; + ifp->if_name = "eth"; + ifp->if_mtu = mtu; + ifp->if_init = fec_init; + ifp->if_ioctl = fec_ioctl; + ifp->if_start = m860_enet_start; + ifp->if_output = ether_output; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; + if (ifp->if_snd.ifq_maxlen == 0) + ifp->if_snd.ifq_maxlen = ifqmaxlen; + + /* + * Attach the interface + */ + if_attach (ifp); + ether_ifattach (ifp); + return 1; +}; + +int +rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config) +{ + int i; + + if ((m860.fec.mii_data & 0xffff) == 0x2000) { +/* rtems_scc1_driver_attach(config);*/ + return rtems_fec_driver_attach(config); + } + else { + return rtems_scc1_driver_attach(config); + } +} diff --git a/c/src/lib/libbsp/powerpc/eth_comm/start/Makefile.in b/c/src/lib/libbsp/powerpc/eth_comm/start/Makefile.in new file mode 100644 index 0000000000..806b77893b --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/start/Makefile.in @@ -0,0 +1,59 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +PGM=${ARCH}/start.rel + +# C source names, if any, go here -- minus the .c +C_PIECES= +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +# Assembly source names, if any, go here -- minus the .S +S_PIECES=start +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) + +SRCS=$(C_FILES) $(H_FILES) $(S_FILES) +OBJS=$(C_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile +install: all diff --git a/c/src/lib/libbsp/powerpc/eth_comm/start/start.S b/c/src/lib/libbsp/powerpc/eth_comm/start/start.S new file mode 100644 index 0000000000..f7b9d420fe --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/start/start.S @@ -0,0 +1,154 @@ +/* dlentry.s + * + * $Id$ + * + * This file contains the entry veneer for RTEMS programs + * downloaded to the eth-comm board. + * + * This file was written by Jay Monkman (jmonkman@fracsa.com) + * It was based on the dlentry.s file for the Papyrus BSP, + * written by: + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + */ + +#include "asm.h" + +/* + * The initial stack is set to run BELOW the code base address. + * (between the vectors and text sections) + * + * All the entry veneer has to do is to clear the BSS. + */ + +/* + * GDB likes to have debugging information for the entry veneer. + * Here is some DWARF information. + */ +/* + * There was some debugging info here, but I removed it because I + * couldn't get it to work. It isn't really necessary as far as I + * can tell. It should still be in the papyrus BSP. -Jay + */ + + + +/* + * On entry to download_entry, R3 will hold a pointer to a Board Info + * Block (boardinfo_t). This should be copied as soon as possible + * to the global M860_binfo. (The block should be copied, _NOT_ + * the pointer) + */ + + .section ".entry" /* This might have to be the first thing in the + * text section. At one time, it had to be + * first, but I don't believe it is true + * andy more. */ + PUBLIC_VAR (start) +SYM(start): + bl .startup +base_addr: + +/* + * Parameters from linker + */ +toc_pointer: + .long s.got +bss_length: + .long bss.size +bss_addr: + .long bss.start + +PUBLIC_VAR (text_addr) +text_addr: + .long text.start + +PUBLIC_VAR (text_length) +text_length: + .long text.size + + +/* + * Initialization code + */ +.startup: + /* Get start address */ + mflr r1 + + /* clear the bss section */ + bl bssclr + +/* + * Copy the Board Info Block + */ + .extern SYM(M860_binfo) + lis r6, SYM(M860_binfo)@ha + addi r6, r6, SYM(M860_binfo)@l + + lhz r4, 0(r3) /* Load the size of the block */ + rlwinm. r4, r4, 30, 0x3fffffff /* get number of words */ + + mtctr r4 + +cpy_b: lwz r5, 0(r3) /* In with the old ... */ + stw r5, 0(r6) /* ... Out with the new */ + addi r6, r6, 0x4 /* Go to the next word */ + addi r3, r3, 0x4 + bdnz cpy_b /* decrement counter and loop */ + +/* + * C_setup. + */ + + /* set toc */ + lwz r2, toc_pointer-base_addr(r1) + + /* Set up stack pointer = beginning of text section - 56 */ + addi r1, r1, -56-4 + + lis r9, 0xff00 + addi r10, 0, -16384 + sth r10, 0x950(r9) + + lis r9, 0x0000 + addi r9, r9, 0x0007 + mtspr 0x9e, r9 + + /* clear argc and argv */ + xor r3, r3, r3 + xor r4, r4, r4 + + .extern SYM (boot_card) + b SYM (boot_card) /* call the first C routine */ + +/* + * bssclr - zero out bss + */ +bssclr: + lwz r4, bss_addr-base_addr(r1) /* Start of bss */ + lwz r5, bss_length-base_addr(r1) /* Length of bss */ + + rlwinm. r5,r5,30,0x3FFFFFFF /* form length/4 */ + beqlr /* no bss */ + mtctr r5 /* set ctr reg */ + xor r6,r6,r6 /* r6 = 0 */ +clear_bss: + stswi r6,r4,0x4 /* store r6 */ + addi r4,r4,0x4 /* update r2 */ + + bdnz clear_bss /* dec counter and loop */ + blr /* return */ diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/Makefile.in b/c/src/lib/libbsp/powerpc/eth_comm/startup/Makefile.in new file mode 100644 index 0000000000..7d75dfca56 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/Makefile.in @@ -0,0 +1,61 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@:@srcdir@/../../../shared +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +PGM=${ARCH}/startup.rel + +# C source names, if any, go here -- minus the .c +C_PIECES=bspclean bsplibc bsppost bspstart main sbrk setvec alloc860 mmu +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +# Assembly source names, if any, go here -- minus the .s +S_PIECES= +S_FILES=$(S_PIECES:%=%.s) +S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) + +SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) +OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + $(INSTALL) $(srcdir)/linkcmds ${PROJECT_RELEASE}/lib + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile +install: all + diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/alloc860.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/alloc860.c new file mode 100644 index 0000000000..b43cb4877b --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/alloc860.c @@ -0,0 +1,117 @@ +/* + * MPC860 buffer descriptor allocation routines + * + * Modified from original code by Jay Monkman (jmonkman@frasca.com) + * + * Original was written by: + * W. Eric Norum + * Saskatchewan Accelerator Laboratory + * University of Saskatchewan + * Saskatoon, Saskatchewan, CANADA + * eric@skatter.usask.ca + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> +#include <rtems/rtems/intr.h> +#include <rtems/error.h> +#include <mpc860.h> +#include <info.h> + +/* + * Send a command to the CPM RISC processer + */ +void M860ExecuteRISC(rtems_unsigned16 command) +{ + rtems_unsigned16 lvl; + + rtems_interrupt_disable(lvl); + while (m860.cpcr & M860_CR_FLG) { + continue; + } + + m860.cpcr = command | M860_CR_FLG; + rtems_interrupt_enable (lvl); +} + + +/* + * Allocation order: + * - Dual-Port RAM section 0 + * - Dual-Port RAM section 1 + * - Dual-Port RAM section 2 + * - Dual-Port RAM section 3 + * - Dual-Port RAM section 4 + */ +static struct { + char *base; + unsigned int size; + unsigned int used; +} bdregions[] = { + { (char *)&m860.dpram0[0], sizeof m860.dpram0, 0 }, + { (char *)&m860.dpram1[0], sizeof m860.dpram1, 0 }, + { (char *)&m860.dpram2[0], sizeof m860.dpram2, 0 }, + { (char *)&m860.dpram3[0], sizeof m860.dpram3, 0 }, + { (char *)&m860.dpram4[0], sizeof m860.dpram4, 0 }, +}; + +void * +M860AllocateBufferDescriptors (int count) +{ + unsigned int i; + ISR_Level level; + void *bdp = NULL; + unsigned int want = count * sizeof(m860BufferDescriptor_t); + + /* + * Running with interrupts disabled is usually considered bad + * form, but this routine is probably being run as part of an + * initialization sequence so the effect shouldn't be too severe. + */ + _ISR_Disable (level); + for (i = 0 ; i < sizeof(bdregions) / sizeof(bdregions[0]) ; i++) { + /* + * Verify that the region exists. + * This test is necessary since some chips have + * less dual-port RAM. + */ + if (bdregions[i].used == 0) { + volatile unsigned char *cp = bdregions[i].base; + *cp = 0xAA; + if (*cp != 0xAA) { + bdregions[i].used = bdregions[i].size; + continue; + } + *cp = 0x55; + if (*cp != 0x55) { + bdregions[i].used = bdregions[i].size; + continue; + } + *cp = 0x0; + } + if (bdregions[i].size - bdregions[i].used >= want) { + bdp = bdregions[i].base + bdregions[i].used; + bdregions[i].used += want; + break; + } + } + _ISR_Enable(level); + if (bdp == NULL) + rtems_panic("Can't allocate %d buffer descriptor(s).\n", count); + return bdp; +} + +void * +M860AllocateRiscTimers (int count) +{ + /* + * Convert the count to the number of buffer descriptors + * of equal or larger size. This ensures that all buffer + * descriptors are allocated with appropriate alignment. + */ + return M860AllocateBufferDescriptors (((count * 4) + + sizeof(m860BufferDescriptor_t) - 1) / + sizeof(m860BufferDescriptor_t)); +} diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c new file mode 100644 index 0000000000..beb734031f --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c @@ -0,0 +1,187 @@ +/* bsp_start() + * + * This routine starts the application. It includes application, + * board, and monitor specific initialization and configuration. + * The generic CPU dependent initialization has been performed + * before this routine is invoked. + * + * The MPC860 specific stuff was written by Jay Monkman (jmonkman@frasca.com) + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include <bsp.h> +#include <mpc860.h> +#include <rtems/libio.h> + +#include <libcsupport.h> + +#include <string.h> +#include <info.h> + +#ifdef STACK_CHECKER_ON +#include <stackchk.h> +#endif + +boardinfo_t M860_binfo; + + +/* + * The original table from the application and our copy of it with + * some changes. + */ +extern rtems_configuration_table Configuration; + +rtems_configuration_table BSP_Configuration; + +rtems_cpu_table Cpu_table; + +char *rtems_progname; + +/* + * Use the shared implementations of the following routines + */ +void bsp_postdriver_hook(void); +void bsp_libc_init( void *, unsigned32, int ); + +/* + * Function: bsp_pretasking_hook + * Created: 95/03/10 + * + * Description: + * BSP pretasking hook. Called just before drivers are initialized. + * Used to setup libc and install any BSP extensions. + * + * NOTES: + * Must not use libc (to do io) from here, since drivers are + * not yet initialized. + * + */ + +void +bsp_pretasking_hook(void) +{ + extern int _end; + rtems_unsigned32 heap_start; + + /* + * Let's check to see if the size of M860_binfo is what + * it should be. It might not be if the info.h files + * for RTEMS and the bootloader define boardinfo_t + * differently. + */ + + /* Oops. printf() won't work yet, since the console is not initialized. + I should probably find some way of doing this though. + if (M860_binfo.size != sizeof(boardinfo_t)) { + printf("The size of the Board Info Block appears to be incorrect.\n"); + printf(" This could occur if the 'info.h' files for RTEMS and the\n"); + printf(" bootloader differ in their definition of boardinfo_t\n"); + } + */ + heap_start = (rtems_unsigned32) &_end; + + /* Align the heap on a natural boundary (4 bytes?) */ + if (heap_start & (CPU_ALIGNMENT-1)) { + heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); + } + /* set up a 256K heap */ + bsp_libc_init((void *) heap_start, 256 * 1024, 0); + +#ifdef STACK_CHECKER_ON + /* + * Initialize the stack bounds checker + * We can either turn it on here or from the app. + */ + + Stack_check_Initialize(); +#endif + +#ifdef RTEMS_DEBUG + rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); +#endif +} + + +void bsp_start(void) +{ + extern int _end; + rtems_unsigned32 heap_start; + rtems_unsigned32 ws_start; + /* + * Allocate the memory for the RTEMS Work Space. This can come from + * a variety of places: hard coded address, malloc'ed from outside + * RTEMS world (e.g. simulator or primitive memory manager), or (as + * typically done by stock BSPs) by subtracting the required amount + * of work space from the last physical address on the CPU board. + */ + + /* + * Need to "allocate" the memory for the RTEMS Workspace and + * tell the RTEMS configuration where it is. This memory is + * not malloc'ed. It is just "pulled from the air". + */ + + heap_start = (rtems_unsigned32) &_end; + if (heap_start & (CPU_ALIGNMENT-1)) + heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); + + + ws_start = heap_start + (256 * 1024); + if (ws_start & ((512 * 1024) - 1)) { /* align to 512K boundary */ + ws_start = (ws_start + (512 * 1024)) & ~((512 * 1024) - 1); + } + + BSP_Configuration.work_space_start = (void *)ws_start; + BSP_Configuration.work_space_size = 512 * 1024; + + /* + * initialize the CPU table for this BSP + */ + + Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ + Cpu_table.postdriver_hook = bsp_postdriver_hook; + Cpu_table.interrupt_stack_size = 4 * 1024; + + Cpu_table.clicks_per_usec = 1; /* for 4MHz extclk */ + Cpu_table.serial_per_sec = 10000000; + Cpu_table.serial_external_clock = 1; + Cpu_table.serial_xon_xoff = 0; + Cpu_table.serial_cts_rts = 1; + Cpu_table.serial_rate = 9600; + Cpu_table.timer_average_overhead = 0; + Cpu_table.timer_least_valid = 0; + Cpu_table.clock_speed = 40000000; + + /* + * Call this in case we use TERMIOS for console I/O + */ + m860_console_reserve_resources(&BSP_Configuration); + + /* + * Since we are currently autodetecting whether to use SCC1 or + * the FEC for ethernet, we set up a register in the ethernet + * transciever that is used for 10/100 Mbps ethernet now, so that + * we can attempt to read it later in rtems_enet_driver_attach() + */ + m860.fec.mii_speed = 0x0a; + m860.fec.mii_data = 0x680a0000; + + + m860.scc2.sccm=0; + m860.scc2p.rbase=0; + m860.scc2p.tbase=0; + M860ExecuteRISC(M860_CR_OP_STOP_TX | M860_CR_CHAN_SCC2); + + mmu_init(); +} + + diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/linkcmds b/c/src/lib/libbsp/powerpc/eth_comm/startup/linkcmds new file mode 100644 index 0000000000..d805fedf39 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/linkcmds @@ -0,0 +1,153 @@ +/* + * This file contains directives for the GNU linker which are specific + * to the Ethernet-Comm Board + * + * $Id$ + */ + +OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc", + "elf32-powerpc") +OUTPUT_ARCH(powerpc) + SEARCH_DIR(/usr/local/powerpc-rtems/lib); + +ENTRY(start) + +MEMORY + { + ram : org = 0x0, l = 4M + dpram : org = 0xff000000, l = 16K + canbus : org = 0xff100000, l = 12K + flash : org = 0xfff00000, l = 512K + } + + +SECTIONS +{ + .vectors : + { + *(.vectors) + } >ram + + /* + * The stack will live in this area - between the vectors and + * the text section. + */ + + .text 0x10000: + { + text.start = .; + *(.entry) + *(.entry2) + *(.text) + *(.rodata) + *(.rodata1) + *(.descriptors) + *(rom_ver) + etext = ALIGN(0x10); + _etext = .; + + __CTOR_LIST__ = .; + LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) + *(.ctors) + LONG(0) + __CTOR_END__ = .; + + __DTOR_LIST__ = .; + LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) + *(.dtors) + LONG(0) + __DTOR_END__ = .; + + *(.lit) + *(.shdata) + *(.init) + *(.fini) + _endtext = .; + text.end = .; + } > ram + + /* R/W Data */ + .data : + { + *(.data) + *(.data1) + PROVIDE (__SDATA_START__ = .); + *(.sdata) + } > ram + + PROVIDE (__EXCEPT_START__ = .); + .gcc_except_table : { *(.gcc_except_table) } >RAM + PROVIDE (__EXCEPT_END__ = .); + __GOT_START__ = .; + .got : + { + s.got = .; + *(.got.plt) *(.got) + } > ram + __GOT_END__ = .; + + .got1 : { *(.got1) } >ram + PROVIDE (__GOT2_START__ = .); + PROVIDE (_GOT2_START_ = .); + .got2 : { *(.got2) } >ram + PROVIDE (__GOT2_END__ = .); + PROVIDE (_GOT2_END_ = .); + + PROVIDE (__FIXUP_START__ = .); + PROVIDE (_FIXUP_START_ = .); + .fixup : { *(.fixup) } >ram + PROVIDE (_FIXUP_END_ = .); + PROVIDE (__FIXUP_END__ = .); + + PROVIDE (__SDATA2_START__ = .); + .sdata2 : { *(.sdata2) } >ram + .sbss2 : { *(.sbss2) } >ram + PROVIDE (__SBSS2_END__ = .); + + .sbss2 : { *(.sbss2) } >ram + PROVIDE (__SBSS2_END__ = .); + + __SBSS_START__ = .; + .bss : + { + bss.start = .; + *(.bss) *(.sbss) *(COMMON) + . = ALIGN(4); + bss.end = .; + } > ram + __SBSS_END__ = .; + + bss.size = bss.end - bss.start; + text.size = text.end - text.start; + PROVIDE(_end = bss.end); + + dpram : + { + m860 = .; + _m860 = .; + . += (8 * 1024); + } >dpram + + canbus : + { + canbus0 = .; + . += (0x1000); + canbus1 = .; + . += (0x1000); + canbus2 = .; + . += (0x1000); + } >canbus + + + .line 0 : { *(.line) } + .debug 0 : { *(.debug) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_aregion 0 : { *(.debug_aregion) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + +} diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/mmu.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/mmu.c new file mode 100644 index 0000000000..1a3f11e20a --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/mmu.c @@ -0,0 +1,126 @@ +/* + * mmu.c - this file contains functions for initializing the MMU + * + * Written by Jay Monkman (jmonkman@frasca.com) + */ + +#include <bsp.h> +#include <mpc860.h> + +/* Macros for handling all the MMU SPRs */ +#define PUT_MI_CTR(r) __asm__ volatile ("mtspr 0x310,%0\n" ::"r"(r)) +#define GET_MI_CTR(r) __asm__ volatile ("mfspr %0,0x310\n" :"=r"(r)) +#define PUT_MD_CTR(r) __asm__ volatile ("mtspr 0x318,%0\n" ::"r"(r)) +#define GET_MD_CTR(r) __asm__ volatile ("mfspr %0,0x318\n" :"=r"(r)) +#define PUT_M_CASID(r) __asm__ volatile ("mtspr 0x319,%0\n" ::"r"(r)) +#define GET_M_CASID(r) __asm__ volatile ("mfspr %0,0x319\n" :"=r"(r)) +#define PUT_MI_EPN(r) __asm__ volatile ("mtspr 0x313,%0\n" ::"r"(r)) +#define GET_MI_EPN(r) __asm__ volatile ("mfspr %0,0x313\n" :"=r"(r)) +#define PUT_MI_TWC(r) __asm__ volatile ("mtspr 0x315,%0\n" ::"r"(r)) +#define GET_MI_TWC(r) __asm__ volatile ("mfspr %0,0x315\n" :"=r"(r)) +#define PUT_MI_RPN(r) __asm__ volatile ("mtspr 0x316,%0\n" ::"r"(r)) +#define GET_MI_RPN(r) __asm__ volatile ("mfspr %0,0x316\n" :"=r"(r)) +#define PUT_MD_EPN(r) __asm__ volatile ("mtspr 0x313,%0\n" ::"r"(r)) +#define GET_MD_EPN(r) __asm__ volatile ("mfspr %0,0x313\n" :"=r"(r)) +#define PUT_M_TWB(r) __asm__ volatile ("mtspr 0x31c,%0\n" ::"r"(r)) +#define GET_M_TWB(r) __asm__ volatile ("mfspr %0,0x31c\n" :"=r"(r)) +#define PUT_MD_TWC(r) __asm__ volatile ("mtspr 0x31d,%0\n" ::"r"(r)) +#define GET_MD_TWC(r) __asm__ volatile ("mfspr %0,0x31d\n" :"=r"(r)) +#define PUT_MD_RPN(r) __asm__ volatile ("mtspr 0x31e,%0\n" ::"r"(r)) +#define GET_MD_RPN(r) __asm__ volatile ("mfspr %0,0x31e\n" :"=r"(r)) +#define PUT_MI_AP(r) __asm__ volatile ("mtspr 0x312,%0\n" ::"r"(r)) +#define GET_MI_AP(r) __asm__ volatile ("mfspr %0,0x312\n" :"=r"(r)) +#define PUT_MD_AP(r) __asm__ volatile ("mtspr 0x31a,%0\n" ::"r"(r)) +#define GET_MD_AP(r) __asm__ volatile ("mfspr %0,0x31a\n" :"=r"(r)) +#define PUT_M_TW(r) __asm__ volatile ("mtspr 0x31f,%0\n" ::"r"(r)) +#define GET_M_TW(r) __asm__ volatile ("mfspr %0,0x31f\n" :"=r"(r)) +#define PUT_MI_DCAM(r) __asm__ volatile ("mtspr 0x330,%0\n" ::"r"(r)) +#define GET_MI_DCAM(r) __asm__ volatile ("mfspr %0,0x330\n" :"=r"(r)) +#define PUT_MI_DRAM0(r) __asm__ volatile ("mtspr 0x331,%0\n" ::"r"(r)) +#define GET_MI_DRAM0(r) __asm__ volatile ("mfspr %0,0x331\n" :"=r"(r)) +#define PUT_MI_DRAM1(r) __asm__ volatile ("mtspr 0x332,%0\n" ::"r"(r)) +#define GET_MI_DRAM1(r) __asm__ volatile ("mfspr %0,0x332\n" :"=r"(r)) +#define PUT_MD_DCAM(r) __asm__ volatile ("mtspr 0x338,%0\n" ::"r"(r)) +#define GET_MD_DCAM(r) __asm__ volatile ("mfspr %0,0x338\n" :"=r"(r)) +#define PUT_MD_DRAM0(r) __asm__ volatile ("mtspr 0x339,%0\n" ::"r"(r)) +#define GET_MD_DRAM0(r) __asm__ volatile ("mfspr %0,0x339\n" :"=r"(r)) +#define PUT_MD_DRAM1(r) __asm__ volatile ("mtspr 0x33a,%0\n" ::"r"(r)) +#define GET_MD_DRAM1(r) __asm__ volatile ("mfspr %0,0x33a\n" :"=r"(r)) +#define PUT_IC_CST(r) __asm__ volatile ("mtspr 0x230,%0\n" ::"r"(r)) +#define GET_IC_CST(r) __asm__ volatile ("mfspr %0,0x230\n" :"=r"(r)) +#define PUT_DC_CST(r) __asm__ volatile ("mtspr 0x238,%0\n" ::"r"(r)) +#define GET_DC_CST(r) __asm__ volatile ("mfspr %0,0x238\n" :"=r"(r)) +#define PUT_IC_ADR(r) __asm__ volatile ("mtspr 0x231,%0\n" ::"r"(r)) +#define GET_IC_ADR(r) __asm__ volatile ("mfspr %0,0x231\n" :"=r"(r)) +#define PUT_IC_DAT(r) __asm__ volatile ("mtspr 0x232,%0\n" ::"r"(r)) +#define GET_IC_DAT(r) __asm__ volatile ("mfspr %0,0x232\n" :"=r"(r)) + +extern rtems_configuration_table BSP_Configuration; + +void mmu_init(void) +{ + register unsigned long t1, t2; + + /* Let's clear MSR[IR] and MSR[DR] */ + t2 = PPC_MSR_IR | PPC_MSR_DR; + __asm__ volatile ( + "mfmsr %0\n" + "andc %0, %0, %1\n" + "mtmsr %0\n" :"=r"(t1), "=r"(t2): + "1"(t2)); + + /* Invalidate the TLBs */ + __asm__ volatile ("tlbia\n"::); + __asm__ volatile ("isync\n"::); + + /* make sure no TLB entries are reserved */ + t1 = 0; + PUT_MI_CTR(t1); + + t1 = M860_MD_CTR_TWAM; /* 4K pages */ + /* PUT_MD_CTR(t1); */ + + t1 = M860_MI_EPN_VALID; /* make entry valid */ + /* PUT_MD_EPN(t1); */ + PUT_MI_EPN(t1); + + t1 = M860_MI_TWC_PS8 | M860_MI_TWC_VALID; /* 8 MB pages, valid */ + /* PUT_MD_TWC(t1); */ + PUT_MI_TWC(t1); + + t1 = M860_MD_RPN_CHANGE | M860_MD_RPN_F | M860_MD_RPN_16K | + M860_MD_RPN_SHARED | M860_MD_RPN_VALID; + /* PUT_MD_RPN(t1); */ + PUT_MI_RPN(t1); + + t1 = M860_MI_AP_Kp << 30; + PUT_MI_AP(t1); + /* PUT_MD_AP(t1); */ + + t1 = M860_CACHE_CMD_UNLOCK; + /* PUT_DC_CST(t1); */ + PUT_IC_CST(t1); + + t1 = M860_CACHE_CMD_INVALIDATE; + /* PUT_DC_CST(t1); */ + PUT_IC_CST(t1); + + t1 = M860_CACHE_CMD_ENABLE; + PUT_IC_CST(t1); + + t1 = M860_CACHE_CMD_SFWT; + /* PUT_DC_CST(t1); */ + t1 = M860_CACHE_CMD_ENABLE; + /* PUT_DC_CST(t1);*/ + + + + /* Let's set MSR[IR] */ + t2 = PPC_MSR_IR; + __asm__ volatile ( + "mfmsr %0\n" + "or %0, %0, %1\n" + "mtmsr %0\n" :"=r"(t1), "=r"(t2): + "1"(t2)); + +} diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/setvec.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/setvec.c new file mode 100644 index 0000000000..b32dc8aaec --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/setvec.c @@ -0,0 +1,44 @@ +/* set_vector + * + * This routine installs an interrupt vector on the target Board/CPU. + * This routine is allowed to be as board dependent as necessary. + * + * INPUT: + * handler - interrupt handler entry point + * vector - vector number + * type - 0 indicates raw hardware connect + * 1 indicates RTEMS interrupt connect + * + * RETURNS: + * address of previous interrupt handler + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> + +rtems_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +) +{ + rtems_isr_entry previous_isr; + + if (type) { + rtems_interrupt_catch(handler, vector, (rtems_isr_entry *) &previous_isr ); + } else { + /* XXX: install non-RTEMS ISR as "raw" interupt */ + } + return previous_isr; +} + diff --git a/c/src/lib/libbsp/powerpc/eth_comm/times b/c/src/lib/libbsp/powerpc/eth_comm/times new file mode 100644 index 0000000000..2ac0b9ee22 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/times @@ -0,0 +1,194 @@ +# +# Timing Test Suite Results for the NO_BSP +# +# NOTE: This is just a template. The times are irrelevant since this BSP +# can only be compiled -- not executed. +# +# $Id$ +# + +Board: +CPU: include coprocessor if applicable +Clock Speed: +Memory Configuration: SRAM, DRAM, cache, etc +Wait States: + +Times Reported in: cycles, microseconds, etc +Timer Source: Count Down Timer, on-CPU cycle counter, etc + +Column X: +Column Y: + +# DESCRIPTION A B +== ================================================================= ==== ==== + 1 rtems_semaphore_create 20 + rtems_semaphore_delete 21 + rtems_semaphore_obtain: available 15 + rtems_semaphore_obtain: not available -- NO_WAIT 15 + rtems_semaphore_release: no waiting tasks 16 + + 2 rtems_semaphore_obtain: not available -- caller blocks 62 + + 3 rtems_semaphore_release: task readied -- preempts caller 55 + + 4 rtems_task_restart: blocked task -- preempts caller 77 + rtems_task_restart: ready task -- preempts caller 70 + rtems_semaphore_release: task readied -- returns to caller 25 + rtems_task_create 57 + rtems_task_start 31 + rtems_task_restart: suspended task -- returns to caller 36 + rtems_task_delete: suspended task 47 + rtems_task_restart: ready task -- returns to caller 37 + rtems_task_restart: blocked task -- returns to caller 46 + rtems_task_delete: blocked task 50 + + 5 rtems_task_suspend: calling task 51 + rtems_task_resume: task readied -- preempts caller 49 + + 6 rtems_task_restart: calling task 59 + rtems_task_suspend: returns to caller 18 + rtems_task_resume: task readied -- returns to caller 19 + rtems_task_delete: ready task 50 + + 7 rtems_task_restart: suspended task -- preempts caller 70 + + 8 rtems_task_set_priority: obtain current priority 12 + rtems_task_set_priority: returns to caller 27 + rtems_task_mode: obtain current mode 5 + rtems_task_mode: no reschedule 5 + rtems_task_mode: reschedule -- returns to caller 8 + rtems_task_mode: reschedule -- preempts caller 39 + rtems_task_set_note 13 + rtems_task_get_note 13 + rtems_clock_set 33 + rtems_clock_get 3 + + 9 rtems_message_queue_create 110 + rtems_message_queue_send: no waiting tasks 37 + rtems_message_queue_urgent: no waiting tasks 37 + rtems_message_queue_receive: available 31 + rtems_message_queue_flush: no messages flushed 12 + rtems_message_queue_flush: messages flushed 16 + rtems_message_queue_delete 26 + +10 rtems_message_queue_receive: not available -- NO_WAIT 15 + rtems_message_queue_receive: not available -- caller blocks 62 + +11 rtems_message_queue_send: task readied -- preempts caller 72 + +12 rtems_message_queue_send: task readied -- returns to caller 39 + +13 rtems_message_queue_urgent: task readied -- preempts caller 72 + +14 rtems_message_queue_urgent: task readied -- returns to caller 39 + +15 rtems_event_receive: obtain current events 1 + rtems_event_receive: not available -- NO_WAIT 12 + rtems_event_receive: not available -- caller blocks 56 + rtems_event_send: no task readied 12 + rtems_event_receive: available 12 + rtems_event_send: task readied -- returns to caller 24 + +16 rtems_event_send: task readied -- preempts caller 55 + +17 rtems_task_set_priority: preempts caller 62 + +18 rtems_task_delete: calling task 83 + +19 rtems_signal_catch 9 + rtems_signal_send: returns to caller 15 + rtems_signal_send: signal to self 18 + exit ASR overhead: returns to calling task 22 + exit ASR overhead: returns to preempting task 49 + +20 rtems_partition_create 35 + rtems_region_create 23 + rtems_partition_get_buffer: available 15 + rtems_partition_get_buffer: not available 13 + rtems_partition_return_buffer 18 + rtems_partition_delete 16 + rtems_region_get_segment: available 22 + rtems_region_get_segment: not available -- NO_WAIT 21 + rtems_region_return_segment: no waiting tasks 19 + rtems_region_get_segment: not available -- caller blocks 64 + rtems_region_return_segment: task readied -- preempts caller 74 + rtems_region_return_segment: task readied -- returns to caller 44 + rtems_region_delete 16 + rtems_io_initialize 2 + rtems_io_open 1 + rtems_io_close 1 + rtems_io_read 1 + rtems_io_write 1 + rtems_io_control 1 + +21 rtems_task_ident 149 + rtems_message_queue_ident 145 + rtems_semaphore_ident 156 + rtems_partition_ident 145 + rtems_region_ident 148 + rtems_port_ident 145 + rtems_timer_ident 145 + rtems_rate_monotonic_ident 145 + +22 rtems_message_queue_broadcast: task readied -- returns to caller 42 + rtems_message_queue_broadcast: no waiting tasks 17 + rtems_message_queue_broadcast: task readied -- preempts caller 78 + +23 rtems_timer_create 14 + rtems_timer_fire_after: inactive 22 + rtems_timer_fire_after: active 24 + rtems_timer_cancel: active 15 + rtems_timer_cancel: inactive 13 + rtems_timer_reset: inactive 21 + rtems_timer_reset: active 23 + rtems_timer_fire_when: inactive 34 + rtems_timer_fire_when: active 34 + rtems_timer_delete: active 19 + rtems_timer_delete: inactive 17 + rtems_task_wake_when 69 + +24 rtems_task_wake_after: yield -- returns to caller 9 + rtems_task_wake_after: yields -- preempts caller 45 + +25 rtems_clock_tick 4 + +26 _ISR_Disable 0 + _ISR_Flash 1 + _ISR_Enable 1 + _Thread_Disable_dispatch 0 + _Thread_Enable_dispatch 7 + _Thread_Set_state 11 + _Thread_Disptach (NO FP) 31 + context switch: no floating point contexts 21 + context switch: self 10 + context switch: to another task 10 + context switch: restore 1st FP task 25 + fp context switch: save idle, restore idle 31 + fp context switch: save idle, restore initialized 19 + fp context switch: save initialized, restore initialized 20 + _Thread_Resume 7 + _Thread_Unblock 7 + _Thread_Ready 9 + _Thread_Get 4 + _Semaphore_Get 2 + _Thread_Get: invalid id 0 + +27 interrupt entry overhead: returns to interrupted task 6 + interrupt exit overhead: returns to interrupted task 6 + interrupt entry overhead: returns to nested interrupt 6 + interrupt exit overhead: returns to nested interrupt 5 + interrupt entry overhead: returns to preempting task 7 + interrupt exit overhead: returns to preempting task 36 + +28 rtems_port_create 16 + rtems_port_external_to_internal 11 + rtems_port_internal_to_external 11 + rtems_port_delete 16 + +29 rtems_rate_monotonic_create 15 + rtems_rate_monotonic_period: initiate period -- returns to caller 21 + rtems_rate_monotonic_period: obtain status 13 + rtems_rate_monotonic_cancel 16 + rtems_rate_monotonic_delete: inactive 18 + rtems_rate_monotonic_delete: active 20 + rtems_rate_monotonic_period: conclude periods -- caller blocks 53 diff --git a/c/src/lib/libbsp/powerpc/eth_comm/wrapup/Makefile.in b/c/src/lib/libbsp/powerpc/eth_comm/wrapup/Makefile.in new file mode 100644 index 0000000000..7841899fe6 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/eth_comm/wrapup/Makefile.in @@ -0,0 +1,60 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +# We only build the networking device driver if HAS_NETWORKING was defined +NETWORKING_DRIVER_yes_V = network +NETWORKING_DRIVER = $(NETWORKING_DRIVER_$(HAS_NETWORKING)_V) + +BSP_PIECES=startup start canbus console $(NETWORKING_DRIVER) +# pieces to pick up out of libcpu/ppc +CPU_PIECES=mpc860/clock mpc860/timer mpc860/console-generic mpc860/vectors +GENERIC_PIECES= + +# bummer; have to use $foreach since % pattern subst rules only replace 1x +OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ + $(foreach piece, $(CPU_PIECES), \ + ../../../../libcpu/$(RTEMS_CPU)/$(piece)/$(ARCH)/$(notdir $(piece)).rel) \ + $(foreach piece, $(GENERIC_PIECES), \ + ../../../$(piece)/$(ARCH)/$(piece).rel) +LIB=$(ARCH)/libbsp.a + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/lib.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +$(LIB): ${OBJS} + $(make-library) + +all: ${ARCH} $(SRCS) $(LIB) + $(INSTALL_VARIANT) -m 644 $(LIB) ${PROJECT_RELEASE}/lib + +install: all + |