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authorJoel Sherrill <joel.sherrill@OARcorp.com>2000-06-12 19:57:02 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2000-06-12 19:57:02 +0000
commit8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52 (patch)
tree9253f150814c99167239f7c2cc850cdd9d92c003 /c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c
parentf481c39c015a71a6747d8e0f4f923fabe1086ffc (diff)
downloadrtems-8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52.tar.bz2
Patch from John Cotton <john.cotton@nrc.ca>, Charles-Antoine Gauthier
<charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart <Darlene.Stewart@nrc.ca> to add support for a number of very significant things: + BSPs for many variations on the Motorola MBX8xx board series + Cache Manager including initial support for m68040 and PowerPC + Rework of mpc8xx libcpu code so all mpc8xx CPUs now use same code base. + Rework of eth_comm BSP to utiltize above. John reports this works on the 821 and 860
Diffstat (limited to 'c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c')
-rw-r--r--c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c19
1 files changed, 10 insertions, 9 deletions
diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c
index be35333ea5..c5c1c37d76 100644
--- a/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c
@@ -18,7 +18,6 @@
*/
#include <bsp.h>
-#include <mpc860.h>
#include <rtems/libio.h>
#include <libcsupport.h>
@@ -115,6 +114,10 @@ void bsp_start(void)
extern int _end;
rtems_unsigned32 heap_start;
rtems_unsigned32 ws_start;
+
+ cpu_init();
+ mmu_init();
+
/*
* Allocate the memory for the RTEMS Work Space. This can come from
* a variety of places: hard coded address, malloc'ed from outside
@@ -166,16 +169,14 @@ void bsp_start(void)
* transciever that is used for 10/100 Mbps ethernet now, so that
* we can attempt to read it later in rtems_enet_driver_attach()
*/
- m860.fec.mii_speed = 0x0a;
- m860.fec.mii_data = 0x680a0000;
-
+ m8xx.fec.mii_speed = 0x0a;
+ m8xx.fec.mii_data = 0x680a0000;
- m860.scc2.sccm=0;
- m860.scc2p.rbase=0;
- m860.scc2p.tbase=0;
- M860ExecuteRISC(M860_CR_OP_STOP_TX | M860_CR_CHAN_SCC2);
- mmu_init();
+ m8xx.scc2.sccm=0;
+ m8xx.scc2p.rbase=0;
+ m8xx.scc2p.tbase=0;
+ m8xx_cp_execute_cmd( M8xx_CR_OP_STOP_TX | M8xx_CR_CHAN_SCC2 );
}