Initial revision

4 files changed, 241 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/addrconv.c b/c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/addrconv.c
new file mode 100644
index 0000000000..0e188fc941
--- /dev/null
+++ b/c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/addrconv.c
@@ -0,0 +1,31 @@
+/*  Shm_Convert_address
+ *
+ *  No address range conversion is required.
+ *
+ *  Input parameters:
+ *    address - address to convert
+ *
+ *  Output parameters:
+ *    returns - converted address
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include <shm.h>
+
+void *Shm_Convert_address(
+  void *address
+)
+{
+  return ( address );
+}
diff --git a/c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/getcfg.c b/c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/getcfg.c
new file mode 100644
index 0000000000..ca8409a3f0
--- /dev/null
+++ b/c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/getcfg.c
@@ -0,0 +1,77 @@
+/*  void Shm_Get_configuration( localnode, &shmcfg )
+ *
+ *  This routine initializes, if necessary, and returns a pointer
+ *  to the Shared Memory Configuration Table for the XXX target.
+ *
+ *  INPUT PARAMETERS:
+ *    localnode - local node number
+ *    shmcfg    - address of pointer to SHM Config Table
+ *
+ *  OUTPUT PARAMETERS:
+ *    *shmcfg   - pointer to SHM Config Table
+ *
+XXX: FIX THE COMMENTS BELOW WHEN THE CPU IS KNOWN
+ *  NOTES:  The XYZ does not have an interprocessor interrupt.
+ *
+ *          The following table illustrates the configuration limitations:
+ *
+ *                                   BUS     MAX
+ *                          MODE    ENDIAN  NODES
+ *                        ========= ====== =======
+ *                         POLLED    BIG    2+
+ *                        INTERRUPT **** NOT SUPPORTED ****
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include <shm.h>
+
+/*
+ *  configured if currently polling of interrupt driven
+ */
+
+#define INTERRUPT 0        /* XXX: */
+#define POLLING   1        /* XXX: fix me -- is polling ONLY!!! */
+
+
+shm_config_table BSP_shm_cfgtbl;
+
+void Shm_Get_configuration(
+  rtems_unsigned32   localnode,
+  shm_config_table **shmcfg
+)
+{
+   BSP_shm_cfgtbl.base         = 0x0;
+   BSP_shm_cfgtbl.length       = 1 * MEGABYTE;
+   BSP_shm_cfgtbl.format       = SHM_BIG;
+
+   /*
+    *  Override cause_intr or shm_isr if your target has
+    *  special requirements.
+    */
+
+   BSP_shm_cfgtbl.cause_intr   = Shm_Cause_interrupt;
+
+#ifdef NEUTRAL_BIG
+   BSP_shm_cfgtbl.convert      = NULL_CONVERT;
+#else
+   BSP_shm_cfgtbl.convert      = CPU_swap_u32;
+#endif
+
+   BSP_shm_cfgtbl.poll_intr    = POLLED_MODE;
+   BSP_shm_cfgtbl.Intr.address = NO_INTERRUPT;
+   BSP_shm_cfgtbl.Intr.value   = NO_INTERRUPT;
+   BSP_shm_cfgtbl.Intr.length  = NO_INTERRUPT;
+
+   *shmcfg = &BSP_shm_cfgtbl;
+}
diff --git a/c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/lock.c b/c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/lock.c
new file mode 100644
index 0000000000..acdc8b7b48
--- /dev/null
+++ b/c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/lock.c
@@ -0,0 +1,86 @@
+/*  Shared Memory Lock Routines
+ *
+ *  This shared memory locked queue support routine need to be
+ *  able to lock the specified locked queue.  Interrupts are
+ *  disabled while the queue is locked to prevent preemption
+ *  and deadlock when two tasks poll for the same lock.
+ *  previous level.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include <shm.h>
+
+/*
+ *  Shm_Initialize_lock
+ *
+ *  Initialize the lock for the specified locked queue.
+ */
+
+void Shm_Initialize_lock(
+  Shm_Locked_queue_Control *lq_cb
+)
+{
+  lq_cb->lock = LQ_UNLOCKED;
+}
+
+/*  void _Shm_Lock( &lq_cb )
+ *
+ *  This shared memory locked queue support routine locks the
+ *  specified locked queue.  It disables interrupts to prevent
+ *  a deadlock condition.
+ */
+
+void Shm_Lock(
+  Shm_Locked_queue_Control *lq_cb
+)
+{
+  rtems_unsigned32 isr_level;
+  rtems_unsigned32 *lockptr = &lq_cb->lock;
+  rtems_unsigned32 lock_value;
+
+  lock_value = 0x80000000;
+  rtems_interrupt_disable( isr_level );
+
+    Shm_isrstat = isr_level;
+    while ( lock_value ) {
+      asm volatile( ""
+                         : "=r" (lockptr), "=r" (lock_value)
+                         : "0" (lockptr),  "1" (lock_value)
+                  );
+      /*
+       *  If not available, then may want to delay to reduce load on lock.
+       */
+
+      if ( lock_value )
+        delay( 10 );   /* approximately 10 microseconds */
+   }
+}
+
+/*
+ *  Shm_Unlock
+ *
+ *  Unlock the lock for the specified locked queue.
+ */
+
+void Shm_Unlock(
+  Shm_Locked_queue_Control *lq_cb
+)
+{
+  rtems_unsigned32 isr_level;
+
+  lq_cb->lock = SHM_UNLOCK_VALUE;
+  isr_level = Shm_isrstat;
+  rtems_interrupt_enable( isr_level );
+}
+
diff --git a/c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/mpisr.c b/c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/mpisr.c
new file mode 100644
index 0000000000..592c0cfcc5
--- /dev/null
+++ b/c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/mpisr.c
@@ -0,0 +1,47 @@
+/*  Shm_isr_nobsp()
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include <shm.h>
+
+rtems_isr Shm_isr_nobsp( void )
+{
+  /*
+   *  If this routine has to do anything other than the mpisr.c
+   *  found in the generic driver, then copy the contents of the generic
+   *  mpisr.c and augment it to satisfy this particular board.  Typically,
+   *  you need to have a board specific mpisr.c when the interrupt
+   *  must be cleared.
+   *
+   *  If the generic mpisr.c satisifies your requirements, then
+   *  remove this routine from your target's shmsupp/mpisb.c file.
+   *  Then simply install the generic Shm_isr in the Shm_setvec
+   *  routine below.
+   */
+}
+
+/*  Shm_setvec
+ *
+ *  This driver routine sets the SHM interrupt vector to point to the
+ *  driver's SHM interrupt service routine.
+ *
+ *  Input parameters:  NONE
+ *
+ *  Output parameters: NONE
+ */
+
+void Shm_setvec( void )
+{
+  /* XXX: FIX ME!!! */
+}