2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org>

	* include/bsp.h: Split out tmtest27 support.
	* include/tm27.h: New.

3 files changed, 68 insertions, 48 deletions

diff --git a/c/src/lib/libbsp/mips/jmr3904/ChangeLog b/c/src/lib/libbsp/mips/jmr3904/ChangeLog
index eb0bb1cee8..2b4108aa11 100644
--- a/c/src/lib/libbsp/mips/jmr3904/ChangeLog
+++ b/c/src/lib/libbsp/mips/jmr3904/ChangeLog
@@ -1,3 +1,8 @@
+2004-04-22	Ralf Corsepius <ralf_corsepius@rtems.org>
+
+	* include/bsp.h: Split out tmtest27 support.
+	* include/tm27.h: New.
+
 2004-04-21	Ralf Corsepius <ralf_corsepius@rtems.org>
 
 	PR 613/bsps
diff --git a/c/src/lib/libbsp/mips/jmr3904/include/bsp.h b/c/src/lib/libbsp/mips/jmr3904/include/bsp.h
index 2d632062d9..ce7f4a78af 100644
--- a/c/src/lib/libbsp/mips/jmr3904/include/bsp.h
+++ b/c/src/lib/libbsp/mips/jmr3904/include/bsp.h
@@ -28,54 +28,6 @@ extern "C" {
 #include <rtems/clockdrv.h>
 #include <libcpu/tx3904.h>
 
-/*
- *  Define the interrupt mechanism for Time Test 27
- *
- *  NOTE: Following are for XXX and are board independent
- *
- */
-
-#define MUST_WAIT_FOR_INTERRUPT 1
-
-#if 0
-#define Install_tm27_vector( handler ) \
-    (void) set_vector( handler, TX3904_IRQ_SOFTWARE_1, 1 ); \
-
-#define Cause_tm27_intr() \
-    asm volatile ( "syscall 0x01" : : );
-
-#define CLOCK_VECTOR TX3904_IRQ_TMR0
-
-#define Clear_tm27_intr()
-
-#define Lower_tm27_intr()
-#else
-#define Install_tm27_vector( handler ) \
-    (void) set_vector( handler, TX3904_IRQ_TMR0, 1 ); \
-
-#define Cause_tm27_intr() \
-  do { \
-    uint32_t   _clicks = 20; \
-    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
-    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, _clicks ); \
-    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \
-    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 ); \
-    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR,   0xC0 ); \
-    *((volatile uint32_t*) 0xFFFFC01C) = 0x00000700; \
-  } while(0)
-
-#define Clear_tm27_intr() \
-  do { \
-    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x0001 ); \
-    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
-    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR,   0x00 ); \
-  } while(0)
-
-#define Lower_tm27_intr() \
-  mips_enable_in_interrupt_mask( 0xff01 );
-
-#endif
-
 /* Constants */
 
 /* miscellaneous stuff assumed to exist */
diff --git a/c/src/lib/libbsp/mips/jmr3904/include/tm27.h b/c/src/lib/libbsp/mips/jmr3904/include/tm27.h
new file mode 100644
index 0000000000..0130f51829
--- /dev/null
+++ b/c/src/lib/libbsp/mips/jmr3904/include/tm27.h
@@ -0,0 +1,63 @@
+/*
+ *  tm27.h
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#ifndef _TMTEST27
+#error "This is an RTEMS internal file you must not include directly."
+#endif
+
+#ifndef __tm27_h
+#define __tm27_h
+
+/*
+ *  Define the interrupt mechanism for Time Test 27
+ */
+
+#define MUST_WAIT_FOR_INTERRUPT 1
+
+#if 0
+#define Install_tm27_vector( handler ) \
+    (void) set_vector( handler, TX3904_IRQ_SOFTWARE_1, 1 ); \
+
+#define Cause_tm27_intr() \
+    asm volatile ( "syscall 0x01" : : );
+
+#define CLOCK_VECTOR TX3904_IRQ_TMR0
+
+#define Clear_tm27_intr()
+
+#define Lower_tm27_intr()
+#else
+#define Install_tm27_vector( handler ) \
+    (void) set_vector( handler, TX3904_IRQ_TMR0, 1 ); \
+
+#define Cause_tm27_intr() \
+  do { \
+    uint32_t   _clicks = 20; \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, _clicks ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR,   0xC0 ); \
+    *((volatile uint32_t*) 0xFFFFC01C) = 0x00000700; \
+  } while(0)
+
+#define Clear_tm27_intr() \
+  do { \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x0001 ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
+    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR,   0x00 ); \
+  } while(0)
+
+#define Lower_tm27_intr() \
+  mips_enable_in_interrupt_mask( 0xff01 );
+
+#endif
+
+#endif