1 files changed, 0 insertions, 48 deletions
diff --git a/c/src/lib/libbsp/mips/jmr3904/include/bsp.h b/c/src/lib/libbsp/mips/jmr3904/include/bsp.h
index 2d632062d9..ce7f4a78af 100644
--- a/c/src/lib/libbsp/mips/jmr3904/include/bsp.h
+++ b/c/src/lib/libbsp/mips/jmr3904/include/bsp.h
@@ -28,54 +28,6 @@ extern "C" {
 #include <rtems/clockdrv.h>
 #include <libcpu/tx3904.h>
 
-/*
- *  Define the interrupt mechanism for Time Test 27
- *
- *  NOTE: Following are for XXX and are board independent
- *
- */
-
-#define MUST_WAIT_FOR_INTERRUPT 1
-
-#if 0
-#define Install_tm27_vector( handler ) \
-    (void) set_vector( handler, TX3904_IRQ_SOFTWARE_1, 1 ); \
-
-#define Cause_tm27_intr() \
-    asm volatile ( "syscall 0x01" : : );
-
-#define CLOCK_VECTOR TX3904_IRQ_TMR0
-
-#define Clear_tm27_intr()
-
-#define Lower_tm27_intr()
-#else
-#define Install_tm27_vector( handler ) \
-    (void) set_vector( handler, TX3904_IRQ_TMR0, 1 ); \
-
-#define Cause_tm27_intr() \
-  do { \
-    uint32_t   _clicks = 20; \
-    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
-    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, _clicks ); \
-    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \
-    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 ); \
-    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR,   0xC0 ); \
-    *((volatile uint32_t*) 0xFFFFC01C) = 0x00000700; \
-  } while(0)
-
-#define Clear_tm27_intr() \
-  do { \
-    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x0001 ); \
-    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
-    TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR,   0x00 ); \
-  } while(0)
-
-#define Lower_tm27_intr() \
-  mips_enable_in_interrupt_mask( 0xff01 );
-
-#endif
-
 /* Constants */
 
 /* miscellaneous stuff assumed to exist */