New (Submission by Bruce Robinson <brucer@pmccorp.com>).

3 files changed, 379 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/mips/hurricane/liblnk/lnklib.S b/c/src/lib/libbsp/mips/hurricane/liblnk/lnklib.S
new file mode 100644
index 0000000000..0800e25078
--- /dev/null
+++ b/c/src/lib/libbsp/mips/hurricane/liblnk/lnklib.S
@@ -0,0 +1,62 @@
+/*
+ *  lnklib.S,v 1.4 1999/03/31 23:21:19 joel Exp
+ */
+
+#include <rtems/mips/iregdef.h>
+#include <rtems/mips/idtcpu.h>
+
+#define FRAME(name,frm_reg,offset,ret_reg)      \
+        .globl  name;                           \
+        .ent    name;                           \
+name:;                                          \
+        .frame  frm_reg,offset,ret_reg
+
+#define ENDFRAME(name)                          \
+        .end name
+
+#define PROM_LINK(name,entry)           \
+        .globl  name;                   \
+        .ent    name;                   \
+name:   la      $2,+entry;              \
+        j       $2;                     \
+        .end name
+
+#define	PROM_ENTRY(x)	(0xbfc00000+((x)*8))
+
+#define PROM_RESET	PROM_ENTRY(0)
+#define PROM_NOT_IMP	PROM_ENTRY(1)
+#define PROM_RESTART	PROM_ENTRY(2)
+#define PROM_REINIT	PROM_ENTRY(3)
+#define	PROM_GETCHAR	PROM_ENTRY(11)
+#define	PROM_PUTCHAR	PROM_ENTRY(12)
+#define	PROM_SHOWCHAR	PROM_ENTRY(13)
+#define	PROM_PRINTF	PROM_ENTRY(16)
+#define	PROM_RETURN	PROM_ENTRY(17)
+
+#define	PROM_RGETS	PROM_ENTRY(25)
+#define PROM_FLUSHCACHE	PROM_ENTRY(28)
+#define PROM_CLEARCACHE	PROM_ENTRY(29)
+#define PROM_SETJMP	PROM_ENTRY(30)
+#define PROM_LONGJMP	PROM_ENTRY(31)
+
+	.text
+
+PROM_LINK(idtsim_putchar, PROM_PUTCHAR)
+PROM_LINK(idtsim_getchar, PROM_GETCHAR)
+PROM_LINK(idtsim_showchar, PROM_SHOWCHAR)
+PROM_LINK(idtsim__exit, PROM_RETURN)
+PROM_LINK(idtsim_reinit, PROM_REINIT)
+PROM_LINK(idtsim_restart, PROM_RESTART)
+PROM_LINK(idtsim_reset, PROM_RESET)
+PROM_LINK(idtsim_promexit, PROM_RETURN)
+PROM_LINK(idtsim_setjmp, PROM_SETJMP)
+PROM_LINK(idtsim_longjmp, PROM_LONGJMP)
+
+FRAME(idtsim_init_sbrk,sp,0,ra)
+	j	ra
+ENDFRAME(idtsim_init_sbrk)
+
+FRAME(idtsim_init_file,sp,0,ra)
+	j	ra
+ENDFRAME(idtsim_init_file)
+
diff --git a/c/src/lib/libbsp/mips/hurricane/liblnk/pmon.S b/c/src/lib/libbsp/mips/hurricane/liblnk/pmon.S
new file mode 100644
index 0000000000..b84771bb74
--- /dev/null
+++ b/c/src/lib/libbsp/mips/hurricane/liblnk/pmon.S
@@ -0,0 +1,180 @@
+/*
+ * pmon.S -- low-level entry points into PMON monitor.
+ *
+ * Copyright (c) 1996, 1997 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#ifdef __mips16
+/* This file contains 32 bit assembly code.  */
+	.set nomips16
+#endif
+
+#if __mips < 3
+  /* This machine does not support 64-bit operations.  */
+  #define ADDU addu
+  #define SUBU subu
+#else
+  /* This machine supports 64-bit operations.  */
+  #define ADDU daddu
+  #define SUBU dsubu
+#endif
+
+#include "regs.S"
+
+	.text
+	.align	2
+
+#ifdef LSI
+  #define PMON_VECTOR 0xbfc00200
+#else
+  #define PMON_VECTOR 0xbfc00500
+#endif
+
+#ifndef __mips_eabi
+/* Provide named functions for entry into the monitor: */
+#define INDIRECT(name,index)				\
+	.globl	name;					\
+	.ent	name;					\
+	.set	noreorder;				\
+name:	la	$2,+(PMON_VECTOR+((index)*4));		\
+	lw	$2,0($2);				\
+	j	$2;					\
+	nop;						\
+	.set	reorder;				\
+	.end	name
+
+#else
+#define INDIRECT(name,index)				\
+	.globl	name;					\
+	.ent	name;					\
+	.set	noreorder;				\
+name:	la	$2,+(PMON_VECTOR+((index)*4));		\
+	lw	$2,0($2);				\
+	SUBU	sp,sp,0x40;				\
+	sd	ra,0x38(sp);				\
+	sd	fp,0x30(sp);				\
+	jal	$2;					\
+	move	fp,sp;					\
+	ld	ra,0x38(sp);				\
+	ld	fp,0x30(sp);				\
+	j	ra;					\
+	ADDU	sp,sp,0x40;				\
+	.set	reorder;				\
+	.end	name
+#endif
+
+
+/* The following magic numbers are for the slots into the PMON monitor */
+/* The first are used as the lo-level library run-time: */
+INDIRECT(mon_read,0)
+INDIRECT(mon_write,1)
+INDIRECT(mon_open,2)
+INDIRECT(mon_close,3)
+/* The following are useful monitor routines: */
+INDIRECT(mon_ioctl,4)
+INDIRECT(mon_printf,5)
+INDIRECT(mon_vsprintf,6)
+INDIRECT(mon_ttctl,7)
+INDIRECT(mon_cliexit,8)
+INDIRECT(mon_getenv,9)
+INDIRECT(mon_onintr,10)
+INDIRECT(mon_flush_cache,11)
+INDIRECT(mon_exception,12)
+INDIRECT(mon_fpgaconfig,21)
+
+#if 0
+
+/* The following routine is required by the "print()" function: */
+	.globl	pmon_outbyte
+	.ent	pmon_outbyte
+	.set	noreorder
+pmon_outbyte:
+	subu	sp,sp,0x20	/* allocate stack space for string */
+	sd	ra,0x18(sp)	/* stack return address */
+	sd	fp,0x10(sp)	/* stack frame-pointer */
+	move	fp,sp		/* take a copy of the stack pointer */
+	/* We leave so much space on the stack for the string (16
+	   characters), since the call to mon_printf seems to corrupt
+	   the 8bytes at offset 8 into the string/stack. */
+	sb	a0,0x00(sp)	/* character to print */
+	sb	z0,0x01(sp)	/* NUL terminator */
+	jal	mon_printf	/* and output the string */
+	move	a0,sp		/* take a copy of the string pointer {DELAY SLOT} */
+
+	move	sp,fp		/* recover stack pointer */
+	ld	ra,0x18(sp)	/* recover return address */
+	ld	fp,0x10(sp)	/* recover frame-pointer */
+	j	ra		/* return to the caller */
+	addu	sp,sp,0x20	/* dump the stack space {DELAY SLOT} */
+	.set	reorder
+	.end	pmon_outbyte
+
+/* The following routine is required by the "sbrk()" function: */
+	.globl	get_mem_info
+	.ent	get_mem_info
+	.set	noreorder
+get_mem_info:
+	# in:  a0 = pointer to 3 word structure
+	# out: void
+	subu	sp,sp,0x18	/* create some stack space */
+	sd	ra,0x00(sp)	/* stack return address */
+	sd	fp,0x08(sp)	/* stack frame-pointer */
+	sd	a0,0x10(sp)	/* stack structure pointer */
+	move	fp,sp		/* take a copy of the stack pointer */
+
+	# The monitor has already sized memory, but unfortunately we
+	# do not have access to the data location containing the
+	# memory size.
+
+	jal	__sizemem
+	nop
+
+	ld	a0,0x10(sp)	# recover structure pointer
+	sw	v0,0(a0)	# amount of memory available
+
+	# Deal with getting the cache size information:
+	mfc0	a1, C0_CONFIG
+	nop
+	nop
+	andi	a2,a1,0x7 << 9	# bits 11..9 for instruction cache size
+	sll	a2,a2,12 - 8
+	sw 	a2,4(a0)
+	andi	a2,a1,0x7 << 6	# bits 8..6 for data cache size
+	sll	a2,a2,12 - 5
+	sw 	a2,8(a0)	# data cache size
+	#
+	move	sp,fp		/* recover stack pointer */
+	ld	ra,0x00(sp)	/* recover return address */
+	ld	fp,0x08(sp)	/* recover frame-pointer */
+	j	ra		/* return to the caller */
+	addu	sp,sp,0x18	/* restore stack pointer {DELAY SLOT} */
+	.set	reorder
+	.end	get_mem_info
+
+#ifdef LSI
+
+# For the LSI MiniRISC board, we can safely assume that we have
+# at least one megabyte of RAM.
+
+	.globl	__sizemem
+	.ent	__sizemem
+__sizemem:
+	li	v0,0x100000
+	j	ra
+	.end	__sizemem
+#else
+
+#endif
+
+#endif
+/* EOF pmon.S */
diff --git a/c/src/lib/libbsp/mips/hurricane/liblnk/regs.S b/c/src/lib/libbsp/mips/hurricane/liblnk/regs.S
new file mode 100644
index 0000000000..1befa8dc79
--- /dev/null
+++ b/c/src/lib/libbsp/mips/hurricane/liblnk/regs.S
@@ -0,0 +1,137 @@
+/*
+ * regs.S -- standard MIPS register names.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/* Standard MIPS register names: */
+#define zero	$0
+#define z0	$0
+#define v0	$2
+#define v1	$3
+#define a0	$4
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define t5	$13
+#define t6	$14
+#define t7	$15
+#define s0	$16
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24
+#define t9	$25
+#define k0	$26	/* kernel private register 0 */
+#define k1	$27	/* kernel private register 1 */
+#define gp	$28	/* global data pointer */
+#define sp 	$29	/* stack-pointer */
+#define fp	$30	/* frame-pointer */
+#define ra	$31	/* return address */
+#define pc	$pc	/* pc, used on mips16 */
+
+#define fp0	$f0
+#define fp1	$f1
+
+/* Useful memory constants: */
+#define K0BASE		0x80000000
+#ifndef __mips64
+#define K1BASE		0xA0000000
+#else
+#define K1BASE		0xFFFFFFFFA0000000LL
+#endif
+
+#define PHYS_TO_K1(a)   ((unsigned)(a) | K1BASE)
+
+/* Standard Co-Processor 0 register numbers: */
+#define C0_COUNT	$9		/* Count Register */
+#define C0_SR		$12		/* Status Register */
+#define C0_CAUSE	$13		/* last exception description */
+#define C0_EPC		$14		/* Exception error address */
+#define C0_CONFIG	$16		/* CPU configuration */
+
+/* Standard Status Register bitmasks: */
+#define SR_CU1		0x20000000	/* Mark CP1 as usable */
+#define SR_FR		0x04000000	/* Enable MIPS III FP registers */
+#define SR_BEV		0x00400000	/* Controls location of exception vectors */
+#define SR_PE		0x00100000	/* Mark soft reset (clear parity error) */
+
+#define SR_KX		0x00000080	/* Kernel extended addressing enabled */
+#define SR_SX		0x00000040	/* Supervisor extended addressing enabled */
+#define SR_UX		0x00000020	/* User extended addressing enabled */
+
+/* Standard (R4000) cache operations. Taken from "MIPS R4000
+   Microprocessor User's Manual" 2nd edition: */
+
+#define CACHE_I		(0)	/* primary instruction */
+#define CACHE_D		(1)	/* primary data */
+#define CACHE_SI	(2)	/* secondary instruction */
+#define CACHE_SD	(3)	/* secondary data (or combined instruction/data) */
+
+#define INDEX_INVALIDATE		(0)	/* also encodes WRITEBACK if CACHE_D or CACHE_SD */
+#define INDEX_LOAD_TAG			(1)
+#define INDEX_STORE_TAG			(2)
+#define CREATE_DIRTY_EXCLUSIVE		(3)	/* CACHE_D and CACHE_SD only */
+#define HIT_INVALIDATE			(4)
+#define CACHE_FILL			(5)	/* CACHE_I only */
+#define HIT_WRITEBACK_INVALIDATE	(5)	/* CACHE_D and CACHE_SD only */
+#define HIT_WRITEBACK			(6)	/* CACHE_I, CACHE_D and CACHE_SD only */
+#define HIT_SET_VIRTUAL			(7)	/* CACHE_SI and CACHE_SD only */
+
+#define BUILD_CACHE_OP(o,c)		(((o) << 2) | (c))
+
+/* Individual cache operations: */
+#define INDEX_INVALIDATE_I		BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
+#define INDEX_WRITEBACK_INVALIDATE_D	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
+#define INDEX_INVALIDATE_SI             BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
+#define INDEX_WRITEBACK_INVALIDATE_SD	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
+
+#define INDEX_LOAD_TAG_I		BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
+#define INDEX_LOAD_TAG_D                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
+#define INDEX_LOAD_TAG_SI               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
+#define INDEX_LOAD_TAG_SD               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
+
+#define INDEX_STORE_TAG_I              	BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
+#define INDEX_STORE_TAG_D               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
+#define INDEX_STORE_TAG_SI              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
+#define INDEX_STORE_TAG_SD              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
+
+#define CREATE_DIRTY_EXCLUSIVE_D        BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
+#define CREATE_DIRTY_EXCLUSIVE_SD       BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
+
+#define HIT_INVALIDATE_I                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
+#define HIT_INVALIDATE_D                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
+#define HIT_INVALIDATE_SI               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
+#define HIT_INVALIDATE_SD               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
+
+#define CACHE_FILL_I                    BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
+#define HIT_WRITEBACK_INVALIDATE_D      BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
+#define HIT_WRITEBACK_INVALIDATE_SD     BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
+
+#define HIT_WRITEBACK_I                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
+#define HIT_WRITEBACK_D                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
+#define HIT_WRITEBACK_SD                BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
+
+#define HIT_SET_VIRTUAL_SI		BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
+#define HIT_SET_VIRTUAL_SD              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
+
+/*> EOF regs.S <*/