PR264 - Stopped the core dump by removing the bad instruction.

PR414 - Fixed the global interupt vector register.
Linker command file to have the boot code in the first 8K.
The chip select remap needed to be volatile.

2 files changed, 31 insertions, 20 deletions

diff --git a/c/src/lib/libbsp/m68k/ods68302/startup/cpuboot.c b/c/src/lib/libbsp/m68k/ods68302/startup/cpuboot.c
index 95b205d6fc..0e7130dc8c 100644
--- a/c/src/lib/libbsp/m68k/ods68302/startup/cpuboot.c
+++ b/c/src/lib/libbsp/m68k/ods68302/startup/cpuboot.c
@@ -68,8 +68,9 @@ void boot_phase_1()
   WRITE_BR(CSEL_2, CSEL_2_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
 #endif
   
-  m302.reg.gimr = m302.reg.ipr = m302.reg.imr = m302.reg.isr = 0;
-  
+  m302.reg.ipr = m302.reg.imr = m302.reg.isr = 0;
+  m302.reg.gimr = 0x0080;
+
   m302.reg.simode = 0;
 
   m302.reg.pacnt = CARD_PA_CONFIGURATION;
@@ -101,8 +102,8 @@ void boot_phase_2(void)
               LED_5_OFF, LED_6_OFF, LED_7_OFF, LED_8_OFF);
 #endif
   
-  WRITE_BR(CSEL_ROM, ROM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED);
-  WRITE_BR(CSEL_RAM, RAM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
+  WRITE_BR(CSEL_ROM, _ROM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED);
+  WRITE_BR(CSEL_RAM, _RAM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
   
 #if defined(LED_CONTROL)
   LED_CONTROL(LED_1_GREEN, LED_2_RED, LED_3_OFF, LED_4_OFF,
@@ -110,7 +111,7 @@ void boot_phase_2(void)
 #endif
 
   /* seems to want 2, looked at assember code output */
-  *(&stack + 2) |= ROM_BASE;
+  *((volatile rtems_unsigned32*) (&stack + 2)) |= ROM_BASE;
 }
 
 /*
diff --git a/c/src/lib/libbsp/m68k/ods68302/startup/linkcmds b/c/src/lib/libbsp/m68k/ods68302/startup/linkcmds
index a00c863e8e..c8d1660d74 100644
--- a/c/src/lib/libbsp/m68k/ods68302/startup/linkcmds
+++ b/c/src/lib/libbsp/m68k/ods68302/startup/linkcmds
@@ -14,6 +14,15 @@ _HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x10000;
 _StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
 
 /*
+ * Memory map.
+ */
+RAM_BASE = DEFINED(RAM_BASE) ? RAM_BASE : 0x00000000;
+RAM_SIZE = DEFINED(RAM_SIZE) ? RAM_SIZE : 0x00100000;
+ROM_BASE = DEFINED(ROM_BASE) ? ROM_BASE : 0x00C00000;
+ROM_SIZE = DEFINED(ROM_SIZE) ? ROM_SIZE : 0x00100000;
+MC68302_BASE = DEFINED(MC68302_BASE) ? MC68302_BASE : 0x00700000;
+
+/*
  * Declare on-board memory.
  */
 MEMORY {
@@ -21,22 +30,26 @@ MEMORY {
 }
 SECTIONS
 {
-	ram : {
-		. = .;
-	} >ram
-
-	.vtable :
+	.vtable RAM_BASE :
 	{
 		vtable_start = .;
 		*(.vtable)
 		evtable = .;
 	} >ram
 
-
         /*
          * Text, data and bss segments
          */
-        .text : {
+        .text ROM_BASE : {
+                /*
+                 * Needs to be first. 8K limit on CS0 at reset.
+                 */
+		*(.resettext);
+                *cpuboot.o(.text)
+
+                /*
+                 * The reset of the text is entered once CS0 is remapped.
+                 */
                 *(.text)
 
 		/*
@@ -114,8 +127,10 @@ SECTIONS
 
                  . = ALIGN (16);
                 PROVIDE (_etext = .);
-        } >ram
-        .data : {
+        } >rom
+
+        .data (ADDR(.vtable) + SIZEOF(.vtable)) : 
+          AT (ADDR(.text) + SIZEOF(.text)) {
                 PROVIDE (_copy_start = .);
                 *(.data)
 		*(.gnu.linkonce.d*)
@@ -125,7 +140,7 @@ SECTIONS
                 PROVIDE (_edata = .);
                 PROVIDE (_copy_end = .);
         } >ram
-        .bss : {
+        .bss (ADDR(.data) + SIZEOF(.data)) : {
                 _clear_start = .;
                 *(.bss)
                 *(COMMON)
@@ -181,11 +196,6 @@ SECTIONS
   /* These must appear regardless of  .  */
 }
 
-RAM_BASE = DEFINED(RAM_BASE) ? RAM_BASE : 0x00000000;
-RAM_SIZE = DEFINED(RAM_SIZE) ? RAM_SIZE : 0x00100000;
-ROM_BASE = DEFINED(ROM_BASE) ? ROM_BASE : 0x00C00000;
-ROM_SIZE = DEFINED(ROM_SIZE) ? ROM_SIZE : 0x00100000;
-MC68302_BASE = DEFINED(MC68302_BASE) ? MC68302_BASE : 0x00700000;
 m302 = MC68302_BASE;
 _VBR = ADDR(.vtable);		/* location of the VBR table (in RAM) */