Whitespace removal.

6 files changed, 131 insertions, 131 deletions

diff --git a/c/src/lib/libbsp/m68k/mcf52235/console/console.c b/c/src/lib/libbsp/m68k/mcf52235/console/console.c
index bb31854b65..dcacee4e1a 100644
--- a/c/src/lib/libbsp/m68k/mcf52235/console/console.c
+++ b/c/src/lib/libbsp/m68k/mcf52235/console/console.c
@@ -135,7 +135,7 @@ IntUartSet(int minor, int baud, int databits, int parity, int stopbits,
    Description : This provides the hardware-dependent portion of tcsetattr().
    value and sets it. At the moment this just sets the baud rate.
 
-   Note: The highest baudrate is 115200 as this stays within 
+   Note: The highest baudrate is 115200 as this stays within
    an error of +/- 5% at 25MHz processor clock
  ***************************************************************************/
 static int IntUartSetAttributes(int minor, const struct termios *t)
@@ -334,9 +334,9 @@ static void IntUartInitialize(void)
 /***************************************************************************
    Function : IntUartInterruptWrite
 
-   Description : This writes a single character to the appropriate uart 
+   Description : This writes a single character to the appropriate uart
    channel. This is either called during an interrupt or in the user's task
-   to initiate a transmit sequence. Calling this routine enables Tx 
+   to initiate a transmit sequence. Calling this routine enables Tx
    interrupts.
  ***************************************************************************/
 static int IntUartInterruptWrite(int minor, const char *buf, int len)
@@ -454,7 +454,7 @@ static int IntUartTaskRead(int minor)
 /***************************************************************************
    Function : IntUartPollRead
 
-   Description : This reads a character from the internal uart. It returns 
+   Description : This reads a character from the internal uart. It returns
    to the caller without blocking if not character is waiting.
  ***************************************************************************/
 static int IntUartPollRead(int minor)
@@ -468,8 +468,8 @@ static int IntUartPollRead(int minor)
 /***************************************************************************
    Function : IntUartPollWrite
 
-   Description : This writes out each character in the buffer to the 
-   appropriate internal uart channel waiting till each one is sucessfully 
+   Description : This writes out each character in the buffer to the
+   appropriate internal uart channel waiting till each one is sucessfully
    transmitted.
  ***************************************************************************/
 static int IntUartPollWrite(int minor, const char *buf, int len)
@@ -530,7 +530,7 @@ rtems_device_driver console_initialize(rtems_device_major_number major,
 /***************************************************************************
    Function : console_open
 
-   Description : This actually opens the device depending on the minor 
+   Description : This actually opens the device depending on the minor
    number set during initialisation. The device specific access routines are
    passed to termios when the devices is opened depending on whether it is
    polled or not.
diff --git a/c/src/lib/libbsp/m68k/mcf52235/include/bsp.h b/c/src/lib/libbsp/m68k/mcf52235/include/bsp.h
index 841cf6be0c..e494efd48e 100644
--- a/c/src/lib/libbsp/m68k/mcf52235/include/bsp.h
+++ b/c/src/lib/libbsp/m68k/mcf52235/include/bsp.h
@@ -1,7 +1,7 @@
 /*
  *  mcf52235 BSP header file
  */
- 
+
 #ifndef _BSP_H
 #define _BSP_H
 
@@ -22,9 +22,9 @@ extern "C" {
 /***************************************************************************/
 /**  Hardware data structure headers                                      **/
 #include <mcf5223x/mcf5223x.h>
-    
+
 /* Declare base address of peripherals area */
-#define __IPSBAR ((vuint8 *) 0x40000000)    
+#define __IPSBAR ((vuint8 *) 0x40000000)
 
 /***************************************************************************/
 /**  Network driver configuration                                         **/
diff --git a/c/src/lib/libbsp/m68k/mcf52235/start/start.S b/c/src/lib/libbsp/m68k/mcf52235/start/start.S
index 03a0091b1b..deaf9dcf78 100644
--- a/c/src/lib/libbsp/m68k/mcf52235/start/start.S
+++ b/c/src/lib/libbsp/m68k/mcf52235/start/start.S
@@ -22,7 +22,7 @@
 .extern _StackInit
 
 BEGIN_CODE
-    
+
     PUBLIC (_INTERRUPT_VECTOR)
 SYM(_INTERRUPT_VECTOR):
 
@@ -313,12 +313,12 @@ _cfm_msec:  .long   0x00000000
  */
 .align 4
     PUBLIC (_uhoh)
-SYM(_uhoh): 
+SYM(_uhoh):
     nop                     | Leave spot for breakpoint
-    stop    #0x2700         | Stop with interrupts disabled 
+    stop    #0x2700         | Stop with interrupts disabled
     bra.w   SYM(_uhoh)      | Stuck forever
 
-/* 
+/*
  * Spurious Interrupt Handler
  */
 .align 4
@@ -327,18 +327,18 @@ SYM(_spuriousInterrupt):
     addql   #1, SYM(_M68kSpuriousInterruptCount)
     rte
 
-/* 
+/*
  * Write VBR Register
  */
 .align 4
     PUBLIC (_wr_vbr)
 SYM(_wr_vbr):
     move.l  4(sp), d0
-    movec   d0, vbr 
+    movec   d0, vbr
     nop
-    rts	
+    rts
 
-/* 
+/*
  * Board startup
  * Disable watchdog, interrupts
  * Enable sram
@@ -359,7 +359,7 @@ SYM(start):
     add.l   #0x21, d0
     movec   d0, %rambar
 
-    /* Locate Stack Pointer */ 
+    /* Locate Stack Pointer */
     move.l  #_StackInit, sp
 
     /* Initialize FLASHBAR */
@@ -371,7 +371,7 @@ SYM(start):
 
 _continue_startup:
 
-    /* Locate Stack Pointer */ 
+    /* Locate Stack Pointer */
     move.l  #_StackInit, sp
 
     /* Save off intial D0 and D1 to RAM */
@@ -385,8 +385,8 @@ _continue_startup:
     jmp SYM(Init52235)
 
 _change_flashbar:
-    /* 
-    * The following sequence is used to set FLASHBAR. Since we may 
+    /*
+    * The following sequence is used to set FLASHBAR. Since we may
     * be executing from Flash, we must put the routine into SRAM for
     * execution and then jump back to Flash using the new address.
     *
@@ -402,7 +402,7 @@ _change_flashbar:
     * This routine is not necessary if the default Flash address
     * (0x00000000) is used.
     *
-    * If running in SRAM, change_flashbar should not be executed 
+    * If running in SRAM, change_flashbar should not be executed
     */
 
     move.l  #RamBase, a0
diff --git a/c/src/lib/libbsp/m68k/mcf52235/startup/bspgetcpuclockspeed.c b/c/src/lib/libbsp/m68k/mcf52235/startup/bspgetcpuclockspeed.c
index c3f99a26a5..2455074b4a 100644
--- a/c/src/lib/libbsp/m68k/mcf52235/startup/bspgetcpuclockspeed.c
+++ b/c/src/lib/libbsp/m68k/mcf52235/startup/bspgetcpuclockspeed.c
@@ -5,7 +5,7 @@
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
- * 
+ *
  *  $Id$
  */
 
diff --git a/c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c b/c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c
index 5f94178130..2e541b2f55 100644
--- a/c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c
+++ b/c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c
@@ -1,15 +1,15 @@
 /*********************************************************************
 * Initialisation Code for ColdFire MCF52235 Processor                *
 **********************************************************************
- Generated by ColdFire Initialisation Utility 2.10.8 
- Fri May 23 14:39:00 2008 
-   
- MicroAPL Ltd makes no warranties in respect of the suitability 
- of this code for any particular purpose, and accepts 
- no liability for any loss arising out of its use. The person or  
- persons making use of this file must make the final evaluation 
- as to its suitability and correctness for a particular application. 
-   
+ Generated by ColdFire Initialisation Utility 2.10.8
+ Fri May 23 14:39:00 2008
+
+ MicroAPL Ltd makes no warranties in respect of the suitability
+ of this code for any particular purpose, and accepts
+ no liability for any loss arising out of its use. The person or
+ persons making use of this file must make the final evaluation
+ as to its suitability and correctness for a particular application.
+
 */
 
 /* Processor/internal bus clocked at 60.00 MHz */
@@ -112,11 +112,11 @@ static void disable_watchdog_timer(void)
 **********************************************************************/
 static void init_clock_config(void)
 {
-  /* Clock source is 25.0000 MHz external crystal 
-     Clock mode: Normal PLL mode 
-     Processor/Bus clock frequency = 60.00 MHz 
-     Loss of clock detection disabled 
-     Reset on loss of lock disabled 
+  /* Clock source is 25.0000 MHz external crystal
+     Clock mode: Normal PLL mode
+     Processor/Bus clock frequency = 60.00 MHz
+     Loss of clock detection disabled
+     Reset on loss of lock disabled
    */
 
   /* Divide 25.0000 MHz clock to get 5.00 MHz PLL input clock */
@@ -137,10 +137,10 @@ static void init_clock_config(void)
 **********************************************************************/
 static void init_ipsbar(void)
 {
-  /* Base address of internal peripherals (IPSBAR) = 0x40000000 
+  /* Base address of internal peripherals (IPSBAR) = 0x40000000
 
-     Note: Processor powers up with IPS base address = 0x40000000 
-     Write to IPS base + 0x00000000 to set new value 
+     Note: Processor powers up with IPS base address = 0x40000000
+     Write to IPS base + 0x00000000 to set new value
    */
   *(vuint32 *) 0x40000000 = (vuint32) __IPSBAR + 1;     /* +1 for Enable */
 }
@@ -150,27 +150,27 @@ static void init_ipsbar(void)
 **********************************************************************/
 static void init_flash_controller(void)
 {
-  /* Internal Flash module enabled, address = $00000000 
-     Flash state machine clock = 197.37 kHz 
-     All access types except CPU space/interrupt acknowledge cycle allowed 
-     Flash is Write-Protected 
-     All interrupts disabled 
+  /* Internal Flash module enabled, address = $00000000
+     Flash state machine clock = 197.37 kHz
+     All access types except CPU space/interrupt acknowledge cycle allowed
+     Flash is Write-Protected
+     All interrupts disabled
    */
   MCF_CFM_CFMCLKD = MCF_CFM_CFMCLKD_PRDIV8 | MCF_CFM_CFMCLKD_DIV(0x12);
   MCF_CFM_CFMMCR = 0;
 
-  /* WARNING: Setting FLASHBAR[6]=1 in order to turn off address speculation 
-     This is a workaround for a hardware problem whereby a speculative 
-     access to the Flash occuring at the same time as an SRAM access 
-     can return corrupt data. 
+  /* WARNING: Setting FLASHBAR[6]=1 in order to turn off address speculation
+     This is a workaround for a hardware problem whereby a speculative
+     access to the Flash occuring at the same time as an SRAM access
+     can return corrupt data.
 
-     This workaround can result in a 4% - 9% performance penalty. Other workarounds 
-     are possible for certain applications. 
+     This workaround can result in a 4% - 9% performance penalty. Other workarounds
+     are possible for certain applications.
 
-     For example, if you know that you will not be using the top 32 KB of the Flash  
-     you can place the SRAM base address at 0x20038000 
+     For example, if you know that you will not be using the top 32 KB of the Flash
+     you can place the SRAM base address at 0x20038000
 
-     See Device Errata for further details 
+     See Device Errata for further details
    */
   asm("move.l   #0x00000161,%d0");
   asm("movec    %d0,%FLASHBAR");
@@ -211,13 +211,13 @@ static void init_flexcan(void)
 **********************************************************************/
 static void init_bus_config(void)
 {
-  /* Use round robin arbitration scheme 
-     Assigned priorities (highest first): 
-     Ethernet 
-     DMA Controller 
-     ColdFire Core 
-     DMA bandwidth control disabled 
-     Park on last active bus master 
+  /* Use round robin arbitration scheme
+     Assigned priorities (highest first):
+     Ethernet
+     DMA Controller
+     ColdFire Core
+     DMA bandwidth control disabled
+     Park on last active bus master
    */
   MCF_SCM_MPARK = MCF_SCM_MPARK_M3PRTY(0x3) |
     MCF_SCM_MPARK_M2PRTY(0x2) | (0x1 << 16);
@@ -228,9 +228,9 @@ static void init_bus_config(void)
 **********************************************************************/
 static void init_sram(void)
 {
-  /* Internal SRAM module enabled, address = $20000000 
-     DMA access to SRAM block disabled 
-     All access types (supervisor and user) allowed 
+  /* Internal SRAM module enabled, address = $20000000
+     DMA access to SRAM block disabled
+     All access types (supervisor and user) allowed
    */
   asm("move.l   #0x20000001,%d0");
   asm("movec    %d0,%RAMBAR");
@@ -241,8 +241,8 @@ static void init_sram(void)
 **********************************************************************/
 static void init_power_management(void)
 {
-  /* On executing STOP instruction, processor enters RUN mode 
-     Mode is exited when an interrupt of level 1 or higher is received 
+  /* On executing STOP instruction, processor enters RUN mode
+     Mode is exited when an interrupt of level 1 or higher is received
    */
   MCF_PMM_LPICR = MCF_PMM_LPICR_ENBSTOP;
   MCF_PMM_LPCR = MCF_PMM_LPCR_LPMD_RUN;
@@ -279,12 +279,12 @@ static void init_dma_timers(void)
 **********************************************************************/
 static void init_gp_timer(void)
 {
-  /*   
-     GPT disabled (GPTASCR1[GPTEN] = 0) 
-     Channel 0 configured as GPIO input 
-     Channel 1 configured as GPIO input 
-     Channel 2 configured as GPIO input 
-     Channel 3 configured as GPIO input 
+  /*
+     GPT disabled (GPTASCR1[GPTEN] = 0)
+     Channel 0 configured as GPIO input
+     Channel 1 configured as GPIO input
+     Channel 2 configured as GPIO input
+     Channel 3 configured as GPIO input
    */
   MCF_GPT_GPTSCR1 = 0;
   MCF_GPT_GPTDDR = 0;
@@ -325,14 +325,14 @@ static void init_watchdog_timer(void)
 **********************************************************************/
 static void init_interrupt_controller(void)
 {
-  /* Configured interrupt sources in order of priority... 
-     Level 7:  External interrupt /IRQ7, (initially masked) 
-     Level 6:  External interrupt /IRQ6, (initially masked) 
-     Level 5:  External interrupt /IRQ5, (initially masked) 
-     Level 4:  External interrupt /IRQ4, (initially masked) 
-     Level 3:  External interrupt /IRQ3, (initially masked) 
-     Level 2:  External interrupt /IRQ2, (initially masked) 
-     Level 1:  External interrupt /IRQ1, (initially masked) 
+  /* Configured interrupt sources in order of priority...
+     Level 7:  External interrupt /IRQ7, (initially masked)
+     Level 6:  External interrupt /IRQ6, (initially masked)
+     Level 5:  External interrupt /IRQ5, (initially masked)
+     Level 4:  External interrupt /IRQ4, (initially masked)
+     Level 3:  External interrupt /IRQ3, (initially masked)
+     Level 2:  External interrupt /IRQ2, (initially masked)
+     Level 1:  External interrupt /IRQ1, (initially masked)
    */
   MCF_INTC0_ICR1 = 0;
   MCF_INTC0_ICR2 = 0;
@@ -426,8 +426,8 @@ static void init_interrupt_controller(void)
 **********************************************************************/
 static void init_pin_assignments(void)
 {
-  /* Pin assignments for port NQ 
-     Pins NQ7-NQ1 : EdgePort GPIO/IRQ 
+  /* Pin assignments for port NQ
+     Pins NQ7-NQ1 : EdgePort GPIO/IRQ
    */
   MCF_GPIO_DDRNQ = 0;
   MCF_GPIO_PNQPAR = MCF_GPIO_PNQPAR_PNQPAR7(0x1) |
@@ -437,8 +437,8 @@ static void init_pin_assignments(void)
     MCF_GPIO_PNQPAR_PNQPAR3(0x1) |
     MCF_GPIO_PNQPAR_PNQPAR2(0x1) | MCF_GPIO_PNQPAR_PNQPAR1(0x1);
 
-  /* Pin assignments for port GP 
-     Pins PG7-PG0 : EdgePort GPIO/IRQ 
+  /* Pin assignments for port GP
+     Pins PG7-PG0 : EdgePort GPIO/IRQ
    */
   MCF_GPIO_DDRGP = 0;
   MCF_GPIO_PGPPAR = MCF_GPIO_PGPPAR_PGPPAR7 |
@@ -449,16 +449,16 @@ static void init_pin_assignments(void)
     MCF_GPIO_PGPPAR_PGPPAR2 |
     MCF_GPIO_PGPPAR_PGPPAR1 | MCF_GPIO_PGPPAR_PGPPAR0;
 
-  /* Pin assignments for port DD 
-     Pin DD7 : DDATA[3] 
-     Pin DD6 : DDATA[2] 
-     Pin DD5 : DDATA[1] 
-     Pin DD4 : DDATA[0] 
-     Pin DD3 : PST[3] 
-     Pin DD2 : PST[2] 
-     Pin DD1 : PST[1] 
-     Pin DD0 : PST[0] 
-     CCON[PSTEN] = 1 to enable PST/DDATA function 
+  /* Pin assignments for port DD
+     Pin DD7 : DDATA[3]
+     Pin DD6 : DDATA[2]
+     Pin DD5 : DDATA[1]
+     Pin DD4 : DDATA[0]
+     Pin DD3 : PST[3]
+     Pin DD2 : PST[2]
+     Pin DD1 : PST[1]
+     Pin DD0 : PST[0]
+     CCON[PSTEN] = 1 to enable PST/DDATA function
    */
   MCF_GPIO_DDRDD = 0;
   MCF_GPIO_PDDPAR = MCF_GPIO_PDDPAR_PDDPAR7 |
@@ -470,75 +470,75 @@ static void init_pin_assignments(void)
     MCF_GPIO_PDDPAR_PDDPAR1 | MCF_GPIO_PDDPAR_PDDPAR0;
   MCF_CIM_CCON = 0x0021;
 
-  /* Pin assignments for port AN 
-     Pins are all GPIO inputs 
+  /* Pin assignments for port AN
+     Pins are all GPIO inputs
    */
   MCF_GPIO_DDRAN = 0;
   MCF_GPIO_PANPAR = 0;
 
-  /* Pin assignments for port AS 
-     Pins are all GPIO inputs 
+  /* Pin assignments for port AS
+     Pins are all GPIO inputs
    */
   MCF_GPIO_DDRAS = 0;
   MCF_GPIO_PASPAR = 0;
 
-  /* Pin assignments for port LD 
-     Pins are all GPIO inputs 
+  /* Pin assignments for port LD
+     Pins are all GPIO inputs
    */
   MCF_GPIO_DDRLD = 0;
   MCF_GPIO_PLDPAR = 0;
 
-  /* Pin assignments for port QS 
-     Pins are all GPIO inputs 
+  /* Pin assignments for port QS
+     Pins are all GPIO inputs
    */
   MCF_GPIO_DDRQS = 0;
   MCF_GPIO_PQSPAR = 0;
 
-  /* Pin assignments for port TA 
-     Pins are all GPIO inputs 
+  /* Pin assignments for port TA
+     Pins are all GPIO inputs
    */
   MCF_GPIO_DDRTA = 0;
   MCF_GPIO_PTAPAR = 0;
 
-  /* Pin assignments for port TC 
-     Pins are all GPIO inputs 
+  /* Pin assignments for port TC
+     Pins are all GPIO inputs
    */
   MCF_GPIO_DDRTC = 0;
   MCF_GPIO_PTCPAR = 0;
 
-  /* Pin assignments for port TD 
-     Pins are all GPIO inputs 
+  /* Pin assignments for port TD
+     Pins are all GPIO inputs
    */
   MCF_GPIO_DDRTD = 0;
   MCF_GPIO_PTDPAR = 0;
 
-  /* Pin assignments for port UA 
-     Pin UA3 : UART 0 clear-to-send, UCTS0 
-     Pin UA2 : UART 0 request-to-send, URTS0 
-     Pin UA1 : UART 0 receive data, URXD0 
-     Pin UA0 : UART 0 transmit data, UTXD0 
+  /* Pin assignments for port UA
+     Pin UA3 : UART 0 clear-to-send, UCTS0
+     Pin UA2 : UART 0 request-to-send, URTS0
+     Pin UA1 : UART 0 receive data, URXD0
+     Pin UA0 : UART 0 transmit data, UTXD0
    */
   MCF_GPIO_DDRUA = 0;
   MCF_GPIO_PUAPAR = MCF_GPIO_PUAPAR_PUAPAR3(0x1) |
     MCF_GPIO_PUAPAR_PUAPAR2(0x1) |
     MCF_GPIO_PUAPAR_PUAPAR1(0x1) | MCF_GPIO_PUAPAR_PUAPAR0(0x1);
 
-  /* Pin assignments for port UB 
-     Pin UB3 : UART 1 clear-to-send, UCTS1 
-     Pin UB2 : UART 1 request-to-send, URTS1 
-     Pin UB1 : UART 1 receive data, URXD1 
-     Pin UB0 : UART 1 transmit data, UTXD1 
+  /* Pin assignments for port UB
+     Pin UB3 : UART 1 clear-to-send, UCTS1
+     Pin UB2 : UART 1 request-to-send, URTS1
+     Pin UB1 : UART 1 receive data, URXD1
+     Pin UB0 : UART 1 transmit data, UTXD1
    */
   MCF_GPIO_DDRUB = 0;
   MCF_GPIO_PUBPAR = MCF_GPIO_PUBPAR_PUBPAR3(0x1) |
     MCF_GPIO_PUBPAR_PUBPAR2(0x1) |
     MCF_GPIO_PUBPAR_PUBPAR1(0x1) | MCF_GPIO_PUBPAR_PUBPAR0(0x1);
 
-  /* Pin assignments for port UC 
-     Pin UC3 : UART 2 clear-to-send, UCTS2 
-     Pin UC2 : UART 2 request-to-send, URTS2 
-     Pin UC1 : UART 2 receive data, URXD2 
-     Pin UC0 : UART 2 transmit data, UTXD2 
+  /* Pin assignments for port UC
+     Pin UC3 : UART 2 clear-to-send, UCTS2
+     Pin UC2 : UART 2 request-to-send, URTS2
+     Pin UC1 : UART 2 receive data, URXD2
+     Pin UC0 : UART 2 transmit data, UTXD2
    */
   MCF_GPIO_DDRUC = 0;
   MCF_GPIO_PUCPAR = MCF_GPIO_PUCPAR_PUCPAR3 |
diff --git a/c/src/lib/libbsp/m68k/mcf52235/startup/init52235.c b/c/src/lib/libbsp/m68k/mcf52235/startup/init52235.c
index 9cce53feae..77a07edc79 100644
--- a/c/src/lib/libbsp/m68k/mcf52235/startup/init52235.c
+++ b/c/src/lib/libbsp/m68k/mcf52235/startup/init52235.c
@@ -30,13 +30,13 @@ void Init52235(void)
   register uint32_t *dp, *sp;
   register uint8_t *dbp, *sbp;
 
-  /* 
+  /*
    * Initialize the hardware
    */
   init_main();
 
-  /* 
-   * Copy the vector table to RAM 
+  /*
+   * Copy the vector table to RAM
    */
 
   if (_VBR != _INTERRUPT_VECTOR) {
@@ -49,8 +49,8 @@ void Init52235(void)
 
   _wr_vbr((uint32_t) _VBR);
 
-  /* 
-   * Move initialized data from ROM to RAM. 
+  /*
+   * Move initialized data from ROM to RAM.
    */
   if (_data_src_start != _data_dest_start) {
     dbp = (uint8_t *) _data_dest_start;
@@ -60,8 +60,8 @@ void Init52235(void)
       *dbp++ = *sbp++;
   }
 
-  /* 
-   * Zero uninitialized data 
+  /*
+   * Zero uninitialized data
    */
 
   if (_clear_start != _clear_end) {