diff options
Diffstat (limited to 'c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c')
| -rw-r--r-- | c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c | 200 |
1 files changed, 100 insertions, 100 deletions
diff --git a/c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c b/c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c index 5f94178130..2e541b2f55 100644 --- a/c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c +++ b/c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c @@ -1,15 +1,15 @@ /********************************************************************* * Initialisation Code for ColdFire MCF52235 Processor * ********************************************************************** - Generated by ColdFire Initialisation Utility 2.10.8 - Fri May 23 14:39:00 2008 - - MicroAPL Ltd makes no warranties in respect of the suitability - of this code for any particular purpose, and accepts - no liability for any loss arising out of its use. The person or - persons making use of this file must make the final evaluation - as to its suitability and correctness for a particular application. - + Generated by ColdFire Initialisation Utility 2.10.8 + Fri May 23 14:39:00 2008 + + MicroAPL Ltd makes no warranties in respect of the suitability + of this code for any particular purpose, and accepts + no liability for any loss arising out of its use. The person or + persons making use of this file must make the final evaluation + as to its suitability and correctness for a particular application. + */ /* Processor/internal bus clocked at 60.00 MHz */ @@ -112,11 +112,11 @@ static void disable_watchdog_timer(void) **********************************************************************/ static void init_clock_config(void) { - /* Clock source is 25.0000 MHz external crystal - Clock mode: Normal PLL mode - Processor/Bus clock frequency = 60.00 MHz - Loss of clock detection disabled - Reset on loss of lock disabled + /* Clock source is 25.0000 MHz external crystal + Clock mode: Normal PLL mode + Processor/Bus clock frequency = 60.00 MHz + Loss of clock detection disabled + Reset on loss of lock disabled */ /* Divide 25.0000 MHz clock to get 5.00 MHz PLL input clock */ @@ -137,10 +137,10 @@ static void init_clock_config(void) **********************************************************************/ static void init_ipsbar(void) { - /* Base address of internal peripherals (IPSBAR) = 0x40000000 + /* Base address of internal peripherals (IPSBAR) = 0x40000000 - Note: Processor powers up with IPS base address = 0x40000000 - Write to IPS base + 0x00000000 to set new value + Note: Processor powers up with IPS base address = 0x40000000 + Write to IPS base + 0x00000000 to set new value */ *(vuint32 *) 0x40000000 = (vuint32) __IPSBAR + 1; /* +1 for Enable */ } @@ -150,27 +150,27 @@ static void init_ipsbar(void) **********************************************************************/ static void init_flash_controller(void) { - /* Internal Flash module enabled, address = $00000000 - Flash state machine clock = 197.37 kHz - All access types except CPU space/interrupt acknowledge cycle allowed - Flash is Write-Protected - All interrupts disabled + /* Internal Flash module enabled, address = $00000000 + Flash state machine clock = 197.37 kHz + All access types except CPU space/interrupt acknowledge cycle allowed + Flash is Write-Protected + All interrupts disabled */ MCF_CFM_CFMCLKD = MCF_CFM_CFMCLKD_PRDIV8 | MCF_CFM_CFMCLKD_DIV(0x12); MCF_CFM_CFMMCR = 0; - /* WARNING: Setting FLASHBAR[6]=1 in order to turn off address speculation - This is a workaround for a hardware problem whereby a speculative - access to the Flash occuring at the same time as an SRAM access - can return corrupt data. + /* WARNING: Setting FLASHBAR[6]=1 in order to turn off address speculation + This is a workaround for a hardware problem whereby a speculative + access to the Flash occuring at the same time as an SRAM access + can return corrupt data. - This workaround can result in a 4% - 9% performance penalty. Other workarounds - are possible for certain applications. + This workaround can result in a 4% - 9% performance penalty. Other workarounds + are possible for certain applications. - For example, if you know that you will not be using the top 32 KB of the Flash - you can place the SRAM base address at 0x20038000 + For example, if you know that you will not be using the top 32 KB of the Flash + you can place the SRAM base address at 0x20038000 - See Device Errata for further details + See Device Errata for further details */ asm("move.l #0x00000161,%d0"); asm("movec %d0,%FLASHBAR"); @@ -211,13 +211,13 @@ static void init_flexcan(void) **********************************************************************/ static void init_bus_config(void) { - /* Use round robin arbitration scheme - Assigned priorities (highest first): - Ethernet - DMA Controller - ColdFire Core - DMA bandwidth control disabled - Park on last active bus master + /* Use round robin arbitration scheme + Assigned priorities (highest first): + Ethernet + DMA Controller + ColdFire Core + DMA bandwidth control disabled + Park on last active bus master */ MCF_SCM_MPARK = MCF_SCM_MPARK_M3PRTY(0x3) | MCF_SCM_MPARK_M2PRTY(0x2) | (0x1 << 16); @@ -228,9 +228,9 @@ static void init_bus_config(void) **********************************************************************/ static void init_sram(void) { - /* Internal SRAM module enabled, address = $20000000 - DMA access to SRAM block disabled - All access types (supervisor and user) allowed + /* Internal SRAM module enabled, address = $20000000 + DMA access to SRAM block disabled + All access types (supervisor and user) allowed */ asm("move.l #0x20000001,%d0"); asm("movec %d0,%RAMBAR"); @@ -241,8 +241,8 @@ static void init_sram(void) **********************************************************************/ static void init_power_management(void) { - /* On executing STOP instruction, processor enters RUN mode - Mode is exited when an interrupt of level 1 or higher is received + /* On executing STOP instruction, processor enters RUN mode + Mode is exited when an interrupt of level 1 or higher is received */ MCF_PMM_LPICR = MCF_PMM_LPICR_ENBSTOP; MCF_PMM_LPCR = MCF_PMM_LPCR_LPMD_RUN; @@ -279,12 +279,12 @@ static void init_dma_timers(void) **********************************************************************/ static void init_gp_timer(void) { - /* - GPT disabled (GPTASCR1[GPTEN] = 0) - Channel 0 configured as GPIO input - Channel 1 configured as GPIO input - Channel 2 configured as GPIO input - Channel 3 configured as GPIO input + /* + GPT disabled (GPTASCR1[GPTEN] = 0) + Channel 0 configured as GPIO input + Channel 1 configured as GPIO input + Channel 2 configured as GPIO input + Channel 3 configured as GPIO input */ MCF_GPT_GPTSCR1 = 0; MCF_GPT_GPTDDR = 0; @@ -325,14 +325,14 @@ static void init_watchdog_timer(void) **********************************************************************/ static void init_interrupt_controller(void) { - /* Configured interrupt sources in order of priority... - Level 7: External interrupt /IRQ7, (initially masked) - Level 6: External interrupt /IRQ6, (initially masked) - Level 5: External interrupt /IRQ5, (initially masked) - Level 4: External interrupt /IRQ4, (initially masked) - Level 3: External interrupt /IRQ3, (initially masked) - Level 2: External interrupt /IRQ2, (initially masked) - Level 1: External interrupt /IRQ1, (initially masked) + /* Configured interrupt sources in order of priority... + Level 7: External interrupt /IRQ7, (initially masked) + Level 6: External interrupt /IRQ6, (initially masked) + Level 5: External interrupt /IRQ5, (initially masked) + Level 4: External interrupt /IRQ4, (initially masked) + Level 3: External interrupt /IRQ3, (initially masked) + Level 2: External interrupt /IRQ2, (initially masked) + Level 1: External interrupt /IRQ1, (initially masked) */ MCF_INTC0_ICR1 = 0; MCF_INTC0_ICR2 = 0; @@ -426,8 +426,8 @@ static void init_interrupt_controller(void) **********************************************************************/ static void init_pin_assignments(void) { - /* Pin assignments for port NQ - Pins NQ7-NQ1 : EdgePort GPIO/IRQ + /* Pin assignments for port NQ + Pins NQ7-NQ1 : EdgePort GPIO/IRQ */ MCF_GPIO_DDRNQ = 0; MCF_GPIO_PNQPAR = MCF_GPIO_PNQPAR_PNQPAR7(0x1) | @@ -437,8 +437,8 @@ static void init_pin_assignments(void) MCF_GPIO_PNQPAR_PNQPAR3(0x1) | MCF_GPIO_PNQPAR_PNQPAR2(0x1) | MCF_GPIO_PNQPAR_PNQPAR1(0x1); - /* Pin assignments for port GP - Pins PG7-PG0 : EdgePort GPIO/IRQ + /* Pin assignments for port GP + Pins PG7-PG0 : EdgePort GPIO/IRQ */ MCF_GPIO_DDRGP = 0; MCF_GPIO_PGPPAR = MCF_GPIO_PGPPAR_PGPPAR7 | @@ -449,16 +449,16 @@ static void init_pin_assignments(void) MCF_GPIO_PGPPAR_PGPPAR2 | MCF_GPIO_PGPPAR_PGPPAR1 | MCF_GPIO_PGPPAR_PGPPAR0; - /* Pin assignments for port DD - Pin DD7 : DDATA[3] - Pin DD6 : DDATA[2] - Pin DD5 : DDATA[1] - Pin DD4 : DDATA[0] - Pin DD3 : PST[3] - Pin DD2 : PST[2] - Pin DD1 : PST[1] - Pin DD0 : PST[0] - CCON[PSTEN] = 1 to enable PST/DDATA function + /* Pin assignments for port DD + Pin DD7 : DDATA[3] + Pin DD6 : DDATA[2] + Pin DD5 : DDATA[1] + Pin DD4 : DDATA[0] + Pin DD3 : PST[3] + Pin DD2 : PST[2] + Pin DD1 : PST[1] + Pin DD0 : PST[0] + CCON[PSTEN] = 1 to enable PST/DDATA function */ MCF_GPIO_DDRDD = 0; MCF_GPIO_PDDPAR = MCF_GPIO_PDDPAR_PDDPAR7 | @@ -470,75 +470,75 @@ static void init_pin_assignments(void) MCF_GPIO_PDDPAR_PDDPAR1 | MCF_GPIO_PDDPAR_PDDPAR0; MCF_CIM_CCON = 0x0021; - /* Pin assignments for port AN - Pins are all GPIO inputs + /* Pin assignments for port AN + Pins are all GPIO inputs */ MCF_GPIO_DDRAN = 0; MCF_GPIO_PANPAR = 0; - /* Pin assignments for port AS - Pins are all GPIO inputs + /* Pin assignments for port AS + Pins are all GPIO inputs */ MCF_GPIO_DDRAS = 0; MCF_GPIO_PASPAR = 0; - /* Pin assignments for port LD - Pins are all GPIO inputs + /* Pin assignments for port LD + Pins are all GPIO inputs */ MCF_GPIO_DDRLD = 0; MCF_GPIO_PLDPAR = 0; - /* Pin assignments for port QS - Pins are all GPIO inputs + /* Pin assignments for port QS + Pins are all GPIO inputs */ MCF_GPIO_DDRQS = 0; MCF_GPIO_PQSPAR = 0; - /* Pin assignments for port TA - Pins are all GPIO inputs + /* Pin assignments for port TA + Pins are all GPIO inputs */ MCF_GPIO_DDRTA = 0; MCF_GPIO_PTAPAR = 0; - /* Pin assignments for port TC - Pins are all GPIO inputs + /* Pin assignments for port TC + Pins are all GPIO inputs */ MCF_GPIO_DDRTC = 0; MCF_GPIO_PTCPAR = 0; - /* Pin assignments for port TD - Pins are all GPIO inputs + /* Pin assignments for port TD + Pins are all GPIO inputs */ MCF_GPIO_DDRTD = 0; MCF_GPIO_PTDPAR = 0; - /* Pin assignments for port UA - Pin UA3 : UART 0 clear-to-send, UCTS0 - Pin UA2 : UART 0 request-to-send, URTS0 - Pin UA1 : UART 0 receive data, URXD0 - Pin UA0 : UART 0 transmit data, UTXD0 + /* Pin assignments for port UA + Pin UA3 : UART 0 clear-to-send, UCTS0 + Pin UA2 : UART 0 request-to-send, URTS0 + Pin UA1 : UART 0 receive data, URXD0 + Pin UA0 : UART 0 transmit data, UTXD0 */ MCF_GPIO_DDRUA = 0; MCF_GPIO_PUAPAR = MCF_GPIO_PUAPAR_PUAPAR3(0x1) | MCF_GPIO_PUAPAR_PUAPAR2(0x1) | MCF_GPIO_PUAPAR_PUAPAR1(0x1) | MCF_GPIO_PUAPAR_PUAPAR0(0x1); - /* Pin assignments for port UB - Pin UB3 : UART 1 clear-to-send, UCTS1 - Pin UB2 : UART 1 request-to-send, URTS1 - Pin UB1 : UART 1 receive data, URXD1 - Pin UB0 : UART 1 transmit data, UTXD1 + /* Pin assignments for port UB + Pin UB3 : UART 1 clear-to-send, UCTS1 + Pin UB2 : UART 1 request-to-send, URTS1 + Pin UB1 : UART 1 receive data, URXD1 + Pin UB0 : UART 1 transmit data, UTXD1 */ MCF_GPIO_DDRUB = 0; MCF_GPIO_PUBPAR = MCF_GPIO_PUBPAR_PUBPAR3(0x1) | MCF_GPIO_PUBPAR_PUBPAR2(0x1) | MCF_GPIO_PUBPAR_PUBPAR1(0x1) | MCF_GPIO_PUBPAR_PUBPAR0(0x1); - /* Pin assignments for port UC - Pin UC3 : UART 2 clear-to-send, UCTS2 - Pin UC2 : UART 2 request-to-send, URTS2 - Pin UC1 : UART 2 receive data, URXD2 - Pin UC0 : UART 2 transmit data, UTXD2 + /* Pin assignments for port UC + Pin UC3 : UART 2 clear-to-send, UCTS2 + Pin UC2 : UART 2 request-to-send, URTS2 + Pin UC1 : UART 2 receive data, URXD2 + Pin UC0 : UART 2 transmit data, UTXD2 */ MCF_GPIO_DDRUC = 0; MCF_GPIO_PUCPAR = MCF_GPIO_PUCPAR_PUCPAR3 | |