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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1997-09-18 16:01:52 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1997-09-18 16:01:52 +0000 |
| commit | 6b4ca3125e022552c9b8e3747987267092efaf9e (patch) | |
| tree | b97aae323eb7a762f3e90f2e4886578f230995b2 /c/src/lib/libbsp/m68k/gen68360/startup/init68360.c | |
| parent | updated (diff) | |
| download | rtems-6b4ca3125e022552c9b8e3747987267092efaf9e.tar.bz2 | |
Merged changes from Eric Norum:
Enable 68360 watchdog. The watchdog control register is a
`write-once' register, so the watchdog has to be enabled in the boot
roms if it is to be used at all. To make the change transparent I
added a default feed of the watchdog to the clock interrupt handler.
This can be overridden if the application wants to handle the
watchdog. The only difficulty with this change is that an
application has to either include the clock driver or handle the
watchdog explicitely. I don't think this is much of a problem since
I am pretty sure that almost every application includes the clock
driver.
Diffstat (limited to 'c/src/lib/libbsp/m68k/gen68360/startup/init68360.c')
| -rw-r--r-- | c/src/lib/libbsp/m68k/gen68360/startup/init68360.c | 34 |
1 files changed, 18 insertions, 16 deletions
diff --git a/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c b/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c index 5c40acd358..a1a5b41657 100644 --- a/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c +++ b/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c @@ -69,14 +69,15 @@ void _Init68360 (void) /* * Step 8: Initialize system protection - * Disable watchdog FIXME: Should use watchdog!!!! - * Watchdog causes system reset - * Slowest watchdog timeout - * Disable double bus fault monitor - * Enable bus monitor external - * 1024 clocks for external timeout + * Enable watchdog + * Watchdog causes system reset + * Next-to-slowest watchdog timeout + * (21 seconds with 25 MHz oscillator) + * Enable double bus fault monitor + * Enable bus monitor for external cycles + * 1024 clocks for external timeout */ - m360.sypcr = 0x74; + m360.sypcr = 0xEC; /* * Step 9: Clear parameter RAM and reset communication processor module @@ -368,14 +369,15 @@ void _Init68360 (void) /* * Step 8: Initialize system protection - * Disable watchdog FIXME: Should use watchdog!!!! - * Watchdog causes system reset - * Slowest watchdog timeout - * Enable double bus fault monitor - * Enable bus monitor external - * 128 clocks for external timeout + * Enable watchdog + * Watchdog causes system reset + * Next-to-slowest watchdog timeout + * (21 seconds with 25 MHz oscillator) + * Enable double bus fault monitor + * Enable bus monitor for external cycles + * 1024 clocks for external timeout */ - m360.sypcr = 0x7F; + m360.sypcr = 0xEC; /* * Step 9: Clear parameter RAM and reset communication processor module @@ -497,7 +499,7 @@ void _Init68360 (void) /* * Step 14: More system initialization * SDCR (Serial DMA configuration register) - * Disable SDMA during FREEZE + * Enable SDMA during FREEZE * Give SDMA priority over all interrupt handlers * Set DMA arbiration level to 4 * CICR (CPM interrupt configuration register): @@ -510,7 +512,7 @@ void _Init68360 (void) * Vector base 128 * SCCs priority grouped at top of table */ - m360.sdcr = M360_SDMA_FREEZE | M360_SDMA_SISM_7 | M360_SDMA_SAID_4; + m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4; m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) | (4 << 13) | (0x1F << 8) | (128); |