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authorJoel Sherrill <joel.sherrill@OARcorp.com>1997-09-18 16:01:52 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>1997-09-18 16:01:52 +0000
commit6b4ca3125e022552c9b8e3747987267092efaf9e (patch)
treeb97aae323eb7a762f3e90f2e4886578f230995b2
parentupdated (diff)
downloadrtems-6b4ca3125e022552c9b8e3747987267092efaf9e.tar.bz2
Merged changes from Eric Norum:
Enable 68360 watchdog. The watchdog control register is a `write-once' register, so the watchdog has to be enabled in the boot roms if it is to be used at all. To make the change transparent I added a default feed of the watchdog to the clock interrupt handler. This can be overridden if the application wants to handle the watchdog. The only difficulty with this change is that an application has to either include the clock driver or handle the watchdog explicitely. I don't think this is much of a problem since I am pretty sure that almost every application includes the clock driver.
-rw-r--r--c/src/lib/libbsp/m68k/gen68360/clock/ckinit.c13
-rw-r--r--c/src/lib/libbsp/m68k/gen68360/include/bsp.h1
-rw-r--r--c/src/lib/libbsp/m68k/gen68360/startup/init68360.c34
3 files changed, 32 insertions, 16 deletions
diff --git a/c/src/lib/libbsp/m68k/gen68360/clock/ckinit.c b/c/src/lib/libbsp/m68k/gen68360/clock/ckinit.c
index 041226f48b..c86427fc43 100644
--- a/c/src/lib/libbsp/m68k/gen68360/clock/ckinit.c
+++ b/c/src/lib/libbsp/m68k/gen68360/clock/ckinit.c
@@ -51,9 +51,12 @@ volatile rtems_unsigned32 Clock_driver_ticks;
rtems_device_major_number rtems_clock_major = ~0;
rtems_device_minor_number rtems_clock_minor;
+char M360DefaultWatchdogFeeder = 1;
+
/*
* Periodic interval timer interrupt handler
*/
+
rtems_isr
Clock_isr (rtems_vector_number vector)
{
@@ -64,6 +67,16 @@ Clock_isr (rtems_vector_number vector)
m360.dpram0[0];
/*
+ * Feed the watchdog
+ * Application code can override this by
+ * setting M360DefaultWatchdogFeeder to zero.
+ */
+ if (M360DefaultWatchdogFeeder) {
+ m360.swsr = 0x55;
+ m360.swsr = 0xAA;
+ }
+
+ /*
* Announce the clock tick
*/
Clock_driver_ticks++;
diff --git a/c/src/lib/libbsp/m68k/gen68360/include/bsp.h b/c/src/lib/libbsp/m68k/gen68360/include/bsp.h
index bcb0044401..70d18cdceb 100644
--- a/c/src/lib/libbsp/m68k/gen68360/include/bsp.h
+++ b/c/src/lib/libbsp/m68k/gen68360/include/bsp.h
@@ -121,6 +121,7 @@ void bsp_cleanup( void );
void M360ExecuteRISC( rtems_unsigned16 command );
void *M360AllocateBufferDescriptors( int count );
void *M360AllocateRiscTimers( int count );
+extern char M360DefaultWatchdogFeeder;
m68k_isr_entry set_vector(
rtems_isr_entry handler,
diff --git a/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c b/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
index 5c40acd358..a1a5b41657 100644
--- a/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
+++ b/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
@@ -69,14 +69,15 @@ void _Init68360 (void)
/*
* Step 8: Initialize system protection
- * Disable watchdog FIXME: Should use watchdog!!!!
- * Watchdog causes system reset
- * Slowest watchdog timeout
- * Disable double bus fault monitor
- * Enable bus monitor external
- * 1024 clocks for external timeout
+ * Enable watchdog
+ * Watchdog causes system reset
+ * Next-to-slowest watchdog timeout
+ * (21 seconds with 25 MHz oscillator)
+ * Enable double bus fault monitor
+ * Enable bus monitor for external cycles
+ * 1024 clocks for external timeout
*/
- m360.sypcr = 0x74;
+ m360.sypcr = 0xEC;
/*
* Step 9: Clear parameter RAM and reset communication processor module
@@ -368,14 +369,15 @@ void _Init68360 (void)
/*
* Step 8: Initialize system protection
- * Disable watchdog FIXME: Should use watchdog!!!!
- * Watchdog causes system reset
- * Slowest watchdog timeout
- * Enable double bus fault monitor
- * Enable bus monitor external
- * 128 clocks for external timeout
+ * Enable watchdog
+ * Watchdog causes system reset
+ * Next-to-slowest watchdog timeout
+ * (21 seconds with 25 MHz oscillator)
+ * Enable double bus fault monitor
+ * Enable bus monitor for external cycles
+ * 1024 clocks for external timeout
*/
- m360.sypcr = 0x7F;
+ m360.sypcr = 0xEC;
/*
* Step 9: Clear parameter RAM and reset communication processor module
@@ -497,7 +499,7 @@ void _Init68360 (void)
/*
* Step 14: More system initialization
* SDCR (Serial DMA configuration register)
- * Disable SDMA during FREEZE
+ * Enable SDMA during FREEZE
* Give SDMA priority over all interrupt handlers
* Set DMA arbiration level to 4
* CICR (CPM interrupt configuration register):
@@ -510,7 +512,7 @@ void _Init68360 (void)
* Vector base 128
* SCCs priority grouped at top of table
*/
- m360.sdcr = M360_SDMA_FREEZE | M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
+ m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
(4 << 13) | (0x1F << 8) | (128);