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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-11-25 08:40:20 +0100 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-11-27 10:33:30 +0100 |
commit | cbc433c7a25dbe19414f70edc64f9de1f630a117 (patch) | |
tree | 8d53c70658b82b052f0c5c81e7a025548a147aea /c/src/lib/libbsp/arm/xilinx-zynq/configure.ac | |
parent | rtems: Add rtems_cache_coherent_allocate() (diff) | |
download | rtems-cbc433c7a25dbe19414f70edc64f9de1f630a117.tar.bz2 |
bsps/arm: Add .nocache section
This section can be use to provide a cache coherent memory area via
rtems_cache_coherent_add_area().
Diffstat (limited to 'c/src/lib/libbsp/arm/xilinx-zynq/configure.ac')
-rw-r--r-- | c/src/lib/libbsp/arm/xilinx-zynq/configure.ac | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac b/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac index 8f47f2f072..ccc90508c9 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac +++ b/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac @@ -77,6 +77,9 @@ RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zedboard],[512M]) RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[*],[256M]) RTEMS_BSPOPTS_HELP([BSP_ZYNQ_RAM_LENGTH],[override a BSP's default RAM length]) +RTEMS_BSPOPTS_SET([BSP_ZYNQ_NOCACHE_LENGTH],[*],[1M]) +RTEMS_BSPOPTS_HELP([BSP_ZYNQ_NOCACHE_LENGTH],[length of nocache RAM region]) + AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu], [ZYNQ_RAM_ORIGIN="0x00000000" ZYNQ_RAM_MMU="0x0fffc000" @@ -133,6 +136,7 @@ ZYNQ_LINKCMD([ZYNQ_RAM_MMU],[MMU region origin],[${ZYNQ_RAM_MMU}]) ZYNQ_LINKCMD([ZYNQ_RAM_MMU_LENGTH],[MMU region length],[${ZYNQ_RAM_MMU_LENGTH}]) ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN_AVAILABLE],[origin of available RAM],[${ZYNQ_RAM_ORIGIN_AVAILABLE}]) ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH_AVAILABLE],[length of available RAM],[${ZYNQ_RAM_LENGTH_AVAILABLE}]) +ZYNQ_LINKCMD([ZYNQ_RAM_NOCACHE_LENGTH],[length of nocache RAM region],[${BSP_ZYNQ_NOCACHE_LENGTH}]) ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_ORIGIN],[internal 0 RAM region origin],[${ZYNQ_RAM_INT_0_ORIGIN}]) ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_LENGTH],[internal 0 RAM region length],[${ZYNQ_RAM_INT_0_LENGTH}]) ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_ORIGIN],[internal 1 RAM region origin],[${ZYNQ_RAM_INT_1_ORIGIN}]) |