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author | Ralf Corsepius <ralf.corsepius@rtems.org> | 2004-04-21 16:01:48 +0000 |
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committer | Ralf Corsepius <ralf.corsepius@rtems.org> | 2004-04-21 16:01:48 +0000 |
commit | f05b2ac0bc4626e854afc6e6a5d1b88071adbd7c (patch) | |
tree | 4150010cec9b6b51100f183b435955cd847679b4 /c/src/lib/libbsp/arm/vegaplus/start | |
parent | Remove stray white spaces. (diff) | |
download | rtems-f05b2ac0bc4626e854afc6e6a5d1b88071adbd7c.tar.bz2 |
Remove duplicate white lines.
Diffstat (limited to 'c/src/lib/libbsp/arm/vegaplus/start')
-rw-r--r-- | c/src/lib/libbsp/arm/vegaplus/start/start.S | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/c/src/lib/libbsp/arm/vegaplus/start/start.S b/c/src/lib/libbsp/arm/vegaplus/start/start.S index 6c3c2ab141..49c216150c 100644 --- a/c/src/lib/libbsp/arm/vegaplus/start/start.S +++ b/c/src/lib/libbsp/arm/vegaplus/start/start.S @@ -40,12 +40,10 @@ .equ I_Bit, 0x80 .equ F_Bit, 0x40 - .equ Mode_SVC_MIRQ, Mode_SVC | I_Bit | F_Bit .equ Mode_SVC_UIRQ, Mode_SVC .equ Mode_IRQ_MIRQ, Mode_SVC | I_Bit | F_Bit - .equ MARK_STACK, 0 /*Fill every stack with a pattern for debug (0 or 1)*/ /*----------------------------------------------------------------------------- @@ -129,7 +127,6 @@ Real_start: LDR r1, =0xA2 STR r1, [r0,#CSCNTL1_2] - MOV r0,#CNTL_CLK_ADR /* Load clock mode 55 MHz */ LDR r1, =0x0010 @@ -155,7 +152,6 @@ zi_init: STRLOT r2, [r0], #4 BLO zi_init - /* Load basic ARM7 interrupt table */ VectorInit: MOV R8, #0 |