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author | Martin Galvan <martin.galvan@tallertechnologies.com> | 2015-02-26 14:39:05 -0300 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-02-27 11:56:51 +0100 |
commit | 63e91fe689db4ddd7a0bf605cdedc975c2bcdbb5 (patch) | |
tree | a58e17d7f4492c03d3abf606951a77ab78122a2e /c/src/lib/libbsp/arm/shared/start/start.S | |
parent | psxtests/psx05: Adjust test case (diff) | |
download | rtems-63e91fe689db4ddd7a0bf605cdedc975c2bcdbb5.tar.bz2 |
ARM: Fix _ARMV4_Exception_fiq_default
In _ARMV4_Exception_fiq_default, set the F bit of the SPSR so that when
it gets loaded back to the CPSR in save_more_context it won't re-enable
the FIQs.
Tested on a TMS570LS3137.
Diffstat (limited to 'c/src/lib/libbsp/arm/shared/start/start.S')
0 files changed, 0 insertions, 0 deletions