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authorMartin Galvan <martin.galvan@tallertechnologies.com>2015-02-26 14:39:05 -0300
committerSebastian Huber <sebastian.huber@embedded-brains.de>2015-02-27 11:56:51 +0100
commit63e91fe689db4ddd7a0bf605cdedc975c2bcdbb5 (patch)
treea58e17d7f4492c03d3abf606951a77ab78122a2e
parent6357e14aac7ad9928b81db157d4b0b5506a9d993 (diff)
downloadrtems-63e91fe689db4ddd7a0bf605cdedc975c2bcdbb5.tar.bz2
ARM: Fix _ARMV4_Exception_fiq_default
In _ARMV4_Exception_fiq_default, set the F bit of the SPSR so that when it gets loaded back to the CPSR in save_more_context it won't re-enable the FIQs. Tested on a TMS570LS3137.
-rw-r--r--cpukit/score/cpu/arm/armv4-exception-default.S8
1 files changed, 8 insertions, 0 deletions
diff --git a/cpukit/score/cpu/arm/armv4-exception-default.S b/cpukit/score/cpu/arm/armv4-exception-default.S
index a0ee46c25b..a10de301b0 100644
--- a/cpukit/score/cpu/arm/armv4-exception-default.S
+++ b/cpukit/score/cpu/arm/armv4-exception-default.S
@@ -99,6 +99,14 @@ _ARMV4_Exception_fiq_default:
stmdb sp!, {r0-r12}
mov r4, #7
+ /*
+ * Don't enable FIQs yet. Set the FIQ disable bit in the SPSR
+ * (which we'll load into the CPSR in save_more_context).
+ */
+ mrs r2, spsr
+ orr r2, #ARM_PSR_F
+ msr spsr_c, r2
+
save_more_context:
/* Save more context */