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author | Ralf Kirchner <ralf.kirchner@embedded-brains.de> | 2014-04-17 11:19:48 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-04-17 13:25:12 +0200 |
commit | 62fa1ea25ed160a08bd795e7b08afaf86f58eea9 (patch) | |
tree | 3a3230a47f8bd4c95e92cb12697728914528b159 /c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h | |
parent | bsp/arm: Add L2 cache locking (diff) | |
download | rtems-62fa1ea25ed160a08bd795e7b08afaf86f58eea9.tar.bz2 |
bsp/arm: Add cache size methods
Add new methods which deliver the cache sizes of for supported cache levels.
Diffstat (limited to 'c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h')
-rw-r--r-- | c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h index 5d23085fc4..7d89a4a80f 100644 --- a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h +++ b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h @@ -463,6 +463,39 @@ static inline void arm_cache_l1_enable_instruction( void ) arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA ); } +static inline size_t arm_cache_l1_get_data_cache_size( void ) +{ + size_t size; + uint32_t line_size = 0; + uint32_t associativity = 0; + uint32_t num_sets = 0; + arm_cache_l1_properties( &line_size, &associativity, + &num_sets ); + + size = (1 << line_size) * associativity * num_sets; + + return size; +} + +static inline size_t arm_cache_l1_get_instruction_cache_size( void ) +{ + size_t size; + uint32_t line_size = 0; + uint32_t associativity = 0; + uint32_t num_sets = 0; + + arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION ); + + arm_cache_l1_properties( &line_size, &associativity, + &num_sets ); + + arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA ); + + size = (1 << line_size) * associativity * num_sets; + + return size; +} + #ifdef __cplusplus } #endif /* __cplusplus */ |