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authorRalf Kirchner <ralf.kirchner@embedded-brains.de>2014-04-17 11:19:48 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2014-04-17 13:25:12 +0200
commit62fa1ea25ed160a08bd795e7b08afaf86f58eea9 (patch)
tree3a3230a47f8bd4c95e92cb12697728914528b159
parent1c62f74d22a7ffee60f4341dc51f95b7d142919e (diff)
downloadrtems-62fa1ea25ed160a08bd795e7b08afaf86f58eea9.tar.bz2
bsp/arm: Add cache size methods
Add new methods which deliver the cache sizes of for supported cache levels.
-rw-r--r--c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h82
-rw-r--r--c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h33
2 files changed, 115 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
index 66075078fe..2dfc330c1d 100644
--- a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
+++ b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
@@ -73,6 +73,7 @@ extern "C" {
#define CPU_INSTRUCTION_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT
#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
+#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
#define CACHE_L2C_310_DATA_LINE_MASK ( CPU_DATA_CACHE_ALIGNMENT - 1 )
#define CACHE_L2C_310_INSTRUCTION_LINE_MASK \
@@ -1207,6 +1208,46 @@ cache_l2c_310_unfreeze( void )
by hardware at all */
}
+static inline size_t
+cache_l2c_310_get_cache_size( void )
+{
+ size_t size = 0;
+ volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
+ uint32_t cache_type = l2cc->cache_type;
+ uint32_t way_size;
+ uint32_t num_ways;
+
+ way_size = (cache_type & CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_MASK)
+ >> CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_SHIFT;
+ num_ways = (cache_type & CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_MASK)
+ >> CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_SHIFT;
+
+ assert( way_size <= 0x07 );
+ assert( num_ways <= 0x01 );
+ if( way_size <= 0x07 && num_ways <= 0x01 ) {
+ if( way_size == 0x00 ) {
+ way_size = 16 * 1024;
+ } else if( way_size == 0x07 ) {
+ way_size = 512 * 1024;
+ } else {
+ way_size = (1 << (way_size - 1)) * 16 * 1024;
+ }
+ switch( num_ways ) {
+ case 0:
+ num_ways = 8;
+ break;
+ case 1:
+ num_ways = 16;
+ break;
+ default:
+ num_ways = 0;
+ break;
+ }
+ size = way_size * num_ways;
+ }
+ return size;
+}
+
static void cache_l2c_310_unlock( void )
{
volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
@@ -1538,6 +1579,47 @@ _CPU_cache_unfreeze_instruction( void )
cache_l2c_310_unfreeze();
}
+static inline size_t
+_CPU_cache_get_data_cache_size( const uint32_t level )
+{
+ size_t size = 0;
+
+ switch( level )
+ {
+ case 0:
+ size = arm_cache_l1_get_data_cache_size();
+ break;
+ case 1:
+ size = cache_l2c_310_get_cache_size();
+ break;
+ default:
+ size = 0;
+ break;
+ }
+ return size;
+}
+
+static inline size_t
+_CPU_cache_get_instruction_cache_size( const uint32_t level )
+{
+ size_t size = 0;
+
+ switch( level )
+ {
+ case 0:
+ size = arm_cache_l1_get_instruction_cache_size();
+ break;
+ case 1:
+ size = cache_l2c_310_get_cache_size();
+ break;
+ default:
+ size = 0;
+ break;
+ }
+ return size;
+}
+
+
/** @} */
#ifdef __cplusplus
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
index 5d23085fc4..7d89a4a80f 100644
--- a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
+++ b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
@@ -463,6 +463,39 @@ static inline void arm_cache_l1_enable_instruction( void )
arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA );
}
+static inline size_t arm_cache_l1_get_data_cache_size( void )
+{
+ size_t size;
+ uint32_t line_size = 0;
+ uint32_t associativity = 0;
+ uint32_t num_sets = 0;
+ arm_cache_l1_properties( &line_size, &associativity,
+ &num_sets );
+
+ size = (1 << line_size) * associativity * num_sets;
+
+ return size;
+}
+
+static inline size_t arm_cache_l1_get_instruction_cache_size( void )
+{
+ size_t size;
+ uint32_t line_size = 0;
+ uint32_t associativity = 0;
+ uint32_t num_sets = 0;
+
+ arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION );
+
+ arm_cache_l1_properties( &line_size, &associativity,
+ &num_sets );
+
+ arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA );
+
+ size = (1 << line_size) * associativity * num_sets;
+
+ return size;
+}
+
#ifdef __cplusplus
}
#endif /* __cplusplus */