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authorSebastian Huber <sebastian.huber@embedded-brains.de>2012-02-11 21:10:12 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2012-02-11 21:11:30 +0100
commit14ee5a1e220fb6bf08ebd36ffb0982dca4515cdb (patch)
tree905beccc8a453e66132ba67db47f0fb23f92834e /c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c
parentUse proper ARMv7-M compiler flags. (diff)
downloadrtems-14ee5a1e220fb6bf08ebd36ffb0982dca4515cdb.tar.bz2
Support for NXP LPC1700 family
Diffstat (limited to 'c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c')
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c37
1 files changed, 36 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c b/c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c
index 30adcf2ba5..b73181024e 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
@@ -74,6 +74,15 @@ void lpc24xx_micro_seconds_delay(unsigned us)
} while (elapsed < delay);
}
+#ifdef ARM_MULTILIB_ARCH_V7M
+ unsigned lpc17xx_sysclk(unsigned clksrcsel)
+ {
+ return (clksrcsel & LPC17XX_SCB_CLKSRCSEL_CLKSRC) != 0 ?
+ LPC24XX_OSCILLATOR_MAIN
+ : LPC24XX_OSCILLATOR_INTERNAL;
+ }
+#endif
+
unsigned lpc24xx_pllclk(void)
{
#ifdef ARM_MULTILIB_ARCH_V4
@@ -106,6 +115,19 @@ unsigned lpc24xx_pllclk(void)
} else {
pllclk = pllinclk;
}
+ #else
+ volatile lpc17xx_scb *scb = &LPC17XX_SCB;
+ unsigned sysclk = lpc17xx_sysclk(scb->clksrcsel);
+ unsigned pllstat = scb->pll_0.stat;
+ unsigned pllclk = 0;
+ unsigned enabled_and_locked = LPC17XX_PLL_STAT_PLLE
+ | LPC17XX_PLL_STAT_PLOCK;
+
+ if ((pllstat & enabled_and_locked) == enabled_and_locked) {
+ unsigned m = LPC17XX_PLL_SEL_MSEL_GET(pllstat) + 1;
+
+ pllclk = sysclk * m;
+ }
#endif
return pllclk;
@@ -119,6 +141,19 @@ unsigned lpc24xx_cclk(void)
/* Get CPU frequency */
unsigned cclk = pllclk / (GET_CCLKCFG_CCLKSEL(CCLKCFG) + 1);
+ #else
+ volatile lpc17xx_scb *scb = &LPC17XX_SCB;
+ unsigned cclksel = scb->cclksel;
+ unsigned cclk_in = 0;
+ unsigned cclk = 0;
+
+ if ((cclksel & LPC17XX_SCB_CCLKSEL_CCLKSEL) != 0) {
+ cclk_in = lpc24xx_pllclk();
+ } else {
+ cclk_in = lpc17xx_sysclk(scb->clksrcsel);
+ }
+
+ cclk = cclk_in / LPC17XX_SCB_CCLKSEL_CCLKDIV_GET(cclksel);
#endif
return cclk;