add support for LPC32xx

1 files changed, 237 insertions, 237 deletions

diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h b/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h
index b4da9f5096..daf198f372 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h
+++ b/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h
@@ -1172,11 +1172,11 @@ Reset, and Code Security/Debugging */
 
 #define CLKSRCSEL_CLKSRC_MASK 0x00000003U
 
-#define GET_CLKSRCSEL_CLKSRC( reg) \
-  GET_FIELD( reg, CLKSRCSEL_CLKSRC_MASK, 0)
+#define GET_CLKSRCSEL_CLKSRC(reg) \
+  GET_FIELD(reg, CLKSRCSEL_CLKSRC_MASK, 0)
 
-#define SET_CLKSRCSEL_CLKSRC( reg, val) \
-  SET_FIELD( reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
+#define SET_CLKSRCSEL_CLKSRC(reg, val) \
+  SET_FIELD(reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
 
 /* PLLCON */
 
@@ -1188,37 +1188,37 @@ Reset, and Code Security/Debugging */
 
 #define PLLCFG_MSEL_MASK 0x00007fffU
 
-#define GET_PLLCFG_MSEL( reg) \
-  GET_FIELD( reg, PLLCFG_MSEL_MASK, 0)
+#define GET_PLLCFG_MSEL(reg) \
+  GET_FIELD(reg, PLLCFG_MSEL_MASK, 0)
 
-#define SET_PLLCFG_MSEL( reg, val) \
-  SET_FIELD( reg, val, PLLCFG_MSEL_MASK, 0)
+#define SET_PLLCFG_MSEL(reg, val) \
+  SET_FIELD(reg, val, PLLCFG_MSEL_MASK, 0)
 
 #define PLLCFG_NSEL_MASK 0x00ff0000U
 
-#define GET_PLLCFG_NSEL( reg) \
-  GET_FIELD( reg, PLLCFG_NSEL_MASK, 16)
+#define GET_PLLCFG_NSEL(reg) \
+  GET_FIELD(reg, PLLCFG_NSEL_MASK, 16)
 
-#define SET_PLLCFG_NSEL( reg, val) \
-  SET_FIELD( reg, val, PLLCFG_NSEL_MASK, 16)
+#define SET_PLLCFG_NSEL(reg, val) \
+  SET_FIELD(reg, val, PLLCFG_NSEL_MASK, 16)
 
 /* PLLSTAT */
 
 #define PLLSTAT_MSEL_MASK 0x00007fffU
 
-#define GET_PLLSTAT_MSEL( reg) \
-  GET_FIELD( reg, PLLSTAT_MSEL_MASK, 0)
+#define GET_PLLSTAT_MSEL(reg) \
+  GET_FIELD(reg, PLLSTAT_MSEL_MASK, 0)
 
-#define SET_PLLSTAT_MSEL( reg, val) \
-  SET_FIELD( reg, val, PLLSTAT_MSEL_MASK, 0)
+#define SET_PLLSTAT_MSEL(reg, val) \
+  SET_FIELD(reg, val, PLLSTAT_MSEL_MASK, 0)
 
 #define PLLSTAT_NSEL_MASK 0x00ff0000U
 
-#define GET_PLLSTAT_NSEL( reg) \
-  GET_FIELD( reg, PLLSTAT_NSEL_MASK, 16)
+#define GET_PLLSTAT_NSEL(reg) \
+  GET_FIELD(reg, PLLSTAT_NSEL_MASK, 16)
 
-#define SET_PLLSTAT_NSEL( reg, val) \
-  SET_FIELD( reg, val, PLLSTAT_NSEL_MASK, 16)
+#define SET_PLLSTAT_NSEL(reg, val) \
+  SET_FIELD(reg, val, PLLSTAT_NSEL_MASK, 16)
 
 #define PLLSTAT_PLLE 0x01000000U
 
@@ -1230,21 +1230,21 @@ Reset, and Code Security/Debugging */
 
 #define CCLKCFG_CCLKSEL_MASK 0x000000ffU
 
-#define GET_CCLKCFG_CCLKSEL( reg) \
-  GET_FIELD( reg, CCLKCFG_CCLKSEL_MASK, 0)
+#define GET_CCLKCFG_CCLKSEL(reg) \
+  GET_FIELD(reg, CCLKCFG_CCLKSEL_MASK, 0)
 
-#define SET_CCLKCFG_CCLKSEL( reg, val) \
-  SET_FIELD( reg, val, CCLKCFG_CCLKSEL_MASK, 0)
+#define SET_CCLKCFG_CCLKSEL(reg, val) \
+  SET_FIELD(reg, val, CCLKCFG_CCLKSEL_MASK, 0)
 
 /* MEMMAP */
 
 #define MEMMAP_MAP_MASK 0x00000003U
 
-#define GET_MEMMAP_MAP( reg) \
-  GET_FIELD( reg, MEMMAP_MAP_MASK, 0)
+#define GET_MEMMAP_MAP(reg) \
+  GET_FIELD(reg, MEMMAP_MAP_MASK, 0)
 
-#define SET_MEMMAP_MAP( reg, val) \
-  SET_FIELD( reg, val, MEMMAP_MAP_MASK, 0)
+#define SET_MEMMAP_MAP(reg, val) \
+  SET_FIELD(reg, val, MEMMAP_MAP_MASK, 0)
 
 /* TIR */
 
@@ -1300,229 +1300,229 @@ Reset, and Code Security/Debugging */
 
 #define PCLKSEL0_PCLK_WDT_MASK 0x00000003U
 
-#define GET_PCLKSEL0_PCLK_WDT( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_WDT_MASK, 0)
+#define GET_PCLKSEL0_PCLK_WDT(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_WDT_MASK, 0)
 
-#define SET_PCLKSEL0_PCLK_WDT( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
+#define SET_PCLKSEL0_PCLK_WDT(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
 
 #define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU
 
-#define GET_PCLKSEL0_PCLK_TIMER0( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
+#define GET_PCLKSEL0_PCLK_TIMER0(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
 
-#define SET_PCLKSEL0_PCLK_TIMER0( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
+#define SET_PCLKSEL0_PCLK_TIMER0(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
 
 #define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U
 
-#define GET_PCLKSEL0_PCLK_TIMER1( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
+#define GET_PCLKSEL0_PCLK_TIMER1(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
 
-#define SET_PCLKSEL0_PCLK_TIMER1( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
+#define SET_PCLKSEL0_PCLK_TIMER1(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
 
 #define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U
 
-#define GET_PCLKSEL0_PCLK_UART0( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_UART0_MASK, 6)
+#define GET_PCLKSEL0_PCLK_UART0(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_UART0_MASK, 6)
 
-#define SET_PCLKSEL0_PCLK_UART0( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
+#define SET_PCLKSEL0_PCLK_UART0(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
 
 #define PCLKSEL0_PCLK_UART1_MASK 0x00000300U
 
-#define GET_PCLKSEL0_PCLK_UART1( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_UART1_MASK, 8)
+#define GET_PCLKSEL0_PCLK_UART1(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_UART1_MASK, 8)
 
-#define SET_PCLKSEL0_PCLK_UART1( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
+#define SET_PCLKSEL0_PCLK_UART1(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
 
 #define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U
 
-#define GET_PCLKSEL0_PCLK_PWM0( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
+#define GET_PCLKSEL0_PCLK_PWM0(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
 
-#define SET_PCLKSEL0_PCLK_PWM0( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
+#define SET_PCLKSEL0_PCLK_PWM0(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
 
 #define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U
 
-#define GET_PCLKSEL0_PCLK_PWM1( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
+#define GET_PCLKSEL0_PCLK_PWM1(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
 
-#define SET_PCLKSEL0_PCLK_PWM1( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
+#define SET_PCLKSEL0_PCLK_PWM1(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
 
 #define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U
 
-#define GET_PCLKSEL0_PCLK_I2C0( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
+#define GET_PCLKSEL0_PCLK_I2C0(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
 
-#define SET_PCLKSEL0_PCLK_I2C0( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
+#define SET_PCLKSEL0_PCLK_I2C0(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
 
 #define PCLKSEL0_PCLK_SPI_MASK 0x00030000U
 
-#define GET_PCLKSEL0_PCLK_SPI( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_SPI_MASK, 16)
+#define GET_PCLKSEL0_PCLK_SPI(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_SPI_MASK, 16)
 
-#define SET_PCLKSEL0_PCLK_SPI( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
+#define SET_PCLKSEL0_PCLK_SPI(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
 
 #define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U
 
-#define GET_PCLKSEL0_PCLK_RTC( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_RTC_MASK, 18)
+#define GET_PCLKSEL0_PCLK_RTC(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_RTC_MASK, 18)
 
-#define SET_PCLKSEL0_PCLK_RTC( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
+#define SET_PCLKSEL0_PCLK_RTC(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
 
 #define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U
 
-#define GET_PCLKSEL0_PCLK_SSP1( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
+#define GET_PCLKSEL0_PCLK_SSP1(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
 
-#define SET_PCLKSEL0_PCLK_SSP1( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
+#define SET_PCLKSEL0_PCLK_SSP1(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
 
 #define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U
 
-#define GET_PCLKSEL0_PCLK_DAC( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_DAC_MASK, 22)
+#define GET_PCLKSEL0_PCLK_DAC(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_DAC_MASK, 22)
 
-#define SET_PCLKSEL0_PCLK_DAC( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
+#define SET_PCLKSEL0_PCLK_DAC(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
 
 #define PCLKSEL0_PCLK_ADC_MASK 0x03000000U
 
-#define GET_PCLKSEL0_PCLK_ADC( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_ADC_MASK, 24)
+#define GET_PCLKSEL0_PCLK_ADC(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_ADC_MASK, 24)
 
-#define SET_PCLKSEL0_PCLK_ADC( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
+#define SET_PCLKSEL0_PCLK_ADC(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
 
 #define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U
 
-#define GET_PCLKSEL0_PCLK_CAN1( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
+#define GET_PCLKSEL0_PCLK_CAN1(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
 
-#define SET_PCLKSEL0_PCLK_CAN1( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
+#define SET_PCLKSEL0_PCLK_CAN1(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
 
 #define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U
 
-#define GET_PCLKSEL0_PCLK_CAN2( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
+#define GET_PCLKSEL0_PCLK_CAN2(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
 
-#define SET_PCLKSEL0_PCLK_CAN2( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
+#define SET_PCLKSEL0_PCLK_CAN2(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
 
 /* PCLKSEL1 */
 
 #define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U
 
-#define GET_PCLKSEL1_PCLK_BAT_RAM( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
+#define GET_PCLKSEL1_PCLK_BAT_RAM(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
 
-#define SET_PCLKSEL1_PCLK_BAT_RAM( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
+#define SET_PCLKSEL1_PCLK_BAT_RAM(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
 
 #define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU
 
-#define GET_PCLKSEL1_PCLK_GPIO( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
+#define GET_PCLKSEL1_PCLK_GPIO(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
 
-#define SET_PCLKSEL1_PCLK_GPIO( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
+#define SET_PCLKSEL1_PCLK_GPIO(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
 
 #define PCLKSEL1_PCLK_PCB_MASK 0x00000030U
 
-#define GET_PCLKSEL1_PCLK_PCB( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_PCB_MASK, 4)
+#define GET_PCLKSEL1_PCLK_PCB(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_PCB_MASK, 4)
 
-#define SET_PCLKSEL1_PCLK_PCB( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
+#define SET_PCLKSEL1_PCLK_PCB(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
 
 #define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U
 
-#define GET_PCLKSEL1_PCLK_I2C1( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
+#define GET_PCLKSEL1_PCLK_I2C1(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
 
-#define SET_PCLKSEL1_PCLK_I2C1( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
+#define SET_PCLKSEL1_PCLK_I2C1(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
 
 #define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U
 
-#define GET_PCLKSEL1_PCLK_SSP0( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
+#define GET_PCLKSEL1_PCLK_SSP0(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
 
-#define SET_PCLKSEL1_PCLK_SSP0( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
+#define SET_PCLKSEL1_PCLK_SSP0(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
 
 #define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U
 
-#define GET_PCLKSEL1_PCLK_TIMER2( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
+#define GET_PCLKSEL1_PCLK_TIMER2(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
 
-#define SET_PCLKSEL1_PCLK_TIMER2( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
+#define SET_PCLKSEL1_PCLK_TIMER2(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
 
 #define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U
 
-#define GET_PCLKSEL1_PCLK_TIMER3( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
+#define GET_PCLKSEL1_PCLK_TIMER3(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
 
-#define SET_PCLKSEL1_PCLK_TIMER3( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
+#define SET_PCLKSEL1_PCLK_TIMER3(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
 
 #define PCLKSEL1_PCLK_UART2_MASK 0x00030000U
 
-#define GET_PCLKSEL1_PCLK_UART2( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_UART2_MASK, 16)
+#define GET_PCLKSEL1_PCLK_UART2(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_UART2_MASK, 16)
 
-#define SET_PCLKSEL1_PCLK_UART2( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
+#define SET_PCLKSEL1_PCLK_UART2(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
 
 #define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U
 
-#define GET_PCLKSEL1_PCLK_UART3( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_UART3_MASK, 18)
+#define GET_PCLKSEL1_PCLK_UART3(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_UART3_MASK, 18)
 
-#define SET_PCLKSEL1_PCLK_UART3( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
+#define SET_PCLKSEL1_PCLK_UART3(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
 
 #define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U
 
-#define GET_PCLKSEL1_PCLK_I2C2( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
+#define GET_PCLKSEL1_PCLK_I2C2(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
 
-#define SET_PCLKSEL1_PCLK_I2C2( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
+#define SET_PCLKSEL1_PCLK_I2C2(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
 
 #define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U
 
-#define GET_PCLKSEL1_PCLK_I2S( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_I2S_MASK, 22)
+#define GET_PCLKSEL1_PCLK_I2S(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_I2S_MASK, 22)
 
-#define SET_PCLKSEL1_PCLK_I2S( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
+#define SET_PCLKSEL1_PCLK_I2S(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
 
 #define PCLKSEL1_PCLK_MCI_MASK 0x03000000U
 
-#define GET_PCLKSEL1_PCLK_MCI( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_MCI_MASK, 24)
+#define GET_PCLKSEL1_PCLK_MCI(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_MCI_MASK, 24)
 
-#define SET_PCLKSEL1_PCLK_MCI( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
+#define SET_PCLKSEL1_PCLK_MCI(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
 
 #define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U
 
-#define GET_PCLKSEL1_PCLK_SYSCON( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
+#define GET_PCLKSEL1_PCLK_SYSCON(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
 
-#define SET_PCLKSEL1_PCLK_SYSCON( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
+#define SET_PCLKSEL1_PCLK_SYSCON(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
 
 /* RTC_ILR */
 
@@ -1559,19 +1559,19 @@ typedef struct {
 
 #define SSP_CR0_DSS_MASK 0x0000000fU
 
-#define GET_SSP_CR0_DSS( reg) \
-  GET_FIELD( reg, SSP_CR0_DSS_MASK, 0)
+#define GET_SSP_CR0_DSS(reg) \
+  GET_FIELD(reg, SSP_CR0_DSS_MASK, 0)
 
-#define SET_SSP_CR0_DSS( reg, val) \
-  SET_FIELD( reg, val, SSP_CR0_DSS_MASK, 0)
+#define SET_SSP_CR0_DSS(reg, val) \
+  SET_FIELD(reg, val, SSP_CR0_DSS_MASK, 0)
 
 #define SSP_CR0_FRF_MASK 0x00000030U
 
-#define GET_SSP_CR0_FRF( reg) \
-  GET_FIELD( reg, SSP_CR0_FRF_MASK, 4)
+#define GET_SSP_CR0_FRF(reg) \
+  GET_FIELD(reg, SSP_CR0_FRF_MASK, 4)
 
-#define SET_SSP_CR0_FRF( reg, val) \
-  SET_FIELD( reg, val, SSP_CR0_FRF_MASK, 4)
+#define SET_SSP_CR0_FRF(reg, val) \
+  SET_FIELD(reg, val, SSP_CR0_FRF_MASK, 4)
 
 #define SSP_CR0_CPOL 0x00000040U
 
@@ -1579,11 +1579,11 @@ typedef struct {
 
 #define SSP_CR0_SCR_MASK 0x0000ff00U
 
-#define GET_SSP_CR0_SCR( reg) \
-  GET_FIELD( reg, SSP_CR0_SCR_MASK, 8)
+#define GET_SSP_CR0_SCR(reg) \
+  GET_FIELD(reg, SSP_CR0_SCR_MASK, 8)
 
-#define SET_SSP_CR0_SCR( reg, val) \
-  SET_FIELD( reg, val, SSP_CR0_SCR_MASK, 8)
+#define SET_SSP_CR0_SCR(reg, val) \
+  SET_FIELD(reg, val, SSP_CR0_SCR_MASK, 8)
 
 /* SSP_CR1 */
 
@@ -1673,7 +1673,7 @@ typedef struct {
 
 #define GPDMA_STATUS_CH_1 0x00000002U
 
-#define GPDMA_CH_BASE_ADDR( i) \
+#define GPDMA_CH_BASE_ADDR(i) \
   ((volatile lpc24xx_dma_channel *) \
     ((i) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR))
 
@@ -1693,29 +1693,29 @@ typedef struct {
 
 #define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU
 
-#define GET_GPDMA_CH_CTRL_TSZ( reg) \
-  GET_FIELD( reg, GPDMA_CH_CTRL_TSZ_MASK, 0)
+#define GET_GPDMA_CH_CTRL_TSZ(reg) \
+  GET_FIELD(reg, GPDMA_CH_CTRL_TSZ_MASK, 0)
 
-#define SET_GPDMA_CH_CTRL_TSZ( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0)
+#define SET_GPDMA_CH_CTRL_TSZ(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0)
 
 #define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU
 
 #define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U
 
-#define GET_GPDMA_CH_CTRL_SBSZ( reg) \
-  GET_FIELD( reg, GPDMA_CH_CTRL_SBSZ_MASK, 12)
+#define GET_GPDMA_CH_CTRL_SBSZ(reg) \
+  GET_FIELD(reg, GPDMA_CH_CTRL_SBSZ_MASK, 12)
 
-#define SET_GPDMA_CH_CTRL_SBSZ( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12)
+#define SET_GPDMA_CH_CTRL_SBSZ(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12)
 
 #define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U
 
-#define GET_GPDMA_CH_CTRL_DBSZ( reg) \
-  GET_FIELD( reg, GPDMA_CH_CTRL_DBSZ_MASK, 15)
+#define GET_GPDMA_CH_CTRL_DBSZ(reg) \
+  GET_FIELD(reg, GPDMA_CH_CTRL_DBSZ_MASK, 15)
 
-#define SET_GPDMA_CH_CTRL_DBSZ( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15)
+#define SET_GPDMA_CH_CTRL_DBSZ(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15)
 
 #define GPDMA_CH_CTRL_BSZ_1 0x00000000U
 
@@ -1735,19 +1735,19 @@ typedef struct {
 
 #define GPDMA_CH_CTRL_SW_MASK 0x001c0000U
 
-#define GET_GPDMA_CH_CTRL_SW( reg) \
-  GET_FIELD( reg, GPDMA_CH_CTRL_SW_MASK, 18)
+#define GET_GPDMA_CH_CTRL_SW(reg) \
+  GET_FIELD(reg, GPDMA_CH_CTRL_SW_MASK, 18)
 
-#define SET_GPDMA_CH_CTRL_SW( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CTRL_SW_MASK, 18)
+#define SET_GPDMA_CH_CTRL_SW(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CTRL_SW_MASK, 18)
 
 #define GPDMA_CH_CTRL_DW_MASK 0x00e00000U
 
-#define GET_GPDMA_CH_CTRL_DW( reg) \
-  GET_FIELD( reg, GPDMA_CH_CTRL_DW_MASK, 21)
+#define GET_GPDMA_CH_CTRL_DW(reg) \
+  GET_FIELD(reg, GPDMA_CH_CTRL_DW_MASK, 21)
 
-#define SET_GPDMA_CH_CTRL_DW( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CTRL_DW_MASK, 21)
+#define SET_GPDMA_CH_CTRL_DW(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CTRL_DW_MASK, 21)
 
 #define GPDMA_CH_CTRL_W_8 0x00000000U
 
@@ -1761,11 +1761,11 @@ typedef struct {
 
 #define GPDMA_CH_CTRL_PROT_MASK 0x70000000U
 
-#define GET_GPDMA_CH_CTRL_PROT( reg) \
-  GET_FIELD( reg, GPDMA_CH_CTRL_PROT_MASK, 28)
+#define GET_GPDMA_CH_CTRL_PROT(reg) \
+  GET_FIELD(reg, GPDMA_CH_CTRL_PROT_MASK, 28)
 
-#define SET_GPDMA_CH_CTRL_PROT( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CTRL_PROT_MASK, 28)
+#define SET_GPDMA_CH_CTRL_PROT(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CTRL_PROT_MASK, 28)
 
 #define GPDMA_CH_CTRL_ITC 0x80000000U
 
@@ -1775,19 +1775,19 @@ typedef struct {
 
 #define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU
 
-#define GET_GPDMA_CH_CFG_SRCPER( reg) \
-  GET_FIELD( reg, GPDMA_CH_CFG_SRCPER_MASK, 1)
+#define GET_GPDMA_CH_CFG_SRCPER(reg) \
+  GET_FIELD(reg, GPDMA_CH_CFG_SRCPER_MASK, 1)
 
-#define SET_GPDMA_CH_CFG_SRCPER( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1)
+#define SET_GPDMA_CH_CFG_SRCPER(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1)
 
 #define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U
 
-#define GET_GPDMA_CH_CFG_DESTPER( reg) \
-  GET_FIELD( reg, GPDMA_CH_CFG_DESTPER_MASK, 6)
+#define GET_GPDMA_CH_CFG_DESTPER(reg) \
+  GET_FIELD(reg, GPDMA_CH_CFG_DESTPER_MASK, 6)
 
-#define SET_GPDMA_CH_CFG_DESTPER( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6)
+#define SET_GPDMA_CH_CFG_DESTPER(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6)
 
 #define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U
 
@@ -1805,11 +1805,11 @@ typedef struct {
 
 #define GPDMA_CH_CFG_FLOW_MASK 0x00003800U
 
-#define GET_GPDMA_CH_CFG_FLOW( reg) \
-  GET_FIELD( reg, GPDMA_CH_CFG_FLOW_MASK, 11)
+#define GET_GPDMA_CH_CFG_FLOW(reg) \
+  GET_FIELD(reg, GPDMA_CH_CFG_FLOW_MASK, 11)
 
-#define SET_GPDMA_CH_CFG_FLOW( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CFG_FLOW_MASK, 11)
+#define SET_GPDMA_CH_CFG_FLOW(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CFG_FLOW_MASK, 11)
 
 #define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U
 
@@ -1859,11 +1859,11 @@ typedef struct {
 
 #define ETH_RX_CTRL_SIZE_MASK 0x000007ffU
 
-#define GET_ETH_RX_CTRL_SIZE( reg) \
-  GET_FIELD( reg, ETH_RX_CTRL_SIZE_MASK, 0)
+#define GET_ETH_RX_CTRL_SIZE(reg) \
+  GET_FIELD(reg, ETH_RX_CTRL_SIZE_MASK, 0)
 
-#define SET_ETH_RX_CTRL_SIZE( reg, val) \
-  SET_FIELD( reg, val, ETH_RX_CTRL_SIZE_MASK, 0)
+#define SET_ETH_RX_CTRL_SIZE(reg, val) \
+  SET_FIELD(reg, val, ETH_RX_CTRL_SIZE_MASK, 0)
 
 #define ETH_RX_CTRL_INTERRUPT 0x80000000U
 
@@ -1871,11 +1871,11 @@ typedef struct {
 
 #define ETH_RX_STAT_RXSIZE_MASK 0x000007ffU
 
-#define GET_ETH_RX_STAT_RXSIZE( reg) \
-  GET_FIELD( reg, ETH_RX_STAT_RXSIZE_MASK, 0)
+#define GET_ETH_RX_STAT_RXSIZE(reg) \
+  GET_FIELD(reg, ETH_RX_STAT_RXSIZE_MASK, 0)
 
-#define SET_ETH_RX_STAT_RXSIZE( reg, val) \
-  SET_FIELD( reg, val, ETH_RX_STAT_RXSIZE_MASK, 0)
+#define SET_ETH_RX_STAT_RXSIZE(reg, val) \
+  SET_FIELD(reg, val, ETH_RX_STAT_RXSIZE_MASK, 0)
 
 #define ETH_RX_STAT_BYTES 0x00000100U
 
@@ -1911,11 +1911,11 @@ typedef struct {
 
 #define ETH_TX_CTRL_SIZE_MASK 0x000007ffU
 
-#define GET_ETH_TX_CTRL_SIZE( reg) \
-  GET_FIELD( reg, ETH_TX_CTRL_SIZE_MASK, 0)
+#define GET_ETH_TX_CTRL_SIZE(reg) \
+  GET_FIELD(reg, ETH_TX_CTRL_SIZE_MASK, 0)
 
-#define SET_ETH_TX_CTRL_SIZE( reg, val) \
-  SET_FIELD( reg, val, ETH_TX_CTRL_SIZE_MASK, 0)
+#define SET_ETH_TX_CTRL_SIZE(reg, val) \
+  SET_FIELD(reg, val, ETH_TX_CTRL_SIZE_MASK, 0)
 
 #define ETH_TX_CTRL_OVERRIDE 0x04000000U
 
@@ -1933,11 +1933,11 @@ typedef struct {
 
 #define ETH_TX_STAT_COLLISION_COUNT_MASK 0x01e00000U
 
-#define GET_ETH_TX_STAT_COLLISION_COUNT( reg) \
-  GET_FIELD( reg, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
+#define GET_ETH_TX_STAT_COLLISION_COUNT(reg) \
+  GET_FIELD(reg, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
 
-#define SET_ETH_TX_STAT_COLLISION_COUNT( reg, val) \
-  SET_FIELD( reg, val, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
+#define SET_ETH_TX_STAT_COLLISION_COUNT(reg, val) \
+  SET_FIELD(reg, val, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
 
 #define ETH_TX_STAT_DEFER 0x02000000U
 
@@ -2027,69 +2027,69 @@ typedef struct {
 
 #define AHBCFG_BREAK_BURST_MASK 0x00000006U
 
-#define GET_AHBCFG_BREAK_BURST( reg) \
-  GET_FIELD( reg, AHBCFG_BREAK_BURST_MASK, 1)
+#define GET_AHBCFG_BREAK_BURST(reg) \
+  GET_FIELD(reg, AHBCFG_BREAK_BURST_MASK, 1)
 
-#define SET_AHBCFG_BREAK_BURST( reg, val) \
-  SET_FIELD( reg, val, AHBCFG_BREAK_BURST_MASK, 1)
+#define SET_AHBCFG_BREAK_BURST(reg, val) \
+  SET_FIELD(reg, val, AHBCFG_BREAK_BURST_MASK, 1)
 
 #define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U
 
 #define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U
 
-#define GET_AHBCFG_QUANTUM_SIZE( reg) \
-  GET_FIELD( reg, AHBCFG_QUANTUM_SIZE_MASK, 4)
+#define GET_AHBCFG_QUANTUM_SIZE(reg) \
+  GET_FIELD(reg, AHBCFG_QUANTUM_SIZE_MASK, 4)
 
-#define SET_AHBCFG_QUANTUM_SIZE( reg, val) \
-  SET_FIELD( reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4)
+#define SET_AHBCFG_QUANTUM_SIZE(reg, val) \
+  SET_FIELD(reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4)
 
 #define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U
 
-#define GET_AHBCFG_DEFAULT_MASTER( reg) \
-  GET_FIELD( reg, AHBCFG_DEFAULT_MASTER_MASK, 8)
+#define GET_AHBCFG_DEFAULT_MASTER(reg) \
+  GET_FIELD(reg, AHBCFG_DEFAULT_MASTER_MASK, 8)
 
-#define SET_AHBCFG_DEFAULT_MASTER( reg, val) \
-  SET_FIELD( reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8)
+#define SET_AHBCFG_DEFAULT_MASTER(reg, val) \
+  SET_FIELD(reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8)
 
 #define AHBCFG_EP1_MASK 0x00007000U
 
-#define GET_AHBCFG_EP1( reg) \
-  GET_FIELD( reg, AHBCFG_EP1_MASK, 12)
+#define GET_AHBCFG_EP1(reg) \
+  GET_FIELD(reg, AHBCFG_EP1_MASK, 12)
 
-#define SET_AHBCFG_EP1( reg, val) \
-  SET_FIELD( reg, val, AHBCFG_EP1_MASK, 12)
+#define SET_AHBCFG_EP1(reg, val) \
+  SET_FIELD(reg, val, AHBCFG_EP1_MASK, 12)
 
 #define AHBCFG_EP2_MASK 0x00070000U
 
-#define GET_AHBCFG_EP2( reg) \
-  GET_FIELD( reg, AHBCFG_EP2_MASK, 16)
+#define GET_AHBCFG_EP2(reg) \
+  GET_FIELD(reg, AHBCFG_EP2_MASK, 16)
 
-#define SET_AHBCFG_EP2( reg, val) \
-  SET_FIELD( reg, val, AHBCFG_EP2_MASK, 16)
+#define SET_AHBCFG_EP2(reg, val) \
+  SET_FIELD(reg, val, AHBCFG_EP2_MASK, 16)
 
 #define AHBCFG_EP3_MASK 0x00700000U
 
-#define GET_AHBCFG_EP3( reg) \
-  GET_FIELD( reg, AHBCFG_EP3_MASK, 20)
+#define GET_AHBCFG_EP3(reg) \
+  GET_FIELD(reg, AHBCFG_EP3_MASK, 20)
 
-#define SET_AHBCFG_EP3( reg, val) \
-  SET_FIELD( reg, val, AHBCFG_EP3_MASK, 20)
+#define SET_AHBCFG_EP3(reg, val) \
+  SET_FIELD(reg, val, AHBCFG_EP3_MASK, 20)
 
 #define AHBCFG_EP4_MASK 0x07000000U
 
-#define GET_AHBCFG_EP4( reg) \
-  GET_FIELD( reg, AHBCFG_EP4_MASK, 24)
+#define GET_AHBCFG_EP4(reg) \
+  GET_FIELD(reg, AHBCFG_EP4_MASK, 24)
 
-#define SET_AHBCFG_EP4( reg, val) \
-  SET_FIELD( reg, val, AHBCFG_EP4_MASK, 24)
+#define SET_AHBCFG_EP4(reg, val) \
+  SET_FIELD(reg, val, AHBCFG_EP4_MASK, 24)
 
 #define AHBCFG_EP5_MASK 0x70000000U
 
-#define GET_AHBCFG_EP5( reg) \
-  GET_FIELD( reg, AHBCFG_EP5_MASK, 28)
+#define GET_AHBCFG_EP5(reg) \
+  GET_FIELD(reg, AHBCFG_EP5_MASK, 28)
 
-#define SET_AHBCFG_EP5( reg, val) \
-  SET_FIELD( reg, val, AHBCFG_EP5_MASK, 28)
+#define SET_AHBCFG_EP5(reg, val) \
+  SET_FIELD(reg, val, AHBCFG_EP5_MASK, 28)
 
 /* EMC */