add support for LPC32xx

50 files changed, 2591 insertions, 594 deletions

diff --git a/c/src/lib/libbsp/arm/ChangeLog b/c/src/lib/libbsp/arm/ChangeLog
index d88f8c9103..f452d2b307 100644
--- a/c/src/lib/libbsp/arm/ChangeLog
+++ b/c/src/lib/libbsp/arm/ChangeLog
@@ -1,3 +1,9 @@
+2009-12-15	Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* shared/include/linker-symbols.h: C++ compatibility.
+	* shared/lpc/include/lpc-timer.h, shared/lpc/clock/lpc-clock-config.c:
+	New files.
+
 2009-12-07	Ralf Corsépius <ralf.corsepiu@rtems.org>
 
 	* shared/comm/console.c: Remove (Unused).
diff --git a/c/src/lib/libbsp/arm/acinclude.m4 b/c/src/lib/libbsp/arm/acinclude.m4
index 89fc7ce761..cd8cd2c2e3 100644
--- a/c/src/lib/libbsp/arm/acinclude.m4
+++ b/c/src/lib/libbsp/arm/acinclude.m4
@@ -18,6 +18,8 @@ AC_DEFUN([RTEMS_CHECK_BSPDIR],
     AC_CONFIG_SUBDIRS([gumstix]);;
   lpc24xx )
     AC_CONFIG_SUBDIRS([lpc24xx]);;
+  lpc32xx )
+    AC_CONFIG_SUBDIRS([lpc32xx]);;
   nds )
     AC_CONFIG_SUBDIRS([nds]);;
   rtl22xx )
diff --git a/c/src/lib/libbsp/arm/lpc24xx/ChangeLog b/c/src/lib/libbsp/arm/lpc24xx/ChangeLog
index eaec880a3a..399ebbb5e2 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/ChangeLog
+++ b/c/src/lib/libbsp/arm/lpc24xx/ChangeLog
@@ -1,3 +1,17 @@
+2009-12-15	Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* clock/clock-config.c: Removed file.
+	* include/lpc-clock-config.h, make/custom/lpc2362.cfg,
+	startup/linkcmds.lpc2362: New files.
+	* Makefile.am, configure.ac, preinstall.am, console/console-config.c,
+	i2c/i2c.c, include/bsp.h, include/io.h, include/irq.h,
+	include/lpc24xx.h, irq/irq.c, make/custom/lpc24xx.inc, misc/dma.c,
+	misc/io.c, misc/timer.c, network/network.c, rtc/rtc-config.c,
+	startup/bspreset.c, startup/bspstart.c, startup/bspstarthooks.c,
+	startup/linkcmds.lpc24xx_ea, startup/linkcmds.lpc24xx_ncs_ram,
+	startup/linkcmds.lpc24xx_ncs_rom_ext,
+	startup/linkcmds.lpc24xx_ncs_rom_int: Changes throughout.
+
 2009-11-03	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* configure.ac: Add RTEMS_BSP_LINKCMDS.
diff --git a/c/src/lib/libbsp/arm/lpc24xx/Makefile.am b/c/src/lib/libbsp/arm/lpc24xx/Makefile.am
index ebc63e766a..765c2c1223 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/Makefile.am
+++ b/c/src/lib/libbsp/arm/lpc24xx/Makefile.am
@@ -34,6 +34,7 @@ include_bsp_HEADERS += ../../shared/include/stackalloc.h
 include_bsp_HEADERS += ../../shared/tod.h
 include_bsp_HEADERS += ../shared/include/linker-symbols.h
 include_bsp_HEADERS += ../shared/include/start.h
+include_bsp_HEADERS += ../shared/lpc/include/lpc-timer.h
 include_bsp_HEADERS += include/irq-config.h
 include_bsp_HEADERS += include/irq.h
 include_bsp_HEADERS += include/lpc24xx.h
@@ -42,6 +43,7 @@ include_bsp_HEADERS += include/ssp.h
 include_bsp_HEADERS += include/dma.h
 include_bsp_HEADERS += include/i2c.h
 include_bsp_HEADERS += include/io.h
+include_bsp_HEADERS += include/lpc-clock-config.h
 
 include_HEADERS += ../../shared/include/tm27.h
 
@@ -61,6 +63,7 @@ EXTRA_DIST = startup/linkcmds.lpc24xx_ea
 EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_rom_int
 EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_rom_ext
 EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_ram
+EXTRA_DIST += startup/linkcmds.lpc2362
 
 ###############################################################################
 #                  LibBSP                                                     #
@@ -100,7 +103,7 @@ libbsp_a_SOURCES += ../../shared/console.c \
 	console/console-config.c
 
 # Clock
-libbsp_a_SOURCES += clock/clock-config.c \
+libbsp_a_SOURCES += ../shared/lpc/clock/lpc-clock-config.c \
 	../../../shared/clockdrv_shell.h
 
 # RTC
diff --git a/c/src/lib/libbsp/arm/lpc24xx/configure.ac b/c/src/lib/libbsp/arm/lpc24xx/configure.ac
index 4cc7dc0d8d..e5724d7238 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/configure.ac
+++ b/c/src/lib/libbsp/arm/lpc24xx/configure.ac
@@ -45,6 +45,10 @@ RTEMS_BSPOPTS_HELP([LPC24XX_EMC_NUMONYX],[enable Numonyx configuration for EMC])
 RTEMS_BSPOPTS_SET([LPC24XX_EMC_TEST],[*],[])
 RTEMS_BSPOPTS_HELP([LPC24XX_EMC_TEST],[enable tests for EMC])
 
+RTEMS_BSPOPTS_SET([LPC24XX_SPECIAL_TASK_STACKS_SUPPORT],[lpc2362],[])
+RTEMS_BSPOPTS_SET([LPC24XX_SPECIAL_TASK_STACKS_SUPPORT],[*],[1])
+RTEMS_BSPOPTS_HELP([LPC24XX_SPECIAL_TASK_STACKS_SUPPORT],[enable special task stack support for task stacks in internal RAM])
+
 RTEMS_BSPOPTS_SET([LPC24XX_CONFIG_CONSOLE],[*],[0])
 RTEMS_BSPOPTS_HELP([LPC24XX_CONFIG_CONSOLE],[configuration for console (UART 0)])
 
diff --git a/c/src/lib/libbsp/arm/lpc24xx/console/console-config.c b/c/src/lib/libbsp/arm/lpc24xx/console/console-config.c
index fd0c26484f..de49468c2f 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/console/console-config.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/console/console-config.c
@@ -25,14 +25,14 @@
 #include <bsp/lpc24xx.h>
 #include <bsp/irq.h>
 
-static uint8_t lpc24xx_uart_register( uint32_t addr, uint8_t i)
+static uint8_t lpc24xx_uart_register(uint32_t addr, uint8_t i)
 {
   volatile uint32_t *reg = (volatile uint32_t *) addr;
 
   return (uint8_t) reg [i];
 }
 
-static void lpc24xx_uart_set_register( uint32_t addr, uint8_t i, uint8_t val)
+static void lpc24xx_uart_set_register(uint32_t addr, uint8_t i, uint8_t val)
 {
   volatile uint32_t *reg = (volatile uint32_t *) addr;
 
@@ -129,7 +129,7 @@ console_tbl Console_Port_Tbl [] = {
 };
 
 #define LPC24XX_UART_NUMBER \
-  (sizeof( Console_Port_Tbl) / sizeof( Console_Port_Tbl [0]))
+  (sizeof(Console_Port_Tbl) / sizeof(Console_Port_Tbl [0]))
 
 unsigned long Console_Port_Count = LPC24XX_UART_NUMBER;
 
diff --git a/c/src/lib/libbsp/arm/lpc24xx/i2c/i2c.c b/c/src/lib/libbsp/arm/lpc24xx/i2c/i2c.c
index a1e86493d6..dc4ba13c1d 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/i2c/i2c.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/i2c/i2c.c
@@ -44,7 +44,7 @@ typedef struct {
   uint8_t * volatile end;
 } lpc24xx_i2c_bus_entry;
 
-static void lpc24xx_i2c_handler( void *arg)
+static void lpc24xx_i2c_handler(void *arg)
 {
   lpc24xx_i2c_bus_entry *e = arg;
   volatile lpc24xx_i2c *regs = e->regs;
@@ -97,20 +97,20 @@ static void lpc24xx_i2c_handler( void *arg)
 
   /* Notify task if necessary */
   if (notify) {
-    bsp_interrupt_vector_disable( e->vector);
+    bsp_interrupt_vector_disable(e->vector);
 
-    rtems_semaphore_release( e->state_update);
+    rtems_semaphore_release(e->state_update);
   }
 }
 
-static rtems_status_code lpc24xx_i2c_wait( lpc24xx_i2c_bus_entry *e)
+static rtems_status_code lpc24xx_i2c_wait(lpc24xx_i2c_bus_entry *e)
 {
-  bsp_interrupt_vector_enable( e->vector);
+  bsp_interrupt_vector_enable(e->vector);
 
-  return rtems_semaphore_obtain( e->state_update, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
+  return rtems_semaphore_obtain(e->state_update, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
 }
 
-static rtems_status_code lpc24xx_i2c_init( rtems_libi2c_bus_t *bus)
+static rtems_status_code lpc24xx_i2c_init(rtems_libi2c_bus_t *bus)
 {
   rtems_status_code sc = RTEMS_SUCCESSFUL;
   lpc24xx_i2c_bus_entry *e = (lpc24xx_i2c_bus_entry *) bus;
@@ -119,21 +119,21 @@ static rtems_status_code lpc24xx_i2c_init( rtems_libi2c_bus_t *bus)
 
   /* Create semaphore */
   sc = rtems_semaphore_create (
-    rtems_build_name ( 'I', '2', 'C', '0' + e->index),
+    rtems_build_name ('I', '2', 'C', '0' + e->index),
     0,
     RTEMS_SIMPLE_BINARY_SEMAPHORE,
     0,
     &e->state_update
   );
-  RTEMS_CHECK_SC( sc, "create status update semaphore");
+  RTEMS_CHECK_SC(sc, "create status update semaphore");
 
   /* Enable module power */
-  sc = lpc24xx_module_enable( LPC24XX_MODULE_I2C, e->index, LPC24XX_MODULE_CCLK_8);
-  RTEMS_CHECK_SC( sc, "enable module");
+  sc = lpc24xx_module_enable(LPC24XX_MODULE_I2C_0 + e->index, LPC24XX_MODULE_CCLK_8);
+  RTEMS_CHECK_SC(sc, "enable module");
 
   /* IO configuration */
-  sc = lpc24xx_io_config( LPC24XX_MODULE_I2C, e->index, e->config);
-  RTEMS_CHECK_SC( sc, "IO configuration");
+  sc = lpc24xx_io_config(LPC24XX_MODULE_I2C_0 + e->index, e->config);
+  RTEMS_CHECK_SC(sc, "IO configuration");
 
   /* Clock high and low duty cycles */
   regs->sclh = cycles;
@@ -150,8 +150,8 @@ static rtems_status_code lpc24xx_i2c_init( rtems_libi2c_bus_t *bus)
     lpc24xx_i2c_handler,
     e
   );
-  RTEMS_CHECK_SC( sc, "install interrupt handler");
-  bsp_interrupt_vector_disable( e->vector);
+  RTEMS_CHECK_SC(sc, "install interrupt handler");
+  bsp_interrupt_vector_disable(e->vector);
 
   /* Enable module in master mode */
   regs->conset = LPC24XX_I2C_EN;
@@ -162,7 +162,7 @@ static rtems_status_code lpc24xx_i2c_init( rtems_libi2c_bus_t *bus)
   return RTEMS_SUCCESSFUL;
 }
 
-static rtems_status_code lpc24xx_i2c_send_start( rtems_libi2c_bus_t *bus)
+static rtems_status_code lpc24xx_i2c_send_start(rtems_libi2c_bus_t *bus)
 {
   rtems_status_code sc = RTEMS_SUCCESSFUL;
   lpc24xx_i2c_bus_entry *e = (lpc24xx_i2c_bus_entry *) bus;
@@ -173,13 +173,13 @@ static rtems_status_code lpc24xx_i2c_send_start( rtems_libi2c_bus_t *bus)
   regs->conset = LPC24XX_I2C_STA;
 
   /* Wait */
-  sc = lpc24xx_i2c_wait( e);
-  RTEMS_CHECK_SC( sc, "wait for state update");
+  sc = lpc24xx_i2c_wait(e);
+  RTEMS_CHECK_SC(sc, "wait for state update");
 
   return RTEMS_SUCCESSFUL;
 }
 
-static rtems_status_code lpc24xx_i2c_send_stop( rtems_libi2c_bus_t *bus)
+static rtems_status_code lpc24xx_i2c_send_stop(rtems_libi2c_bus_t *bus)
 {
   lpc24xx_i2c_bus_entry *e = (lpc24xx_i2c_bus_entry *) bus;
   volatile lpc24xx_i2c *regs = e->regs;
@@ -213,8 +213,8 @@ static rtems_status_code lpc24xx_i2c_send_addr(
   regs->conclr = LPC24XX_I2C_STA | LPC24XX_I2C_SI;
 
   /* Wait */
-  sc = lpc24xx_i2c_wait( e);
-  RTEMS_CHECK_SC_RV( sc, "wait for state update");
+  sc = lpc24xx_i2c_wait(e);
+  RTEMS_CHECK_SC_RV(sc, "wait for state update");
 
   /* Check state */
   state = regs->stat;
@@ -225,7 +225,7 @@ static rtems_status_code lpc24xx_i2c_send_addr(
   return RTEMS_SUCCESSFUL;
 }
 
-static int lpc24xx_i2c_read( rtems_libi2c_bus_t *bus, unsigned char *in, int n)
+static int lpc24xx_i2c_read(rtems_libi2c_bus_t *bus, unsigned char *in, int n)
 {
   rtems_status_code sc = RTEMS_SUCCESSFUL;
   lpc24xx_i2c_bus_entry *e = (lpc24xx_i2c_bus_entry *) bus;
@@ -253,8 +253,8 @@ static int lpc24xx_i2c_read( rtems_libi2c_bus_t *bus, unsigned char *in, int n)
   regs->conclr = LPC24XX_I2C_SI;
 
   /* Wait */
-  sc = lpc24xx_i2c_wait( e);
-  RTEMS_CHECK_SC_RV( sc, "wait for state update");
+  sc = lpc24xx_i2c_wait(e);
+  RTEMS_CHECK_SC_RV(sc, "wait for state update");
 
   /* Check state */
   state = regs->stat;
@@ -290,8 +290,8 @@ static int lpc24xx_i2c_write(
   regs->conclr = LPC24XX_I2C_SI;
 
   /* Wait */
-  sc = lpc24xx_i2c_wait( e);
-  RTEMS_CHECK_SC_RV( sc, "wait for state update");
+  sc = lpc24xx_i2c_wait(e);
+  RTEMS_CHECK_SC_RV(sc, "wait for state update");
 
   /* Check state */
   state = regs->stat;
@@ -310,14 +310,14 @@ static int lpc24xx_i2c_set_transfer_mode(
   return -RTEMS_NOT_IMPLEMENTED;
 }
 
-static int lpc24xx_i2c_ioctl( rtems_libi2c_bus_t *bus, int cmd, void *arg)
+static int lpc24xx_i2c_ioctl(rtems_libi2c_bus_t *bus, int cmd, void *arg)
 {
   int rv = -1;
   const rtems_libi2c_tfr_mode_t *tm = (const rtems_libi2c_tfr_mode_t *) arg;
 
   switch (cmd) {
     case RTEMS_LIBI2C_IOCTL_SET_TFRMODE:
-      rv = lpc24xx_i2c_set_transfer_mode( bus, tm);
+      rv = lpc24xx_i2c_set_transfer_mode(bus, tm);
       break;
     default:
       rv = -RTEMS_NOT_DEFINED;
@@ -341,7 +341,7 @@ static const rtems_libi2c_bus_ops_t lpc24xx_i2c_ops = {
   static lpc24xx_i2c_bus_entry lpc24xx_i2c_entry_0 = {
     .bus = {
       .ops = &lpc24xx_i2c_ops,
-      .size = sizeof( lpc24xx_i2c_bus_entry)
+      .size = sizeof(lpc24xx_i2c_bus_entry)
     },
     .regs = (volatile lpc24xx_i2c *) I2C0_BASE_ADDR,
     .index = 0,
@@ -357,7 +357,7 @@ static const rtems_libi2c_bus_ops_t lpc24xx_i2c_ops = {
   static lpc24xx_i2c_bus_entry lpc24xx_i2c_entry_1 = {
     .bus = {
       .ops = &lpc24xx_i2c_ops,
-      .size = sizeof( lpc24xx_i2c_bus_entry)
+      .size = sizeof(lpc24xx_i2c_bus_entry)
     },
     .regs = (volatile lpc24xx_i2c *) I2C1_BASE_ADDR,
     .index = 1,
@@ -373,7 +373,7 @@ static const rtems_libi2c_bus_ops_t lpc24xx_i2c_ops = {
   static lpc24xx_i2c_bus_entry lpc24xx_i2c_entry_2 = {
     .bus = {
       .ops = &lpc24xx_i2c_ops,
-      .size = sizeof( lpc24xx_i2c_bus_entry)
+      .size = sizeof(lpc24xx_i2c_bus_entry)
     },
     .regs = (volatile lpc24xx_i2c *) I2C2_BASE_ADDR,
     .index = 2,
diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h b/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h
index 75a6731507..a982305c95 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h
+++ b/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h
@@ -80,12 +80,12 @@ int lpc24xx_eth_attach_detach(
  *
  * #define CONFIGURE_INIT
  *
- * #define CONFIGURE_IDLE_TASK_BODY lpc24xx_idle
+ * #define CONFIGURE_IDLE_TASK_BODY bsp_idle_thread
  *
  * #include <confdefs.h>
  * @endcode
  */
-void *lpc24xx_idle(uintptr_t ignored);
+void *bsp_idle_thread(uintptr_t ignored);
 
 /** @} */
 
diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/io.h b/c/src/lib/libbsp/arm/lpc24xx/include/io.h
index ac107ff0fa..a29cf44357 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/include/io.h
+++ b/c/src/lib/libbsp/arm/lpc24xx/include/io.h
@@ -44,39 +44,53 @@ extern "C" {
 
 #define LPC24XX_IO_INDEX_MAX (LPC24XX_IO_PORT_COUNT * 32U)
 
-#define LPC24XX_IO_INDEX_BY_PORT( port, bit) (((port) << 5U) + (bit))
+#define LPC24XX_IO_INDEX_BY_PORT(port, bit) (((port) << 5U) + (bit))
 
-#define LPC24XX_IO_PORT( index) (index >> 5U)
+#define LPC24XX_IO_PORT(index) (index >> 5U)
 
-#define LPC24XX_IO_PORT_BIT( index) (index & 0x1fU)
+#define LPC24XX_IO_PORT_BIT(index) (index & 0x1fU)
 
 typedef enum {
-  LPC24XX_MODULE_ACF,
+  LPC24XX_MODULE_ACF = 0,
   LPC24XX_MODULE_ADC,
   LPC24XX_MODULE_BAT_RAM,
-  LPC24XX_MODULE_CAN,
+  LPC24XX_MODULE_CAN_0,
+  LPC24XX_MODULE_CAN_1,
   LPC24XX_MODULE_DAC,
   LPC24XX_MODULE_EMC,
   LPC24XX_MODULE_ETHERNET,
   LPC24XX_MODULE_GPDMA,
   LPC24XX_MODULE_GPIO,
-  LPC24XX_MODULE_I2C,
+  LPC24XX_MODULE_I2C_0,
+  LPC24XX_MODULE_I2C_1,
+  LPC24XX_MODULE_I2C_2,
   LPC24XX_MODULE_I2S,
   LPC24XX_MODULE_LCD,
   LPC24XX_MODULE_MCI,
   LPC24XX_MODULE_PCB,
-  LPC24XX_MODULE_PWM,
+  LPC24XX_MODULE_PWM_0,
+  LPC24XX_MODULE_PWM_1,
   LPC24XX_MODULE_RTC,
   LPC24XX_MODULE_SPI,
-  LPC24XX_MODULE_SSP,
+  LPC24XX_MODULE_SSP_0,
+  LPC24XX_MODULE_SSP_1,
   LPC24XX_MODULE_SYSCON,
-  LPC24XX_MODULE_TIMER,
-  LPC24XX_MODULE_UART,
+  LPC24XX_MODULE_TIMER_0,
+  LPC24XX_MODULE_TIMER_1,
+  LPC24XX_MODULE_TIMER_2,
+  LPC24XX_MODULE_TIMER_3,
+  LPC24XX_MODULE_UART_0,
+  LPC24XX_MODULE_UART_1,
+  LPC24XX_MODULE_UART_2,
+  LPC24XX_MODULE_UART_3,
   LPC24XX_MODULE_USB,
-  LPC24XX_MODULE_WDT,
-  LPC24XX_MODULE_COUNT
+  LPC24XX_MODULE_WDT
 } lpc24xx_module;
 
+#define LPC24XX_MODULE_FIRST LPC24XX_MODULE_ACF
+
+#define LPC24XX_MODULE_COUNT (LPC24XX_MODULE_WDT + 1)
+
 typedef enum {
   LPC24XX_MODULE_PCLK_DEFAULT = 0x0U,
   LPC24XX_MODULE_CCLK = 0x1U,
@@ -102,24 +116,20 @@ typedef enum {
 
 rtems_status_code lpc24xx_module_enable(
   lpc24xx_module module,
-  unsigned index,
   lpc24xx_module_clock clock
 );
 
 rtems_status_code lpc24xx_module_disable(
-  lpc24xx_module module,
-  unsigned index
+  lpc24xx_module module
 );
 
 rtems_status_code lpc24xx_io_config(
   lpc24xx_module module,
-  unsigned index,
   unsigned config
 );
 
 rtems_status_code lpc24xx_io_release(
   lpc24xx_module module,
-  unsigned index,
   unsigned config
 );
 
@@ -128,40 +138,40 @@ rtems_status_code lpc24xx_gpio_config(
   lpc24xx_gpio_settings settings
 );
 
-static inline void lpc24xx_gpio_set( unsigned index)
+static inline void lpc24xx_gpio_set(unsigned index)
 {
   if (index <= LPC24XX_IO_INDEX_MAX) {
-    unsigned port = LPC24XX_IO_PORT( index);
-    unsigned bit = LPC24XX_IO_PORT_BIT( index);
+    unsigned port = LPC24XX_IO_PORT(index);
+    unsigned bit = LPC24XX_IO_PORT_BIT(index);
 
     LPC24XX_FIO [port].set = 1U << bit;
   }
 }
 
-static inline void lpc24xx_gpio_clear( unsigned index)
+static inline void lpc24xx_gpio_clear(unsigned index)
 {
   if (index <= LPC24XX_IO_INDEX_MAX) {
-    unsigned port = LPC24XX_IO_PORT( index);
-    unsigned bit = LPC24XX_IO_PORT_BIT( index);
+    unsigned port = LPC24XX_IO_PORT(index);
+    unsigned bit = LPC24XX_IO_PORT_BIT(index);
 
     LPC24XX_FIO [port].clr = 1U << bit;
   }
 }
 
-static inline void lpc24xx_gpio_write( unsigned index, bool value)
+static inline void lpc24xx_gpio_write(unsigned index, bool value)
 {
   if (value) {
-    lpc24xx_gpio_set( index);
+    lpc24xx_gpio_set(index);
   } else {
-    lpc24xx_gpio_clear( index);
+    lpc24xx_gpio_clear(index);
   }
 }
 
-static inline bool lpc24xx_gpio_get( unsigned index)
+static inline bool lpc24xx_gpio_get(unsigned index)
 {
   if (index <= LPC24XX_IO_INDEX_MAX) {
-    unsigned port = LPC24XX_IO_PORT( index);
-    unsigned bit = LPC24XX_IO_PORT_BIT( index);
+    unsigned port = LPC24XX_IO_PORT(index);
+    unsigned bit = LPC24XX_IO_PORT_BIT(index);
 
     return (LPC24XX_FIO [port].pin & (1U << bit)) != 0;
   } else {
diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/irq.h b/c/src/lib/libbsp/arm/lpc24xx/include/irq.h
index d1cb6b5b7e..6b9ddf8a37 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/include/irq.h
+++ b/c/src/lib/libbsp/arm/lpc24xx/include/irq.h
@@ -68,6 +68,9 @@
 
 #define LPC24XX_IRQ_PRIORITY_VALUE_MIN 0U
 #define LPC24XX_IRQ_PRIORITY_VALUE_MAX 15U
+#define LPC24XX_IRQ_PRIORITY_COUNT (LPC24XX_IRQ_PRIORITY_VALUE_MAX + 1U)
+#define LPC24XX_IRQ_PRIORITY_HIGHEST LPC24XX_IRQ_PRIORITY_VALUE_MIN
+#define LPC24XX_IRQ_PRIORITY_LOWEST LPC24XX_IRQ_PRIORITY_VALUE_MAX
 
 /**
  * @brief Minimum vector number.
@@ -79,11 +82,9 @@
  */
 #define BSP_INTERRUPT_VECTOR_MAX LPC24XX_IRQ_I2S
 
-void bsp_interrupt_dispatch( void);
+void lpc24xx_irq_set_priority(rtems_vector_number vector, unsigned priority);
 
-void lpc24xx_irq_set_priority( rtems_vector_number vector, unsigned priority);
-
-unsigned lpc24xx_irq_priority( rtems_vector_number vector);
+unsigned lpc24xx_irq_get_priority(rtems_vector_number vector);
 
 /** @} */
 
diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h b/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h
index b4da9f5096..daf198f372 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h
+++ b/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h
@@ -1172,11 +1172,11 @@ Reset, and Code Security/Debugging */
 
 #define CLKSRCSEL_CLKSRC_MASK 0x00000003U
 
-#define GET_CLKSRCSEL_CLKSRC( reg) \
-  GET_FIELD( reg, CLKSRCSEL_CLKSRC_MASK, 0)
+#define GET_CLKSRCSEL_CLKSRC(reg) \
+  GET_FIELD(reg, CLKSRCSEL_CLKSRC_MASK, 0)
 
-#define SET_CLKSRCSEL_CLKSRC( reg, val) \
-  SET_FIELD( reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
+#define SET_CLKSRCSEL_CLKSRC(reg, val) \
+  SET_FIELD(reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
 
 /* PLLCON */
 
@@ -1188,37 +1188,37 @@ Reset, and Code Security/Debugging */
 
 #define PLLCFG_MSEL_MASK 0x00007fffU
 
-#define GET_PLLCFG_MSEL( reg) \
-  GET_FIELD( reg, PLLCFG_MSEL_MASK, 0)
+#define GET_PLLCFG_MSEL(reg) \
+  GET_FIELD(reg, PLLCFG_MSEL_MASK, 0)
 
-#define SET_PLLCFG_MSEL( reg, val) \
-  SET_FIELD( reg, val, PLLCFG_MSEL_MASK, 0)
+#define SET_PLLCFG_MSEL(reg, val) \
+  SET_FIELD(reg, val, PLLCFG_MSEL_MASK, 0)
 
 #define PLLCFG_NSEL_MASK 0x00ff0000U
 
-#define GET_PLLCFG_NSEL( reg) \
-  GET_FIELD( reg, PLLCFG_NSEL_MASK, 16)
+#define GET_PLLCFG_NSEL(reg) \
+  GET_FIELD(reg, PLLCFG_NSEL_MASK, 16)
 
-#define SET_PLLCFG_NSEL( reg, val) \
-  SET_FIELD( reg, val, PLLCFG_NSEL_MASK, 16)
+#define SET_PLLCFG_NSEL(reg, val) \
+  SET_FIELD(reg, val, PLLCFG_NSEL_MASK, 16)
 
 /* PLLSTAT */
 
 #define PLLSTAT_MSEL_MASK 0x00007fffU
 
-#define GET_PLLSTAT_MSEL( reg) \
-  GET_FIELD( reg, PLLSTAT_MSEL_MASK, 0)
+#define GET_PLLSTAT_MSEL(reg) \
+  GET_FIELD(reg, PLLSTAT_MSEL_MASK, 0)
 
-#define SET_PLLSTAT_MSEL( reg, val) \
-  SET_FIELD( reg, val, PLLSTAT_MSEL_MASK, 0)
+#define SET_PLLSTAT_MSEL(reg, val) \
+  SET_FIELD(reg, val, PLLSTAT_MSEL_MASK, 0)
 
 #define PLLSTAT_NSEL_MASK 0x00ff0000U
 
-#define GET_PLLSTAT_NSEL( reg) \
-  GET_FIELD( reg, PLLSTAT_NSEL_MASK, 16)
+#define GET_PLLSTAT_NSEL(reg) \
+  GET_FIELD(reg, PLLSTAT_NSEL_MASK, 16)
 
-#define SET_PLLSTAT_NSEL( reg, val) \
-  SET_FIELD( reg, val, PLLSTAT_NSEL_MASK, 16)
+#define SET_PLLSTAT_NSEL(reg, val) \
+  SET_FIELD(reg, val, PLLSTAT_NSEL_MASK, 16)
 
 #define PLLSTAT_PLLE 0x01000000U
 
@@ -1230,21 +1230,21 @@ Reset, and Code Security/Debugging */
 
 #define CCLKCFG_CCLKSEL_MASK 0x000000ffU
 
-#define GET_CCLKCFG_CCLKSEL( reg) \
-  GET_FIELD( reg, CCLKCFG_CCLKSEL_MASK, 0)
+#define GET_CCLKCFG_CCLKSEL(reg) \
+  GET_FIELD(reg, CCLKCFG_CCLKSEL_MASK, 0)
 
-#define SET_CCLKCFG_CCLKSEL( reg, val) \
-  SET_FIELD( reg, val, CCLKCFG_CCLKSEL_MASK, 0)
+#define SET_CCLKCFG_CCLKSEL(reg, val) \
+  SET_FIELD(reg, val, CCLKCFG_CCLKSEL_MASK, 0)
 
 /* MEMMAP */
 
 #define MEMMAP_MAP_MASK 0x00000003U
 
-#define GET_MEMMAP_MAP( reg) \
-  GET_FIELD( reg, MEMMAP_MAP_MASK, 0)
+#define GET_MEMMAP_MAP(reg) \
+  GET_FIELD(reg, MEMMAP_MAP_MASK, 0)
 
-#define SET_MEMMAP_MAP( reg, val) \
-  SET_FIELD( reg, val, MEMMAP_MAP_MASK, 0)
+#define SET_MEMMAP_MAP(reg, val) \
+  SET_FIELD(reg, val, MEMMAP_MAP_MASK, 0)
 
 /* TIR */
 
@@ -1300,229 +1300,229 @@ Reset, and Code Security/Debugging */
 
 #define PCLKSEL0_PCLK_WDT_MASK 0x00000003U
 
-#define GET_PCLKSEL0_PCLK_WDT( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_WDT_MASK, 0)
+#define GET_PCLKSEL0_PCLK_WDT(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_WDT_MASK, 0)
 
-#define SET_PCLKSEL0_PCLK_WDT( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
+#define SET_PCLKSEL0_PCLK_WDT(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
 
 #define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU
 
-#define GET_PCLKSEL0_PCLK_TIMER0( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
+#define GET_PCLKSEL0_PCLK_TIMER0(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
 
-#define SET_PCLKSEL0_PCLK_TIMER0( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
+#define SET_PCLKSEL0_PCLK_TIMER0(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
 
 #define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U
 
-#define GET_PCLKSEL0_PCLK_TIMER1( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
+#define GET_PCLKSEL0_PCLK_TIMER1(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
 
-#define SET_PCLKSEL0_PCLK_TIMER1( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
+#define SET_PCLKSEL0_PCLK_TIMER1(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
 
 #define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U
 
-#define GET_PCLKSEL0_PCLK_UART0( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_UART0_MASK, 6)
+#define GET_PCLKSEL0_PCLK_UART0(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_UART0_MASK, 6)
 
-#define SET_PCLKSEL0_PCLK_UART0( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
+#define SET_PCLKSEL0_PCLK_UART0(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
 
 #define PCLKSEL0_PCLK_UART1_MASK 0x00000300U
 
-#define GET_PCLKSEL0_PCLK_UART1( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_UART1_MASK, 8)
+#define GET_PCLKSEL0_PCLK_UART1(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_UART1_MASK, 8)
 
-#define SET_PCLKSEL0_PCLK_UART1( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
+#define SET_PCLKSEL0_PCLK_UART1(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
 
 #define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U
 
-#define GET_PCLKSEL0_PCLK_PWM0( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
+#define GET_PCLKSEL0_PCLK_PWM0(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
 
-#define SET_PCLKSEL0_PCLK_PWM0( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
+#define SET_PCLKSEL0_PCLK_PWM0(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
 
 #define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U
 
-#define GET_PCLKSEL0_PCLK_PWM1( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
+#define GET_PCLKSEL0_PCLK_PWM1(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
 
-#define SET_PCLKSEL0_PCLK_PWM1( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
+#define SET_PCLKSEL0_PCLK_PWM1(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
 
 #define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U
 
-#define GET_PCLKSEL0_PCLK_I2C0( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
+#define GET_PCLKSEL0_PCLK_I2C0(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
 
-#define SET_PCLKSEL0_PCLK_I2C0( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
+#define SET_PCLKSEL0_PCLK_I2C0(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
 
 #define PCLKSEL0_PCLK_SPI_MASK 0x00030000U
 
-#define GET_PCLKSEL0_PCLK_SPI( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_SPI_MASK, 16)
+#define GET_PCLKSEL0_PCLK_SPI(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_SPI_MASK, 16)
 
-#define SET_PCLKSEL0_PCLK_SPI( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
+#define SET_PCLKSEL0_PCLK_SPI(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
 
 #define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U
 
-#define GET_PCLKSEL0_PCLK_RTC( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_RTC_MASK, 18)
+#define GET_PCLKSEL0_PCLK_RTC(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_RTC_MASK, 18)
 
-#define SET_PCLKSEL0_PCLK_RTC( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
+#define SET_PCLKSEL0_PCLK_RTC(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
 
 #define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U
 
-#define GET_PCLKSEL0_PCLK_SSP1( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
+#define GET_PCLKSEL0_PCLK_SSP1(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
 
-#define SET_PCLKSEL0_PCLK_SSP1( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
+#define SET_PCLKSEL0_PCLK_SSP1(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
 
 #define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U
 
-#define GET_PCLKSEL0_PCLK_DAC( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_DAC_MASK, 22)
+#define GET_PCLKSEL0_PCLK_DAC(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_DAC_MASK, 22)
 
-#define SET_PCLKSEL0_PCLK_DAC( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
+#define SET_PCLKSEL0_PCLK_DAC(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
 
 #define PCLKSEL0_PCLK_ADC_MASK 0x03000000U
 
-#define GET_PCLKSEL0_PCLK_ADC( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_ADC_MASK, 24)
+#define GET_PCLKSEL0_PCLK_ADC(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_ADC_MASK, 24)
 
-#define SET_PCLKSEL0_PCLK_ADC( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
+#define SET_PCLKSEL0_PCLK_ADC(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
 
 #define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U
 
-#define GET_PCLKSEL0_PCLK_CAN1( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
+#define GET_PCLKSEL0_PCLK_CAN1(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
 
-#define SET_PCLKSEL0_PCLK_CAN1( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
+#define SET_PCLKSEL0_PCLK_CAN1(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
 
 #define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U
 
-#define GET_PCLKSEL0_PCLK_CAN2( reg) \
-  GET_FIELD( reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
+#define GET_PCLKSEL0_PCLK_CAN2(reg) \
+  GET_FIELD(reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
 
-#define SET_PCLKSEL0_PCLK_CAN2( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
+#define SET_PCLKSEL0_PCLK_CAN2(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
 
 /* PCLKSEL1 */
 
 #define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U
 
-#define GET_PCLKSEL1_PCLK_BAT_RAM( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
+#define GET_PCLKSEL1_PCLK_BAT_RAM(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
 
-#define SET_PCLKSEL1_PCLK_BAT_RAM( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
+#define SET_PCLKSEL1_PCLK_BAT_RAM(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
 
 #define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU
 
-#define GET_PCLKSEL1_PCLK_GPIO( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
+#define GET_PCLKSEL1_PCLK_GPIO(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
 
-#define SET_PCLKSEL1_PCLK_GPIO( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
+#define SET_PCLKSEL1_PCLK_GPIO(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
 
 #define PCLKSEL1_PCLK_PCB_MASK 0x00000030U
 
-#define GET_PCLKSEL1_PCLK_PCB( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_PCB_MASK, 4)
+#define GET_PCLKSEL1_PCLK_PCB(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_PCB_MASK, 4)
 
-#define SET_PCLKSEL1_PCLK_PCB( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
+#define SET_PCLKSEL1_PCLK_PCB(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
 
 #define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U
 
-#define GET_PCLKSEL1_PCLK_I2C1( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
+#define GET_PCLKSEL1_PCLK_I2C1(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
 
-#define SET_PCLKSEL1_PCLK_I2C1( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
+#define SET_PCLKSEL1_PCLK_I2C1(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
 
 #define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U
 
-#define GET_PCLKSEL1_PCLK_SSP0( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
+#define GET_PCLKSEL1_PCLK_SSP0(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
 
-#define SET_PCLKSEL1_PCLK_SSP0( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
+#define SET_PCLKSEL1_PCLK_SSP0(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
 
 #define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U
 
-#define GET_PCLKSEL1_PCLK_TIMER2( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
+#define GET_PCLKSEL1_PCLK_TIMER2(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
 
-#define SET_PCLKSEL1_PCLK_TIMER2( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
+#define SET_PCLKSEL1_PCLK_TIMER2(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
 
 #define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U
 
-#define GET_PCLKSEL1_PCLK_TIMER3( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
+#define GET_PCLKSEL1_PCLK_TIMER3(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
 
-#define SET_PCLKSEL1_PCLK_TIMER3( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
+#define SET_PCLKSEL1_PCLK_TIMER3(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
 
 #define PCLKSEL1_PCLK_UART2_MASK 0x00030000U
 
-#define GET_PCLKSEL1_PCLK_UART2( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_UART2_MASK, 16)
+#define GET_PCLKSEL1_PCLK_UART2(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_UART2_MASK, 16)
 
-#define SET_PCLKSEL1_PCLK_UART2( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
+#define SET_PCLKSEL1_PCLK_UART2(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
 
 #define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U
 
-#define GET_PCLKSEL1_PCLK_UART3( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_UART3_MASK, 18)
+#define GET_PCLKSEL1_PCLK_UART3(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_UART3_MASK, 18)
 
-#define SET_PCLKSEL1_PCLK_UART3( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
+#define SET_PCLKSEL1_PCLK_UART3(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
 
 #define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U
 
-#define GET_PCLKSEL1_PCLK_I2C2( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
+#define GET_PCLKSEL1_PCLK_I2C2(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
 
-#define SET_PCLKSEL1_PCLK_I2C2( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
+#define SET_PCLKSEL1_PCLK_I2C2(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
 
 #define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U
 
-#define GET_PCLKSEL1_PCLK_I2S( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_I2S_MASK, 22)
+#define GET_PCLKSEL1_PCLK_I2S(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_I2S_MASK, 22)
 
-#define SET_PCLKSEL1_PCLK_I2S( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
+#define SET_PCLKSEL1_PCLK_I2S(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
 
 #define PCLKSEL1_PCLK_MCI_MASK 0x03000000U
 
-#define GET_PCLKSEL1_PCLK_MCI( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_MCI_MASK, 24)
+#define GET_PCLKSEL1_PCLK_MCI(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_MCI_MASK, 24)
 
-#define SET_PCLKSEL1_PCLK_MCI( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
+#define SET_PCLKSEL1_PCLK_MCI(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
 
 #define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U
 
-#define GET_PCLKSEL1_PCLK_SYSCON( reg) \
-  GET_FIELD( reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
+#define GET_PCLKSEL1_PCLK_SYSCON(reg) \
+  GET_FIELD(reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
 
-#define SET_PCLKSEL1_PCLK_SYSCON( reg, val) \
-  SET_FIELD( reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
+#define SET_PCLKSEL1_PCLK_SYSCON(reg, val) \
+  SET_FIELD(reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
 
 /* RTC_ILR */
 
@@ -1559,19 +1559,19 @@ typedef struct {
 
 #define SSP_CR0_DSS_MASK 0x0000000fU
 
-#define GET_SSP_CR0_DSS( reg) \
-  GET_FIELD( reg, SSP_CR0_DSS_MASK, 0)
+#define GET_SSP_CR0_DSS(reg) \
+  GET_FIELD(reg, SSP_CR0_DSS_MASK, 0)
 
-#define SET_SSP_CR0_DSS( reg, val) \
-  SET_FIELD( reg, val, SSP_CR0_DSS_MASK, 0)
+#define SET_SSP_CR0_DSS(reg, val) \
+  SET_FIELD(reg, val, SSP_CR0_DSS_MASK, 0)
 
 #define SSP_CR0_FRF_MASK 0x00000030U
 
-#define GET_SSP_CR0_FRF( reg) \
-  GET_FIELD( reg, SSP_CR0_FRF_MASK, 4)
+#define GET_SSP_CR0_FRF(reg) \
+  GET_FIELD(reg, SSP_CR0_FRF_MASK, 4)
 
-#define SET_SSP_CR0_FRF( reg, val) \
-  SET_FIELD( reg, val, SSP_CR0_FRF_MASK, 4)
+#define SET_SSP_CR0_FRF(reg, val) \
+  SET_FIELD(reg, val, SSP_CR0_FRF_MASK, 4)
 
 #define SSP_CR0_CPOL 0x00000040U
 
@@ -1579,11 +1579,11 @@ typedef struct {
 
 #define SSP_CR0_SCR_MASK 0x0000ff00U
 
-#define GET_SSP_CR0_SCR( reg) \
-  GET_FIELD( reg, SSP_CR0_SCR_MASK, 8)
+#define GET_SSP_CR0_SCR(reg) \
+  GET_FIELD(reg, SSP_CR0_SCR_MASK, 8)
 
-#define SET_SSP_CR0_SCR( reg, val) \
-  SET_FIELD( reg, val, SSP_CR0_SCR_MASK, 8)
+#define SET_SSP_CR0_SCR(reg, val) \
+  SET_FIELD(reg, val, SSP_CR0_SCR_MASK, 8)
 
 /* SSP_CR1 */
 
@@ -1673,7 +1673,7 @@ typedef struct {
 
 #define GPDMA_STATUS_CH_1 0x00000002U
 
-#define GPDMA_CH_BASE_ADDR( i) \
+#define GPDMA_CH_BASE_ADDR(i) \
   ((volatile lpc24xx_dma_channel *) \
     ((i) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR))
 
@@ -1693,29 +1693,29 @@ typedef struct {
 
 #define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU
 
-#define GET_GPDMA_CH_CTRL_TSZ( reg) \
-  GET_FIELD( reg, GPDMA_CH_CTRL_TSZ_MASK, 0)
+#define GET_GPDMA_CH_CTRL_TSZ(reg) \
+  GET_FIELD(reg, GPDMA_CH_CTRL_TSZ_MASK, 0)
 
-#define SET_GPDMA_CH_CTRL_TSZ( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0)
+#define SET_GPDMA_CH_CTRL_TSZ(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0)
 
 #define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU
 
 #define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U
 
-#define GET_GPDMA_CH_CTRL_SBSZ( reg) \
-  GET_FIELD( reg, GPDMA_CH_CTRL_SBSZ_MASK, 12)
+#define GET_GPDMA_CH_CTRL_SBSZ(reg) \
+  GET_FIELD(reg, GPDMA_CH_CTRL_SBSZ_MASK, 12)
 
-#define SET_GPDMA_CH_CTRL_SBSZ( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12)
+#define SET_GPDMA_CH_CTRL_SBSZ(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12)
 
 #define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U
 
-#define GET_GPDMA_CH_CTRL_DBSZ( reg) \
-  GET_FIELD( reg, GPDMA_CH_CTRL_DBSZ_MASK, 15)
+#define GET_GPDMA_CH_CTRL_DBSZ(reg) \
+  GET_FIELD(reg, GPDMA_CH_CTRL_DBSZ_MASK, 15)
 
-#define SET_GPDMA_CH_CTRL_DBSZ( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15)
+#define SET_GPDMA_CH_CTRL_DBSZ(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15)
 
 #define GPDMA_CH_CTRL_BSZ_1 0x00000000U
 
@@ -1735,19 +1735,19 @@ typedef struct {
 
 #define GPDMA_CH_CTRL_SW_MASK 0x001c0000U
 
-#define GET_GPDMA_CH_CTRL_SW( reg) \
-  GET_FIELD( reg, GPDMA_CH_CTRL_SW_MASK, 18)
+#define GET_GPDMA_CH_CTRL_SW(reg) \
+  GET_FIELD(reg, GPDMA_CH_CTRL_SW_MASK, 18)
 
-#define SET_GPDMA_CH_CTRL_SW( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CTRL_SW_MASK, 18)
+#define SET_GPDMA_CH_CTRL_SW(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CTRL_SW_MASK, 18)
 
 #define GPDMA_CH_CTRL_DW_MASK 0x00e00000U
 
-#define GET_GPDMA_CH_CTRL_DW( reg) \
-  GET_FIELD( reg, GPDMA_CH_CTRL_DW_MASK, 21)
+#define GET_GPDMA_CH_CTRL_DW(reg) \
+  GET_FIELD(reg, GPDMA_CH_CTRL_DW_MASK, 21)
 
-#define SET_GPDMA_CH_CTRL_DW( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CTRL_DW_MASK, 21)
+#define SET_GPDMA_CH_CTRL_DW(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CTRL_DW_MASK, 21)
 
 #define GPDMA_CH_CTRL_W_8 0x00000000U
 
@@ -1761,11 +1761,11 @@ typedef struct {
 
 #define GPDMA_CH_CTRL_PROT_MASK 0x70000000U
 
-#define GET_GPDMA_CH_CTRL_PROT( reg) \
-  GET_FIELD( reg, GPDMA_CH_CTRL_PROT_MASK, 28)
+#define GET_GPDMA_CH_CTRL_PROT(reg) \
+  GET_FIELD(reg, GPDMA_CH_CTRL_PROT_MASK, 28)
 
-#define SET_GPDMA_CH_CTRL_PROT( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CTRL_PROT_MASK, 28)
+#define SET_GPDMA_CH_CTRL_PROT(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CTRL_PROT_MASK, 28)
 
 #define GPDMA_CH_CTRL_ITC 0x80000000U
 
@@ -1775,19 +1775,19 @@ typedef struct {
 
 #define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU
 
-#define GET_GPDMA_CH_CFG_SRCPER( reg) \
-  GET_FIELD( reg, GPDMA_CH_CFG_SRCPER_MASK, 1)
+#define GET_GPDMA_CH_CFG_SRCPER(reg) \
+  GET_FIELD(reg, GPDMA_CH_CFG_SRCPER_MASK, 1)
 
-#define SET_GPDMA_CH_CFG_SRCPER( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1)
+#define SET_GPDMA_CH_CFG_SRCPER(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1)
 
 #define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U
 
-#define GET_GPDMA_CH_CFG_DESTPER( reg) \
-  GET_FIELD( reg, GPDMA_CH_CFG_DESTPER_MASK, 6)
+#define GET_GPDMA_CH_CFG_DESTPER(reg) \
+  GET_FIELD(reg, GPDMA_CH_CFG_DESTPER_MASK, 6)
 
-#define SET_GPDMA_CH_CFG_DESTPER( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6)
+#define SET_GPDMA_CH_CFG_DESTPER(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6)
 
 #define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U
 
@@ -1805,11 +1805,11 @@ typedef struct {
 
 #define GPDMA_CH_CFG_FLOW_MASK 0x00003800U
 
-#define GET_GPDMA_CH_CFG_FLOW( reg) \
-  GET_FIELD( reg, GPDMA_CH_CFG_FLOW_MASK, 11)
+#define GET_GPDMA_CH_CFG_FLOW(reg) \
+  GET_FIELD(reg, GPDMA_CH_CFG_FLOW_MASK, 11)
 
-#define SET_GPDMA_CH_CFG_FLOW( reg, val) \
-  SET_FIELD( reg, val, GPDMA_CH_CFG_FLOW_MASK, 11)
+#define SET_GPDMA_CH_CFG_FLOW(reg, val) \
+  SET_FIELD(reg, val, GPDMA_CH_CFG_FLOW_MASK, 11)
 
 #define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U
 
@@ -1859,11 +1859,11 @@ typedef struct {
 
 #define ETH_RX_CTRL_SIZE_MASK 0x000007ffU
 
-#define GET_ETH_RX_CTRL_SIZE( reg) \
-  GET_FIELD( reg, ETH_RX_CTRL_SIZE_MASK, 0)
+#define GET_ETH_RX_CTRL_SIZE(reg) \
+  GET_FIELD(reg, ETH_RX_CTRL_SIZE_MASK, 0)
 
-#define SET_ETH_RX_CTRL_SIZE( reg, val) \
-  SET_FIELD( reg, val, ETH_RX_CTRL_SIZE_MASK, 0)
+#define SET_ETH_RX_CTRL_SIZE(reg, val) \
+  SET_FIELD(reg, val, ETH_RX_CTRL_SIZE_MASK, 0)
 
 #define ETH_RX_CTRL_INTERRUPT 0x80000000U
 
@@ -1871,11 +1871,11 @@ typedef struct {
 
 #define ETH_RX_STAT_RXSIZE_MASK 0x000007ffU
 
-#define GET_ETH_RX_STAT_RXSIZE( reg) \
-  GET_FIELD( reg, ETH_RX_STAT_RXSIZE_MASK, 0)
+#define GET_ETH_RX_STAT_RXSIZE(reg) \
+  GET_FIELD(reg, ETH_RX_STAT_RXSIZE_MASK, 0)
 
-#define SET_ETH_RX_STAT_RXSIZE( reg, val) \
-  SET_FIELD( reg, val, ETH_RX_STAT_RXSIZE_MASK, 0)
+#define SET_ETH_RX_STAT_RXSIZE(reg, val) \
+  SET_FIELD(reg, val, ETH_RX_STAT_RXSIZE_MASK, 0)
 
 #define ETH_RX_STAT_BYTES 0x00000100U
 
@@ -1911,11 +1911,11 @@ typedef struct {
 
 #define ETH_TX_CTRL_SIZE_MASK 0x000007ffU
 
-#define GET_ETH_TX_CTRL_SIZE( reg) \
-  GET_FIELD( reg, ETH_TX_CTRL_SIZE_MASK, 0)
+#define GET_ETH_TX_CTRL_SIZE(reg) \
+  GET_FIELD(reg, ETH_TX_CTRL_SIZE_MASK, 0)
 
-#define SET_ETH_TX_CTRL_SIZE( reg, val) \
-  SET_FIELD( reg, val, ETH_TX_CTRL_SIZE_MASK, 0)
+#define SET_ETH_TX_CTRL_SIZE(reg, val) \
+  SET_FIELD(reg, val, ETH_TX_CTRL_SIZE_MASK, 0)
 
 #define ETH_TX_CTRL_OVERRIDE 0x04000000U
 
@@ -1933,11 +1933,11 @@ typedef struct {
 
 #define ETH_TX_STAT_COLLISION_COUNT_MASK 0x01e00000U
 
-#define GET_ETH_TX_STAT_COLLISION_COUNT( reg) \
-  GET_FIELD( reg, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
+#define GET_ETH_TX_STAT_COLLISION_COUNT(reg) \
+  GET_FIELD(reg, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
 
-#define SET_ETH_TX_STAT_COLLISION_COUNT( reg, val) \
-  SET_FIELD( reg, val, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
+#define SET_ETH_TX_STAT_COLLISION_COUNT(reg, val) \
+  SET_FIELD(reg, val, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
 
 #define ETH_TX_STAT_DEFER 0x02000000U
 
@@ -2027,69 +2027,69 @@ typedef struct {
 
 #define AHBCFG_BREAK_BURST_MASK 0x00000006U
 
-#define GET_AHBCFG_BREAK_BURST( reg) \
-  GET_FIELD( reg, AHBCFG_BREAK_BURST_MASK, 1)
+#define GET_AHBCFG_BREAK_BURST(reg) \
+  GET_FIELD(reg, AHBCFG_BREAK_BURST_MASK, 1)
 
-#define SET_AHBCFG_BREAK_BURST( reg, val) \
-  SET_FIELD( reg, val, AHBCFG_BREAK_BURST_MASK, 1)
+#define SET_AHBCFG_BREAK_BURST(reg, val) \
+  SET_FIELD(reg, val, AHBCFG_BREAK_BURST_MASK, 1)
 
 #define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U
 
 #define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U
 
-#define GET_AHBCFG_QUANTUM_SIZE( reg) \
-  GET_FIELD( reg, AHBCFG_QUANTUM_SIZE_MASK, 4)
+#define GET_AHBCFG_QUANTUM_SIZE(reg) \
+  GET_FIELD(reg, AHBCFG_QUANTUM_SIZE_MASK, 4)
 
-#define SET_AHBCFG_QUANTUM_SIZE( reg, val) \
-  SET_FIELD( reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4)
+#define SET_AHBCFG_QUANTUM_SIZE(reg, val) \
+  SET_FIELD(reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4)
 
 #define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U
 
-#define GET_AHBCFG_DEFAULT_MASTER( reg) \
-  GET_FIELD( reg, AHBCFG_DEFAULT_MASTER_MASK, 8)
+#define GET_AHBCFG_DEFAULT_MASTER(reg) \
+  GET_FIELD(reg, AHBCFG_DEFAULT_MASTER_MASK, 8)
 
-#define SET_AHBCFG_DEFAULT_MASTER( reg, val) \
-  SET_FIELD( reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8)
+#define SET_AHBCFG_DEFAULT_MASTER(reg, val) \
+  SET_FIELD(reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8)
 
 #define AHBCFG_EP1_MASK 0x00007000U
 
-#define GET_AHBCFG_EP1( reg) \
-  GET_FIELD( reg, AHBCFG_EP1_MASK, 12)
+#define GET_AHBCFG_EP1(reg) \
+  GET_FIELD(reg, AHBCFG_EP1_MASK, 12)
 
-#define SET_AHBCFG_EP1( reg, val) \
-  SET_FIELD( reg, val, AHBCFG_EP1_MASK, 12)
+#define SET_AHBCFG_EP1(reg, val) \
+  SET_FIELD(reg, val, AHBCFG_EP1_MASK, 12)
 
 #define AHBCFG_EP2_MASK 0x00070000U
 
-#define GET_AHBCFG_EP2( reg) \
-  GET_FIELD( reg, AHBCFG_EP2_MASK, 16)
+#define GET_AHBCFG_EP2(reg) \
+  GET_FIELD(reg, AHBCFG_EP2_MASK, 16)
 
-#define SET_AHBCFG_EP2( reg, val) \
-  SET_FIELD( reg, val, AHBCFG_EP2_MASK, 16)
+#define SET_AHBCFG_EP2(reg, val) \
+  SET_FIELD(reg, val, AHBCFG_EP2_MASK, 16)
 
 #define AHBCFG_EP3_MASK 0x00700000U
 
-#define GET_AHBCFG_EP3( reg) \
-  GET_FIELD( reg, AHBCFG_EP3_MASK, 20)
+#define GET_AHBCFG_EP3(reg) \
+  GET_FIELD(reg, AHBCFG_EP3_MASK, 20)
 
-#define SET_AHBCFG_EP3( reg, val) \
-  SET_FIELD( reg, val, AHBCFG_EP3_MASK, 20)
+#define SET_AHBCFG_EP3(reg, val) \
+  SET_FIELD(reg, val, AHBCFG_EP3_MASK, 20)
 
 #define AHBCFG_EP4_MASK 0x07000000U
 
-#define GET_AHBCFG_EP4( reg) \
-  GET_FIELD( reg, AHBCFG_EP4_MASK, 24)
+#define GET_AHBCFG_EP4(reg) \
+  GET_FIELD(reg, AHBCFG_EP4_MASK, 24)
 
-#define SET_AHBCFG_EP4( reg, val) \
-  SET_FIELD( reg, val, AHBCFG_EP4_MASK, 24)
+#define SET_AHBCFG_EP4(reg, val) \
+  SET_FIELD(reg, val, AHBCFG_EP4_MASK, 24)
 
 #define AHBCFG_EP5_MASK 0x70000000U
 
-#define GET_AHBCFG_EP5( reg) \
-  GET_FIELD( reg, AHBCFG_EP5_MASK, 28)
+#define GET_AHBCFG_EP5(reg) \
+  GET_FIELD(reg, AHBCFG_EP5_MASK, 28)
 
-#define SET_AHBCFG_EP5( reg, val) \
-  SET_FIELD( reg, val, AHBCFG_EP5_MASK, 28)
+#define SET_AHBCFG_EP5(reg, val) \
+  SET_FIELD(reg, val, AHBCFG_EP5_MASK, 28)
 
 /* EMC */
 
diff --git a/c/src/lib/libbsp/arm/lpc24xx/irq/irq.c b/c/src/lib/libbsp/arm/lpc24xx/irq/irq.c
index 0c5e9a307d..d3073315f8 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/irq/irq.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/irq/irq.c
@@ -23,14 +23,14 @@
 #include <bsp/irq-generic.h>
 #include <bsp/lpc24xx.h>
 
-static inline bool lpc24xx_irq_is_valid( rtems_vector_number vector)
+static inline bool lpc24xx_irq_is_valid(rtems_vector_number vector)
 {
   return vector <= BSP_INTERRUPT_VECTOR_MAX;
 }
 
-void lpc24xx_irq_set_priority( rtems_vector_number vector, unsigned priority)
+void lpc24xx_irq_set_priority(rtems_vector_number vector, unsigned priority)
 {
-  if (lpc24xx_irq_is_valid( vector)) {
+  if (lpc24xx_irq_is_valid(vector)) {
     if (priority > LPC24XX_IRQ_PRIORITY_VALUE_MAX) {
       priority = LPC24XX_IRQ_PRIORITY_VALUE_MAX;
     }
@@ -39,16 +39,16 @@ void lpc24xx_irq_set_priority( rtems_vector_number vector, unsigned priority)
   }
 }
 
-unsigned lpc24xx_irq_priority( rtems_vector_number vector)
+unsigned lpc24xx_irq_get_priority(rtems_vector_number vector)
 {
-  if (lpc24xx_irq_is_valid( vector)) {
+  if (lpc24xx_irq_is_valid(vector)) {
     return VICVectPriorityBase [vector];
   } else {
     return LPC24XX_IRQ_PRIORITY_VALUE_MIN - 1U;
   }
 }
 
-void bsp_interrupt_dispatch( void)
+void bsp_interrupt_dispatch(void)
 {
   /* Read current vector number */
   rtems_vector_number vector = VICVectAddr;
@@ -57,37 +57,34 @@ void bsp_interrupt_dispatch( void)
   uint32_t psr = arm_status_irq_enable();
 
   /* Dispatch interrupt handlers */
-  bsp_interrupt_handler_dispatch( vector);
+  bsp_interrupt_handler_dispatch(vector);
 
   /* Restore program status register */
-  arm_status_restore( psr);
+  arm_status_restore(psr);
 
   /* Acknowledge interrupt */
   VICVectAddr = 0;
 }
 
-rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number vector)
+rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
 {
-  if (lpc24xx_irq_is_valid( vector)) {
+  if (lpc24xx_irq_is_valid(vector)) {
     VICIntEnable = 1U << vector;
   }
 
   return RTEMS_SUCCESSFUL;
 }
 
-rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number vector)
+rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
 {
-  if (lpc24xx_irq_is_valid( vector)) {
+  if (lpc24xx_irq_is_valid(vector)) {
     VICIntEnClear = 1U << vector;
   }
 
   return RTEMS_SUCCESSFUL;
 }
 
-/* FIXME */
-void arm_exc_interrupt( void);
-
-rtems_status_code bsp_interrupt_facility_initialize( void)
+rtems_status_code bsp_interrupt_facility_initialize(void)
 {
   volatile uint32_t *addr = VICVectAddrBase;
   volatile uint32_t *prio = VICVectPriorityBase;
@@ -117,12 +114,12 @@ rtems_status_code bsp_interrupt_facility_initialize( void)
   VICVectAddr = 0;
 
   /* Install the IRQ exception handler */
-  _CPU_ISR_install_vector( ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
+  _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
 
   return RTEMS_SUCCESSFUL;
 }
 
-void bsp_interrupt_handler_default( rtems_vector_number vector)
+void bsp_interrupt_handler_default(rtems_vector_number vector)
 {
-  printk( "spurious interrupt: %u\n", vector);
+  printk("spurious interrupt: %u\n", vector);
 }
diff --git a/c/src/lib/libbsp/arm/lpc24xx/misc/dma.c b/c/src/lib/libbsp/arm/lpc24xx/misc/dma.c
index 1f3f896d43..32df2a7fa8 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/misc/dma.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/misc/dma.c
@@ -33,7 +33,7 @@ static bool lpc24xx_dma_channel_occupation [GPDMA_CH_NUMBER];
 void lpc24xx_dma_initialize(void)
 {
   /* Enable module power */
-  lpc24xx_module_enable(LPC24XX_MODULE_GPDMA, 0, LPC24XX_MODULE_PCLK_DEFAULT);
+  lpc24xx_module_enable(LPC24XX_MODULE_GPDMA, LPC24XX_MODULE_PCLK_DEFAULT);
 
   /* Disable module */
   GPDMA_CONFIG = 0;
diff --git a/c/src/lib/libbsp/arm/lpc24xx/misc/io.c b/c/src/lib/libbsp/arm/lpc24xx/misc/io.c
index 6526bf8b7c..340ce2153a 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/misc/io.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/misc/io.c
@@ -36,10 +36,9 @@
 
 #define LPC24XX_IO_ALTERNATE_2 0x3U
 
-#define LPC24XX_IO_ENTRY(mod, idx, cfg, begin_port, begin_index, last_port, last_index, function) \
+#define LPC24XX_IO_ENTRY(mod, cfg, begin_port, begin_index, last_port, last_index, function) \
   { \
     .module = mod, \
-    .index = idx, \
     .config = cfg, \
     .pin_begin = LPC24XX_IO_INDEX_BY_PORT(begin_port, begin_index), \
     .pin_last = LPC24XX_IO_INDEX_BY_PORT(last_port, last_index), \
@@ -47,8 +46,7 @@
   }
 
 typedef struct {
-  unsigned module : 5;
-  unsigned index : 4;
+  unsigned module : 6;
   unsigned config : 4;
   unsigned pin_begin : 8;
   unsigned pin_last : 8;
@@ -59,59 +57,58 @@ typedef void (*lpc24xx_io_iterate_routine)(unsigned /* pin */, unsigned /* funct
 
 static const lpc24xx_io_entry lpc24xx_io_config_table [] = {
   /* UART */
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 0, 0, 0, 2, 0, 3, LPC24XX_IO_ALTERNATE_0),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 1, 0, 0, 15, 0, 16, LPC24XX_IO_ALTERNATE_0),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 1, 1, 2, 0, 2, 1, LPC24XX_IO_ALTERNATE_1),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 1, 2, 3, 16, 3, 17, LPC24XX_IO_ALTERNATE_2),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 2, 0, 0, 10, 0, 11, LPC24XX_IO_ALTERNATE_0),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 2, 1, 2, 8, 2, 9, LPC24XX_IO_ALTERNATE_1),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 2, 2, 4, 22, 4, 23, LPC24XX_IO_ALTERNATE_1),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 3, 0, 0, 0, 0, 1, LPC24XX_IO_ALTERNATE_1),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 3, 1, 0, 25, 0, 26, LPC24XX_IO_ALTERNATE_2),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 3, 2, 4, 28, 4, 29, LPC24XX_IO_ALTERNATE_2),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_0, 0, 0, 2, 0, 3, LPC24XX_IO_ALTERNATE_0),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_1, 0, 0, 15, 0, 16, LPC24XX_IO_ALTERNATE_0),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_1, 1, 2, 0, 2, 1, LPC24XX_IO_ALTERNATE_1),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_1, 2, 3, 16, 3, 17, LPC24XX_IO_ALTERNATE_2),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_2, 0, 0, 10, 0, 11, LPC24XX_IO_ALTERNATE_0),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_2, 1, 2, 8, 2, 9, LPC24XX_IO_ALTERNATE_1),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_2, 2, 4, 22, 4, 23, LPC24XX_IO_ALTERNATE_1),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_3, 0, 0, 0, 0, 1, LPC24XX_IO_ALTERNATE_1),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_3, 1, 0, 25, 0, 26, LPC24XX_IO_ALTERNATE_2),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART_3, 2, 4, 28, 4, 29, LPC24XX_IO_ALTERNATE_2),
 
   /* Ethernet */
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 0, 1, 0, 1, 17, LPC24XX_IO_ALTERNATE_0),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 1, 1, 0, 1, 1, LPC24XX_IO_ALTERNATE_0),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 1, 1, 4, 1, 4, LPC24XX_IO_ALTERNATE_0),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 1, 1, 8, 1, 10, LPC24XX_IO_ALTERNATE_0),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 1, 1, 14, 1, 17, LPC24XX_IO_ALTERNATE_0),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 1, 0, 1, 17, LPC24XX_IO_ALTERNATE_0),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 1, 1, 0, 1, 1, LPC24XX_IO_ALTERNATE_0),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 1, 1, 4, 1, 4, LPC24XX_IO_ALTERNATE_0),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 1, 1, 8, 1, 10, LPC24XX_IO_ALTERNATE_0),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 1, 1, 14, 1, 17, LPC24XX_IO_ALTERNATE_0),
 
   /* ADC */
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ADC, 0, 0, 0, 12, 0, 13, LPC24XX_IO_ALTERNATE_2),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ADC, 0, 0, 12, 0, 13, LPC24XX_IO_ALTERNATE_2),
 
   /* I2C */
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 0, 0, 0, 27, 0, 28, LPC24XX_IO_ALTERNATE_0),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 1, 0, 0, 0, 0, 1, LPC24XX_IO_ALTERNATE_2),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 1, 1, 0, 19, 0, 20, LPC24XX_IO_ALTERNATE_2),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 1, 2, 2, 14, 2, 15, LPC24XX_IO_ALTERNATE_2),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 2, 0, 0, 10, 0, 11, LPC24XX_IO_ALTERNATE_1),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 2, 1, 2, 30, 2, 31, LPC24XX_IO_ALTERNATE_2),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 2, 2, 4, 20, 4, 21, LPC24XX_IO_ALTERNATE_1),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C_0, 0, 0, 27, 0, 28, LPC24XX_IO_ALTERNATE_0),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C_1, 0, 0, 0, 0, 1, LPC24XX_IO_ALTERNATE_2),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C_1, 1, 0, 19, 0, 20, LPC24XX_IO_ALTERNATE_2),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C_1, 2, 2, 14, 2, 15, LPC24XX_IO_ALTERNATE_2),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C_2, 0, 0, 10, 0, 11, LPC24XX_IO_ALTERNATE_1),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C_2, 1, 2, 30, 2, 31, LPC24XX_IO_ALTERNATE_2),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C_2, 2, 4, 20, 4, 21, LPC24XX_IO_ALTERNATE_1),
 
   /* SSP */
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 0, 0, 0, 15, 0, 18, LPC24XX_IO_ALTERNATE_1),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 0, 1, 1, 20, 0, 21, LPC24XX_IO_ALTERNATE_2),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 0, 1, 1, 23, 0, 24, LPC24XX_IO_ALTERNATE_2),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 0, 2, 2, 22, 2, 23, LPC24XX_IO_ALTERNATE_2),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 0, 2, 2, 26, 2, 27, LPC24XX_IO_ALTERNATE_2),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 1, 0, 0, 6, 0, 9, LPC24XX_IO_ALTERNATE_1),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 1, 1, 0, 12, 0, 13, LPC24XX_IO_ALTERNATE_1),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 1, 1, 0, 14, 0, 14, LPC24XX_IO_ALTERNATE_2),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 1, 1, 1, 31, 1, 31, LPC24XX_IO_ALTERNATE_1),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 1, 2, 4, 20, 4, 23, LPC24XX_IO_ALTERNATE_2),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_0, 0, 0, 15, 0, 18, LPC24XX_IO_ALTERNATE_1),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_0, 1, 1, 20, 0, 21, LPC24XX_IO_ALTERNATE_2),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_0, 1, 1, 23, 0, 24, LPC24XX_IO_ALTERNATE_2),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_0, 2, 2, 22, 2, 23, LPC24XX_IO_ALTERNATE_2),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_0, 2, 2, 26, 2, 27, LPC24XX_IO_ALTERNATE_2),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_1, 0, 0, 6, 0, 9, LPC24XX_IO_ALTERNATE_1),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_1, 1, 0, 12, 0, 13, LPC24XX_IO_ALTERNATE_1),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_1, 1, 0, 14, 0, 14, LPC24XX_IO_ALTERNATE_2),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_1, 1, 1, 31, 1, 31, LPC24XX_IO_ALTERNATE_1),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP_1, 2, 4, 20, 4, 23, LPC24XX_IO_ALTERNATE_2),
 
   /* USB */
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_USB, 0, 0, 0, 29, 0, 30, LPC24XX_IO_ALTERNATE_0),
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_USB, 0, 0, 1, 19, 1, 19, LPC24XX_IO_ALTERNATE_1),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_USB, 0, 0, 29, 0, 30, LPC24XX_IO_ALTERNATE_0),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_USB, 0, 1, 19, 1, 19, LPC24XX_IO_ALTERNATE_1),
 
   /* Terminate */
-  LPC24XX_IO_ENTRY(LPC24XX_MODULE_COUNT, 0, 0, 0, 0, 0, 0, 0),
+  LPC24XX_IO_ENTRY(LPC24XX_MODULE_COUNT, 0, 0, 0, 0, 0, 0),
 };
 
 static rtems_status_code lpc24xx_io_iterate(
   lpc24xx_module module,
-  unsigned index,
   unsigned config,
   lpc24xx_io_iterate_routine routine
 )
@@ -120,7 +117,7 @@ static rtems_status_code lpc24xx_io_iterate(
   const lpc24xx_io_entry *e = &lpc24xx_io_config_table [0];
 
   while (e->module != LPC24XX_MODULE_COUNT) {
-    if (e->module == module && e->index == index && e->config == config) {
+    if (e->module == module && e->config == config) {
       unsigned pin = e->pin_begin;
       unsigned last = e->pin_last;
       unsigned function = e->pin_function;
@@ -172,20 +169,18 @@ static void lpc24xx_io_do_release(unsigned pin, unsigned function)
 
 rtems_status_code lpc24xx_io_config(
   lpc24xx_module module,
-  unsigned index,
   unsigned config
 )
 {
-  return lpc24xx_io_iterate(module, index, config, lpc24xx_io_do_config);
+  return lpc24xx_io_iterate(module, config, lpc24xx_io_do_config);
 }
 
 rtems_status_code lpc24xx_io_release(
   lpc24xx_module module,
-  unsigned index,
   unsigned config
 )
 {
-  return lpc24xx_io_iterate(module, index, config, lpc24xx_io_do_release);
+  return lpc24xx_io_iterate(module, config, lpc24xx_io_do_release);
 }
 
 rtems_status_code lpc24xx_gpio_config(
@@ -239,197 +234,102 @@ rtems_status_code lpc24xx_gpio_config(
   return RTEMS_SUCCESSFUL;
 }
 
+#define LPC24XX_MODULE_ENTRY(mod, pwr, clk, idx) \
+  [mod] = { \
+    .power = pwr, \
+    .clock = clk, \
+    .index = idx \
+  }
+
+typedef struct {
+  unsigned char power : 1;
+  unsigned char clock : 1;
+  unsigned char index : 6;
+} lpc24xx_module_entry;
+
+static const lpc24xx_module_entry lpc24xx_module_table [] = {
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_ACF, 0, 1, 15),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_ADC, 1, 1, 12),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_BAT_RAM, 0, 1, 16),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_CAN_0, 1, 1, 13),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_CAN_1, 1, 1, 14),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_DAC, 0, 1, 11),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_EMC, 1, 0, 11),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_ETHERNET, 1, 0, 30),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_GPDMA, 1, 1, 29),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_GPIO, 0, 1, 17),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_I2C_0, 1, 1, 7),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_I2C_1, 1, 1, 19),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_I2C_2, 1, 1, 26),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_I2S, 1, 1, 27),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_LCD, 1, 1, 20),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_MCI, 1, 1, 28),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_PCB, 0, 1, 18),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_PWM_0, 1, 1, 5),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_PWM_1, 1, 1, 6),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_RTC, 1, 1, 9),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SPI, 1, 1, 8),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SSP_0, 1, 1, 21),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SSP_1, 1, 1, 10),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SYSCON, 0, 1, 30),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_TIMER_0, 1, 1, 1),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_TIMER_1, 1, 1, 2),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_TIMER_2, 1, 1, 22),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_TIMER_3, 1, 1, 23),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_UART_0, 1, 1, 3),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_UART_1, 1, 1, 4),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_UART_2, 1, 1, 24),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_UART_3, 1, 1, 25),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_USB, 1, 0, 31),
+  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_WDT, 0, 1, 0)
+};
+
 static rtems_status_code lpc24xx_module_do_enable(
   lpc24xx_module module,
-  unsigned index,
   lpc24xx_module_clock clock,
   bool enable
 )
 {
-  const unsigned NO_POWER = 32U;
-  const unsigned INVALID = 33U;
-  unsigned power_bit = INVALID;
-  unsigned clock_shift = INVALID;
-
-  /* Check clock value */
-  if ((clock & ~LPC24XX_MODULE_CLOCK_MASK) != 0U) {
-    return RTEMS_INVALID_NUMBER;
-  }
+  rtems_interrupt_level level;
+  bool has_power = false;
+  bool has_clock = false;
+  unsigned index = 0;
 
-  /* Get power bit */
-  switch (module) {
-    case LPC24XX_MODULE_ACF:
-      if (index == 0) {
-        power_bit = NO_POWER;
-        clock_shift = 30U;
-      }
-      break;
-    case LPC24XX_MODULE_ADC:
-      if (index == 0) {
-        power_bit = 12U;
-      }
-      break;
-    case LPC24XX_MODULE_BAT_RAM:
-      if (index == 0) {
-        power_bit = NO_POWER;
-        clock_shift = 32U;
-      }
-      break;
-    case LPC24XX_MODULE_CAN:
-      if (index < 2) {
-        power_bit = 13U + index;
-      }
-      break;
-    case LPC24XX_MODULE_DAC:
-      if (index == 0) {
-        power_bit = NO_POWER;
-        clock_shift = 22U;
-      }
-      break;
-    case LPC24XX_MODULE_EMC:
-      if (index == 0) {
-        power_bit = 11U;
-      }
-      break;
-    case LPC24XX_MODULE_ETHERNET:
-      if (index == 0) {
-        power_bit = 30U;
-      }
-      break;
-    case LPC24XX_MODULE_GPDMA:
-      if (index == 0) {
-        power_bit = 29U;
-      }
-      break;
-    case LPC24XX_MODULE_GPIO:
-      if (index == 0) {
-        power_bit = NO_POWER;
-        clock_shift = 34U;
-      }
-      break;
-    case LPC24XX_MODULE_I2C:
-      switch (index) {
-        case 0U:
-          power_bit = 7U;
-          break;
-        case 1U:
-          power_bit = 19U;
-          break;
-        case 2U:
-          power_bit = 26U;
-          break;
-      }
-      break;
-    case LPC24XX_MODULE_I2S:
-      if (index == 0) {
-        power_bit = 27U;
-      }
-      break;
-    case LPC24XX_MODULE_LCD:
-      if (index == 0) {
-        power_bit = 20U;
-      }
-      break;
-    case LPC24XX_MODULE_MCI:
-      if (index == 0) {
-        power_bit = 28U;
-      }
-      break;
-    case LPC24XX_MODULE_PCB:
-      if (index == 0) {
-        power_bit = NO_POWER;
-        clock_shift = 36U;
-      }
-      break;
-    case LPC24XX_MODULE_PWM:
-      if (index < 2) {
-        power_bit = 5U + index;
-      }
-      break;
-    case LPC24XX_MODULE_RTC:
-      if (index == 0) {
-        power_bit = 9U;
-      }
-      break;
-    case LPC24XX_MODULE_SPI:
-      if (index == 0) {
-        power_bit = 8U;
-      }
-      break;
-    case LPC24XX_MODULE_SSP:
-      switch (index) {
-        case 0U:
-          power_bit = 21U;
-          break;
-        case 1U:
-          power_bit = 10U;
-          break;
-      }
-      break;
-    case LPC24XX_MODULE_SYSCON:
-      if (index == 0) {
-        power_bit = NO_POWER;
-        clock_shift = 60U;
-      }
-      break;
-    case LPC24XX_MODULE_TIMER:
-      if (index < 2) {
-        power_bit = 1U + index;
-      } else if (index < 4) {
-        power_bit = 20U + index;
-      }
-      break;
-    case LPC24XX_MODULE_UART:
-      if (index < 2) {
-        power_bit = 3U + index;
-      } else if (index < 4) {
-        power_bit = 22U + index;
-      }
-      break;
-    case LPC24XX_MODULE_USB:
-      if (index == 0) {
-        power_bit = 31U;
-      }
-      break;
-    case LPC24XX_MODULE_WDT:
-      if (index == 0) {
-        power_bit = NO_POWER;
-        clock_shift = 0U;
-      }
-      break;
-    default:
+  if ((unsigned) module >= LPC24XX_MODULE_COUNT) {
       return RTEMS_INVALID_ID;
   }
 
-  /* Check power bit */
-  if (power_bit == INVALID) {
-    return RTEMS_INVALID_ID;
+  if ((clock & ~LPC24XX_MODULE_CLOCK_MASK) != 0U) {
+    return RTEMS_INVALID_NUMBER;
   }
 
-  /* Get clock shift */
-  if (clock_shift == INVALID) {
-    clock_shift = power_bit << 1U;
-  }
+  has_power = lpc24xx_module_table [module].power;
+  has_clock = lpc24xx_module_table [module].clock;
+  index = lpc24xx_module_table [module].index;
 
   /* Enable or disable module */
   if (enable) {
-    rtems_interrupt_level level;
-
-    rtems_interrupt_disable(level);
-    PCONP |= 1U << power_bit;
-    rtems_interrupt_enable(level);
+    if (has_power) {
+      rtems_interrupt_disable(level);
+      PCONP |= 1U << index;
+      rtems_interrupt_enable(level);
+    }
 
     if (module != LPC24XX_MODULE_USB) {
-      rtems_interrupt_disable(level);
-      if (clock_shift < 32U) {
-        PCLKSEL0 = (PCLKSEL0 & ~(LPC24XX_MODULE_CLOCK_MASK << clock_shift))
-            | (clock << clock_shift);
-      } else {
-        clock_shift -= 32U;
-        PCLKSEL1 = (PCLKSEL1 & ~(LPC24XX_MODULE_CLOCK_MASK << clock_shift))
-            | (clock << clock_shift);
+      if (has_clock) {
+        unsigned clock_shift = 2U * index;
+
+        rtems_interrupt_disable(level);
+        if (clock_shift < 32U) {
+          PCLKSEL0 = (PCLKSEL0 & ~(LPC24XX_MODULE_CLOCK_MASK << clock_shift))
+              | (clock << clock_shift);
+        } else {
+          clock_shift -= 32U;
+          PCLKSEL1 = (PCLKSEL1 & ~(LPC24XX_MODULE_CLOCK_MASK << clock_shift))
+              | (clock << clock_shift);
+        }
+        rtems_interrupt_enable(level);
       }
-      rtems_interrupt_enable(level);
     } else {
       unsigned pllclk = lpc24xx_pllclk();
       unsigned usbsel = pllclk / 48000000U - 1U;
@@ -441,11 +341,11 @@ static rtems_status_code lpc24xx_module_do_enable(
       USBCLKCFG = usbsel;
     }
   } else {
-    rtems_interrupt_level level;
-
-    rtems_interrupt_disable(level);
-    PCONP &= ~(1U << power_bit);
-    rtems_interrupt_enable(level);
+    if (has_power) {
+      rtems_interrupt_disable(level);
+      PCONP &= ~(1U << index);
+      rtems_interrupt_enable(level);
+    }
   }
 
   return RTEMS_SUCCESSFUL;
@@ -453,17 +353,15 @@ static rtems_status_code lpc24xx_module_do_enable(
 
 rtems_status_code lpc24xx_module_enable(
   lpc24xx_module module,
-  unsigned index,
   lpc24xx_module_clock clock
 )
 {
-  return lpc24xx_module_do_enable(module, index, clock, true);
+  return lpc24xx_module_do_enable(module, clock, true);
 }
 
 rtems_status_code lpc24xx_module_disable(
-  lpc24xx_module module,
-  unsigned index
+  lpc24xx_module module
 )
 {
-  return lpc24xx_module_do_enable(module, index, 0U, false);
+  return lpc24xx_module_do_enable(module, 0U, false);
 }
diff --git a/c/src/lib/libbsp/arm/lpc24xx/misc/timer.c b/c/src/lib/libbsp/arm/lpc24xx/misc/timer.c
index e9d44312ab..73ec32693e 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/misc/timer.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/misc/timer.c
@@ -49,7 +49,7 @@ uint32_t benchmark_timer_read(void)
   }
 }
 
-void benchmark_timer_disable_subtracting_average_overhead( bool find_average_overhead )
+void benchmark_timer_disable_subtracting_average_overhead(bool find_average_overhead )
 {
   benchmark_timer_find_average_overhead = find_average_overhead;
 }
diff --git a/c/src/lib/libbsp/arm/lpc24xx/network/network.c b/c/src/lib/libbsp/arm/lpc24xx/network/network.c
index 43a73a1240..2941aeaf6b 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/network/network.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/network/network.c
@@ -899,15 +899,14 @@ static void lpc24xx_eth_interface_init(void *arg)
     /* Enable module power */
     lpc24xx_module_enable(
       LPC24XX_MODULE_ETHERNET,
-      0,
       LPC24XX_MODULE_PCLK_DEFAULT
     );
 
     /* Module IO configuration */
     #ifdef LPC24XX_ETHERNET_RMII
-    	lpc24xx_io_config(LPC24XX_MODULE_ETHERNET, 0, 0);
+    	lpc24xx_io_config(LPC24XX_MODULE_ETHERNET, 0);
     #else
-    	lpc24xx_io_config(LPC24XX_MODULE_ETHERNET, 0, 1);
+    	lpc24xx_io_config(LPC24XX_MODULE_ETHERNET, 1);
     #endif
 
     /* Soft reset */
diff --git a/c/src/lib/libbsp/arm/lpc24xx/preinstall.am b/c/src/lib/libbsp/arm/lpc24xx/preinstall.am
index ce8a124ff2..3b145cd6a0 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/preinstall.am
+++ b/c/src/lib/libbsp/arm/lpc24xx/preinstall.am
@@ -81,6 +81,10 @@ $(PROJECT_INCLUDE)/bsp/start.h: ../shared/include/start.h $(PROJECT_INCLUDE)/bsp
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/start.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/start.h
 
+$(PROJECT_INCLUDE)/bsp/lpc-timer.h: ../shared/lpc/include/lpc-timer.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc-timer.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc-timer.h
+
 $(PROJECT_INCLUDE)/bsp/irq-config.h: include/irq-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-config.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-config.h
@@ -113,6 +117,10 @@ $(PROJECT_INCLUDE)/bsp/io.h: include/io.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/io.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/io.h
 
+$(PROJECT_INCLUDE)/bsp/lpc-clock-config.h: include/lpc-clock-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc-clock-config.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc-clock-config.h
+
 $(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
diff --git a/c/src/lib/libbsp/arm/lpc24xx/rtc/rtc-config.c b/c/src/lib/libbsp/arm/lpc24xx/rtc/rtc-config.c
index e2cec3132a..e44797e075 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/rtc/rtc-config.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/rtc/rtc-config.c
@@ -25,10 +25,10 @@
 
 #define LPC24XX_RTC_NUMBER 1
 
-static void lpc24xx_rtc_initialize( int minor)
+static void lpc24xx_rtc_initialize(int minor)
 {
   /* Enable module power */
-  lpc24xx_module_enable( LPC24XX_MODULE_RTC, 0, LPC24XX_MODULE_PCLK_DEFAULT);
+  lpc24xx_module_enable(LPC24XX_MODULE_RTC, LPC24XX_MODULE_PCLK_DEFAULT);
 
   /* Enable the RTC and use external clock */
   RTC_CCR = RTC_CCR_CLKEN | RTC_CCR_CLKSRC;
@@ -42,7 +42,7 @@ static void lpc24xx_rtc_initialize( int minor)
   RTC_ILR = RTC_ILR_RTCCIF | RTC_ILR_RTCALF | RTC_ILR_RTSSF;
 }
 
-static int lpc24xx_rtc_get_time( int minor, rtems_time_of_day *tod)
+static int lpc24xx_rtc_get_time(int minor, rtems_time_of_day *tod)
 {
   tod->ticks = 0;
   tod->second = RTC_SEC;
@@ -55,7 +55,7 @@ static int lpc24xx_rtc_get_time( int minor, rtems_time_of_day *tod)
   return 0;
 }
 
-static int lpc24xx_rtc_set_time( int minor, const rtems_time_of_day *tod)
+static int lpc24xx_rtc_set_time(int minor, const rtems_time_of_day *tod)
 {
   RTC_SEC = tod->second;
   RTC_MIN = tod->minute;
@@ -67,7 +67,7 @@ static int lpc24xx_rtc_set_time( int minor, const rtems_time_of_day *tod)
   return 0;
 }
 
-static bool lpc24xx_rtc_probe( int minor)
+static bool lpc24xx_rtc_probe(int minor)
 {
   return true;
 }
diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/bspreset.c b/c/src/lib/libbsp/arm/lpc24xx/startup/bspreset.c
index fb3eaa7b4b..f38ce1a46c 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/startup/bspreset.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/startup/bspreset.c
@@ -23,11 +23,11 @@
 #include <bsp/bootcard.h>
 #include <bsp/lpc24xx.h>
 
-void bsp_reset( void)
+void bsp_reset(void)
 {
   rtems_interrupt_level level;
 
-  rtems_interrupt_disable( level);
+  rtems_interrupt_disable(level);
 
   /* Trigger watchdog reset */
   WDCLKSEL = 0;
diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/bspstart.c b/c/src/lib/libbsp/arm/lpc24xx/startup/bspstart.c
index 6090cce8ea..76e1aa79aa 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/startup/bspstart.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/startup/bspstart.c
@@ -33,15 +33,15 @@
 void bsp_start(void)
 {
   /* Initialize Timer 1 */
-  lpc24xx_module_enable(LPC24XX_MODULE_TIMER, 1, LPC24XX_MODULE_CCLK);
+  lpc24xx_module_enable(LPC24XX_MODULE_TIMER_1, LPC24XX_MODULE_CCLK);
 
   /* Initialize standard timer */
   lpc24xx_timer_initialize();
 
   /* Initialize console */
   #ifdef LPC24XX_CONFIG_CONSOLE
-    lpc24xx_module_enable(LPC24XX_MODULE_UART, 0, LPC24XX_MODULE_CCLK);
-    lpc24xx_io_config(LPC24XX_MODULE_UART, 0, LPC24XX_CONFIG_CONSOLE);
+    lpc24xx_module_enable(LPC24XX_MODULE_UART_0, LPC24XX_MODULE_CCLK);
+    lpc24xx_io_config(LPC24XX_MODULE_UART_0, LPC24XX_CONFIG_CONSOLE);
     U0LCR = 0;
     U0IER = 0;
     U0LCR = 0x80;
@@ -60,23 +60,25 @@ void bsp_start(void)
   lpc24xx_dma_initialize();
 
   /* Task stacks */
-  bsp_stack_initialize(
-    bsp_section_stack_begin,
-    (uintptr_t) bsp_section_stack_size
-  );
+  #ifdef LPC24XX_SPECIAL_TASK_STACKS_SUPPORT
+    bsp_stack_initialize(
+      bsp_section_stack_begin,
+      (uintptr_t) bsp_section_stack_size
+    );
+  #endif
 
   /* UART configurations */
   #ifdef LPC24XX_CONFIG_UART_1
-    lpc24xx_module_enable(LPC24XX_MODULE_UART, 1, LPC24XX_MODULE_CCLK);
-    lpc24xx_io_config(LPC24XX_MODULE_UART, 1, LPC24XX_CONFIG_UART_1);
+    lpc24xx_module_enable(LPC24XX_MODULE_UART_1, LPC24XX_MODULE_CCLK);
+    lpc24xx_io_config(LPC24XX_MODULE_UART_1, LPC24XX_CONFIG_UART_1);
   #endif
   #ifdef LPC24XX_CONFIG_UART_2
-    lpc24xx_module_enable(LPC24XX_MODULE_UART, 2, LPC24XX_MODULE_CCLK);
-    lpc24xx_io_config(LPC24XX_MODULE_UART, 2, LPC24XX_CONFIG_UART_2);
+    lpc24xx_module_enable(LPC24XX_MODULE_UART_2, LPC24XX_MODULE_CCLK);
+    lpc24xx_io_config(LPC24XX_MODULE_UART_2, LPC24XX_CONFIG_UART_2);
   #endif
   #ifdef LPC24XX_CONFIG_UART_3
-    lpc24xx_module_enable(LPC24XX_MODULE_UART, 3, LPC24XX_MODULE_CCLK);
-    lpc24xx_io_config(LPC24XX_MODULE_UART, 3, LPC24XX_CONFIG_UART_3);
+    lpc24xx_module_enable(LPC24XX_MODULE_UART_3, LPC24XX_MODULE_CCLK);
+    lpc24xx_io_config(LPC24XX_MODULE_UART_3, LPC24XX_CONFIG_UART_3);
   #endif
 }
 
diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c
index 1c899a00ad..732d30ddf5 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c
@@ -26,8 +26,10 @@
 #include <bsp/lpc24xx.h>
 #include <bsp/linker-symbols.h>
 
+#define BSP_START_SECTION __attribute__((section(".bsp_start")))
+
 #ifdef LPC24XX_EMC_MICRON
-  static void __attribute__((section(".bsp_start"))) lpc24xx_ram_test_32(void)
+  static void BSP_START_SECTION lpc24xx_ram_test_32(void)
   {
     #ifdef LPC24XX_EMC_TEST
       int *begin = (int *) 0xa0000000;
@@ -51,7 +53,7 @@
     #endif
   }
 
-  static void __attribute__((section(".bsp_start"))) lpc24xx_cpu_delay(
+  static void BSP_START_SECTION lpc24xx_cpu_delay(
     unsigned ticks
   )
   {
@@ -69,7 +71,7 @@
 /**
  * @brief EMC initialization hook 0.
  */
-static void __attribute__((section(".bsp_start"))) lpc24xx_init_emc_0(void)
+static void BSP_START_SECTION lpc24xx_init_emc_0(void)
 {
   #ifdef LPC24XX_EMC_NUMONYX
     /*
@@ -131,7 +133,7 @@ static void __attribute__((section(".bsp_start"))) lpc24xx_init_emc_0(void)
 /**
  * @brief EMC initialization hook 1.
  */
-static void __attribute__((section(".bsp_start"))) lpc24xx_init_emc_1(void)
+static void BSP_START_SECTION lpc24xx_init_emc_1(void)
 {
   /* Use normal memory map */
   EMC_CTRL = CLEAR_FLAG(EMC_CTRL, 0x2);
@@ -234,7 +236,7 @@ static void __attribute__((section(".bsp_start"))) lpc24xx_init_emc_1(void)
   #endif
 }
 
-static void __attribute__((section(".bsp_start"))) lpc24xx_pll_config(
+static void BSP_START_SECTION lpc24xx_pll_config(
   uint32_t val
 )
 {
@@ -257,7 +259,7 @@ static void __attribute__((section(".bsp_start"))) lpc24xx_pll_config(
  * @param cclksel Selects the divide value for creating the CPU clock (CCLK)
  * from the PLL output.
  */
-static void __attribute__((section(".bsp_start"))) lpc24xx_set_pll(
+static void BSP_START_SECTION lpc24xx_set_pll(
   unsigned clksrc,
   unsigned nsel,
   unsigned msel,
@@ -313,7 +315,7 @@ static void __attribute__((section(".bsp_start"))) lpc24xx_set_pll(
   lpc24xx_pll_config(PLLCON_PLLE | PLLCON_PLLC);
 }
 
-static void __attribute__((section(".bsp_start"))) lpc24xx_init_pll(void)
+static void BSP_START_SECTION lpc24xx_init_pll(void)
 {
   /* Enable main oscillator */
   if (IS_FLAG_CLEARED(SCS, 0x40)) {
@@ -327,7 +329,7 @@ static void __attribute__((section(".bsp_start"))) lpc24xx_init_pll(void)
   lpc24xx_set_pll(1, 0, 11, 3);
 }
 
-static void __attribute__((section(".bsp_start"))) lpc24xx_clear_bss(void)
+static void BSP_START_SECTION lpc24xx_clear_bss(void)
 {
   const int *end = (const int *) bsp_section_bss_end;
   int *out = (int *) bsp_section_bss_begin;
@@ -339,7 +341,7 @@ static void __attribute__((section(".bsp_start"))) lpc24xx_clear_bss(void)
   }
 }
 
-void __attribute__((section(".bsp_start"))) bsp_start_hook_0(void)
+void BSP_START_SECTION bsp_start_hook_0(void)
 {
   /* Initialize PLL */
   lpc24xx_init_pll();
@@ -348,7 +350,7 @@ void __attribute__((section(".bsp_start"))) bsp_start_hook_0(void)
   lpc24xx_init_emc_0();
 }
 
-void __attribute__((section(".bsp_start"))) bsp_start_hook_1(void)
+void BSP_START_SECTION bsp_start_hook_1(void)
 {
   /* Re-map interrupt vectors to internal RAM */
   MEMMAP = SET_MEMMAP_MAP(MEMMAP, 2);
diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ea b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ea
index ca6b52a4fe..afad88d747 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ea
+++ b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ea
@@ -21,7 +21,7 @@
  *
  * <table>
  *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
- *   <tr><td>.start</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.start</td><td>RAM_EXT</td><td></td></tr>
  *   <tr><td>.vector</td><td>RAM_INT</td><td></td></tr>
  *   <tr><td>.text</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
  *   <tr><td>.rodata</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ncs_ram b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ncs_ram
index 5322c7a725..c3f908b907 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ncs_ram
+++ b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ncs_ram
@@ -21,7 +21,7 @@
  *
  * <table>
  *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
- *   <tr><td>.start</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.start</td><td>RAM_EXT</td><td></td></tr>
  *   <tr><td>.vector</td><td>RAM_INT</td><td></td></tr>
  *   <tr><td>.text</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
  *   <tr><td>.rodata</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ncs_rom_ext b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ncs_rom_ext
index f4518090d4..d35d8cd10d 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ncs_rom_ext
+++ b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ncs_rom_ext
@@ -23,7 +23,7 @@
  *
  * <table>
  *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
- *   <tr><td>.start</td><td>ROM_BOOT</td><td>ROM_BOOT</td></tr>
+ *   <tr><td>.start</td><td>ROM_BOOT</td><td></td></tr>
  *   <tr><td>.vector</td><td>RAM_INT</td><td></td></tr>
  *   <tr><td>.text</td><td>RAM_EXT</td><td>ROM_EXT</td></tr>
  *   <tr><td>.rodata</td><td>RAM_EXT</td><td>ROM_EXT</td></tr>
diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ncs_rom_int b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ncs_rom_int
index a46145d333..044131ba30 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ncs_rom_int
+++ b/c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc24xx_ncs_rom_int
@@ -23,7 +23,7 @@
  *
  * <table>
  *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
- *   <tr><td>.start</td><td>ROM_INT</td><td>ROM_INT</td></tr>
+ *   <tr><td>.start</td><td>ROM_INT</td><td></td></tr>
  *   <tr><td>.vector</td><td>RAM_VEC</td><td></td></tr>
  *   <tr><td>.text</td><td>ROM_INT</td><td>ROM_INT</td></tr>
  *   <tr><td>.rodata</td><td>ROM_INT</td><td>ROM_INT</td></tr>
diff --git a/c/src/lib/libbsp/arm/lpc32xx/.cvsignore b/c/src/lib/libbsp/arm/lpc32xx/.cvsignore
new file mode 100644
index 0000000000..baba64eafa
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/.cvsignore
@@ -0,0 +1,8 @@
+aclocal.m4
+autom4te*.cache
+config.cache
+config.log
+config.status
+configure
+Makefile
+Makefile.in
diff --git a/c/src/lib/libbsp/arm/lpc32xx/ChangeLog b/c/src/lib/libbsp/arm/lpc32xx/ChangeLog
new file mode 100644
index 0000000000..faa574da80
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/ChangeLog
@@ -0,0 +1,9 @@
+2009-12-15	Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* bsp_specs, configure.ac, console/console-config.c, include/bsp.h,
+	include/irq-config.h, include/irq.h, include/lpc32xx.h,
+	include/lpc-clock-config.h, irq/irq.c,
+	make/custom/lpc32xx_phycore.cfg, Makefile.am, misc/timer.c,
+	preinstall.am, README, rtc/rtc-config.c, startup/bspreset.c,
+	startup/bspstart.c, startup/bspstarthooks.c,
+	startup/linkcmds.lpc32xx_phycore: New files.
diff --git a/c/src/lib/libbsp/arm/lpc32xx/Makefile.am b/c/src/lib/libbsp/arm/lpc32xx/Makefile.am
new file mode 100644
index 0000000000..fd866bcdcd
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/Makefile.am
@@ -0,0 +1,142 @@
+##
+#
+# @file
+#
+# @brief Makefile of LibBSP for the LPC32XX boards.
+#
+
+# $Id$
+
+ACLOCAL_AMFLAGS = -I ../../../../aclocal
+
+include $(top_srcdir)/../../../../automake/compile.am
+
+include_bspdir = $(includedir)/bsp
+
+dist_project_lib_DATA = bsp_specs
+
+###############################################################################
+#                  Header                                                     #
+###############################################################################
+
+include_HEADERS = include/bsp.h
+
+nodist_include_HEADERS = ../../shared/include/coverhd.h \
+	include/bspopts.h
+
+nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
+
+include_bsp_HEADERS =
+include_bsp_HEADERS += ../../shared/include/utility.h
+include_bsp_HEADERS += ../../shared/include/irq-generic.h
+include_bsp_HEADERS += ../../shared/include/irq-info.h
+include_bsp_HEADERS += ../../shared/include/stackalloc.h
+include_bsp_HEADERS += ../../shared/tod.h
+include_bsp_HEADERS += ../shared/include/linker-symbols.h
+include_bsp_HEADERS += ../shared/include/start.h
+include_bsp_HEADERS += ../shared/lpc/include/lpc-timer.h
+include_bsp_HEADERS += include/irq-config.h
+include_bsp_HEADERS += include/irq.h
+include_bsp_HEADERS += include/lpc32xx.h
+include_bsp_HEADERS += include/lpc-clock-config.h
+
+include_HEADERS += ../../shared/include/tm27.h
+
+###############################################################################
+#                  Data                                                       #
+###############################################################################
+
+noinst_LIBRARIES = libbspstart.a
+
+libbspstart_a_SOURCES = ../shared/start/start.S
+
+project_lib_DATA = start.$(OBJEXT)
+
+project_lib_DATA += startup/linkcmds
+project_lib_DATA += ../shared/startup/linkcmds.base
+
+EXTRA_DIST = startup/linkcmds.lpc32xx_phycore
+
+###############################################################################
+#                  LibBSP                                                     #
+###############################################################################
+
+noinst_LIBRARIES += libbsp.a
+
+libbsp_a_SOURCES =
+
+# Shared
+libbsp_a_SOURCES += ../../shared/bootcard.c \
+	../../shared/bspclean.c \
+	../../shared/bspgetworkarea.c \
+	../../shared/bsplibc.c \
+	../../shared/bsppost.c \
+	../../shared/bsppredriverhook.c \
+	../../shared/bsppretaskinghook.c \
+	../../shared/gnatinstallhandler.c \
+	../../shared/sbrk.c \
+	../../shared/src/stackalloc.c \
+	../shared/abort/simple_abort.c
+
+# Startup
+libbsp_a_SOURCES += startup/bspstart.c \
+	startup/bspreset.c
+
+# IRQ
+libbsp_a_SOURCES += ../../shared/src/irq-generic.c \
+	../../shared/src/irq-legacy.c \
+	../../shared/src/irq-info.c \
+	../../shared/src/irq-shell.c \
+	../../shared/src/irq-server.c \
+	irq/irq.c
+
+# Console
+libbsp_a_SOURCES += ../../shared/console.c \
+	console/console-config.c
+
+# Clock
+libbsp_a_SOURCES += ../shared/lpc/clock/lpc-clock-config.c \
+	../../../shared/clockdrv_shell.h
+
+# RTC
+libbsp_a_SOURCES += ../../shared/tod.c \
+	rtc/rtc-config.c
+
+# Timer
+libbsp_a_SOURCES += misc/timer.c
+
+# SSP
+
+# I2C
+
+# Start hooks (FIXME: This is brittle.)
+libbsp_a_SOURCES += startup/bspstarthooks.c
+bspstarthooks.o: startup/bspstarthooks.c
+	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS:-mthumb=) \
+	-MT bspstarthooks.o -MD -MP -MF $(DEPDIR)/bspstarthooks.Tpo -c -o bspstarthooks.o \
+	`test -f 'startup/bspstarthooks.c' || echo '$(srcdir)/'`startup/bspstarthooks.c
+
+###############################################################################
+#                  Network                                                    #
+###############################################################################
+
+if HAS_NETWORKING
+
+# noinst_PROGRAMS = network.rel
+
+# network_rel_SOURCES = network/network.c
+# network_rel_CPPFLAGS = $(AM_CPPFLAGS) -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ -D__BSD_VISIBLE
+# network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+# libbsp_a_LIBADD = network.rel
+
+endif
+
+###############################################################################
+#                  Special Rules                                              #
+###############################################################################
+
+DISTCLEANFILES = include/bspopts.h
+
+include $(srcdir)/preinstall.am
+include $(top_srcdir)/../../../../automake/local.am
diff --git a/c/src/lib/libbsp/arm/lpc32xx/README b/c/src/lib/libbsp/arm/lpc32xx/README
new file mode 100644
index 0000000000..97a1546e2d
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/README
@@ -0,0 +1,5 @@
+Development board is phyCORE-LPC3250 RDK.  Basic initialization via stage 1
+bootloader or U-Boot will be assumed.  Drivers:
+
+        o Standard UART 3, 4, 5, 6 (Console = 5, 115200N1)
+        o Clock uses TIMER 0
diff --git a/c/src/lib/libbsp/arm/lpc32xx/bsp_specs b/c/src/lib/libbsp/arm/lpc32xx/bsp_specs
new file mode 100644
index 0000000000..9be7e23eb6
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/bsp_specs
@@ -0,0 +1,13 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+%rename link old_link
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e start}}
+
+*link:
+%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N}
+
+*endfile:
+%{!qrtems: *(old_endfiles)} %{qrtems: crtend.o%s crtn.o%s }
diff --git a/c/src/lib/libbsp/arm/lpc32xx/configure.ac b/c/src/lib/libbsp/arm/lpc32xx/configure.ac
new file mode 100644
index 0000000000..6febd9d350
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/configure.ac
@@ -0,0 +1,61 @@
+##
+#
+# @file
+#
+# @brief Configure script of LibBSP for the LPC32XX boards.
+#
+
+AC_PREREQ(2.59)
+AC_INIT([rtems-c-src-lib-libbsp-arm-lpc32xx],[_RTEMS_VERSION],[rtems-bugs@rtems.com])
+AC_CONFIG_SRCDIR([bsp_specs])
+RTEMS_TOP(../../../../../..)
+
+RTEMS_CANONICAL_TARGET_CPU
+AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.9])
+RTEMS_BSP_CONFIGURE
+
+RTEMS_PROG_CC_FOR_TARGET
+RTEMS_CANONICALIZE_TOOLS
+RTEMS_PROG_CCAS
+
+RTEMS_CHECK_NETWORKING
+AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
+
+RTEMS_BSPOPTS_SET([LPC32XX_OSCILLATOR_MAIN],[*],[13000000U])
+RTEMS_BSPOPTS_HELP([LPC32XX_OSCILLATOR_MAIN],[main oscillator frequency in Hz])
+
+RTEMS_BSPOPTS_SET([LPC32XX_OSCILLATOR_RTC],[*],[32768U])
+RTEMS_BSPOPTS_HELP([LPC32XX_OSCILLATOR_RTC],[RTC oscillator frequency in Hz])
+
+RTEMS_BSPOPTS_SET([LPC32XX_ARM_CLK],[*],[208000000U])
+RTEMS_BSPOPTS_HELP([LPC32XX_ARM_CLK],[ARM clock in Hz])
+
+RTEMS_BSPOPTS_SET([LPC32XX_HCLK],[*],[104000000U])
+RTEMS_BSPOPTS_HELP([LPC32XX_HCLK],[AHB bus clock in Hz])
+
+RTEMS_BSPOPTS_SET([LPC32XX_PERIPH_CLK],[*],[13000000U])
+RTEMS_BSPOPTS_HELP([LPC32XX_PERIPH_CLK],[peripheral clock in Hz])
+
+RTEMS_BSPOPTS_SET([LPC32XX_CONFIG_U3CLK],[*],[])
+RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_U3CLK],[clock configuration for UART 3])
+
+RTEMS_BSPOPTS_SET([LPC32XX_CONFIG_U4CLK],[*],[])
+RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_U4CLK],[clock configuration for UART 4])
+
+RTEMS_BSPOPTS_SET([LPC32XX_CONFIG_U5CLK],[*],[0x00001386U])
+RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_U5CLK],[clock configuration for UART 5])
+
+RTEMS_BSPOPTS_SET([LPC32XX_CONFIG_U6CLK],[*],[])
+RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_U6CLK],[clock configuration for UART 6])
+
+RTEMS_BSPOPTS_SET([LPC32XX_CONFIG_UART_CLKMODE],[*],[0x00000200U])
+RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_UART_CLKMODE],[clock mode configuration for UARTs])
+
+RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
+RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
+
+RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
+RTEMS_BSP_LINKCMDS
+
+AC_CONFIG_FILES([Makefile])
+AC_OUTPUT
diff --git a/c/src/lib/libbsp/arm/lpc32xx/console/console-config.c b/c/src/lib/libbsp/arm/lpc32xx/console/console-config.c
new file mode 100644
index 0000000000..1504919a55
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/console/console-config.c
@@ -0,0 +1,139 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx
+ *
+ * @brief Console configuration.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <libchip/serial.h>
+#include <libchip/ns16550.h>
+
+#include <bsp.h>
+#include <bsp/lpc32xx.h>
+#include <bsp/irq.h>
+
+static uint8_t lpc32xx_uart_get_register(uint32_t addr, uint8_t i)
+{
+  volatile uint32_t *reg = (volatile uint32_t *) addr;
+
+  return (uint8_t) reg [i];
+}
+
+static void lpc32xx_uart_set_register(uint32_t addr, uint8_t i, uint8_t val)
+{
+  volatile uint32_t *reg = (volatile uint32_t *) addr;
+
+  reg [i] = val;
+}
+
+rtems_device_minor_number Console_Port_Minor = 0;
+
+/* FIXME: Console selection */
+
+console_tbl Console_Port_Tbl [] = {
+  #ifdef LPC32XX_CONFIG_U5CLK
+    {
+      .sDeviceName = "/dev/ttyS5",
+      .deviceType = SERIAL_NS16550,
+      .pDeviceFns = &ns16550_fns,
+      .deviceProbe = NULL,
+      .pDeviceFlow = NULL,
+      .ulMargin = 16,
+      .ulHysteresis = 8,
+      .pDeviceParams = (void *) 1,
+      .ulCtrlPort1 = LPC32XX_BASE_UART_5,
+      .ulCtrlPort2 = 0,
+      .ulDataPort = LPC32XX_BASE_UART_5,
+      .getRegister = lpc32xx_uart_get_register,
+      .setRegister = lpc32xx_uart_set_register,
+      .getData = NULL,
+      .setData = NULL,
+      .ulClock = 16,
+      .ulIntVector = LPC32XX_IRQ_UART_5
+    },
+  #endif
+  #ifdef LPC32XX_CONFIG_U3CLK
+    {
+      .sDeviceName = "/dev/ttyS3",
+      .deviceType = SERIAL_NS16550,
+      .pDeviceFns = &ns16550_fns,
+      .deviceProbe = NULL,
+      .pDeviceFlow = NULL,
+      .ulMargin = 16,
+      .ulHysteresis = 8,
+      .pDeviceParams = (void *) 1,
+      .ulCtrlPort1 = LPC32XX_BASE_UART_3,
+      .ulCtrlPort2 = 0,
+      .ulDataPort = LPC32XX_BASE_UART_3,
+      .getRegister = lpc32xx_uart_get_register,
+      .setRegister = lpc32xx_uart_set_register,
+      .getData = NULL,
+      .setData = NULL,
+      .ulClock = 16,
+      .ulIntVector = LPC32XX_IRQ_UART_3
+    },
+  #endif
+  #ifdef LPC32XX_CONFIG_U4CLK
+    {
+      .sDeviceName = "/dev/ttyS4",
+      .deviceType = SERIAL_NS16550,
+      .pDeviceFns = &ns16550_fns,
+      .deviceProbe = NULL,
+      .pDeviceFlow = NULL,
+      .ulMargin = 16,
+      .ulHysteresis = 8,
+      .pDeviceParams = (void *) 1,
+      .ulCtrlPort1 = LPC32XX_BASE_UART_4,
+      .ulCtrlPort2 = 0,
+      .ulDataPort = LPC32XX_BASE_UART_4,
+      .getRegister = lpc32xx_uart_get_register,
+      .setRegister = lpc32xx_uart_set_register,
+      .getData = NULL,
+      .setData = NULL,
+      .ulClock = 16,
+      .ulIntVector = LPC32XX_IRQ_UART_4
+    },
+  #endif
+  #ifdef LPC32XX_CONFIG_U6CLK
+    {
+      .sDeviceName = "/dev/ttyS6",
+      .deviceType = SERIAL_NS16550,
+      .pDeviceFns = &ns16550_fns,
+      .deviceProbe = NULL,
+      .pDeviceFlow = NULL,
+      .ulMargin = 16,
+      .ulHysteresis = 8,
+      .pDeviceParams = (void *) 1,
+      .ulCtrlPort1 = LPC32XX_BASE_UART_6,
+      .ulCtrlPort2 = 0,
+      .ulDataPort = LPC32XX_BASE_UART_6,
+      .getRegister = lpc32xx_uart_get_register,
+      .setRegister = lpc32xx_uart_set_register,
+      .getData = NULL,
+      .setData = NULL,
+      .ulClock = 16,
+      .ulIntVector = LPC32XX_IRQ_UART_6
+    },
+  #endif
+};
+
+#define LPC32XX_UART_COUNT \
+  (sizeof(Console_Port_Tbl) / sizeof(Console_Port_Tbl [0]))
+
+unsigned long Console_Port_Count = LPC32XX_UART_COUNT;
+
+console_data Console_Port_Data [LPC32XX_UART_COUNT];
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h b/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h
new file mode 100644
index 0000000000..a42dd7b0be
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h
@@ -0,0 +1,99 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx
+ *
+ * @brief Global BSP definitions.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_LPC32XX_BSP_H
+#define LIBBSP_ARM_LPC32XX_BSP_H
+
+#include <bspopts.h>
+
+#include <rtems.h>
+#include <rtems/console.h>
+#include <rtems/clockdrv.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define BSP_FEATURE_IRQ_EXTENSION
+
+#ifndef ASM
+
+struct rtems_bsdnet_ifconfig;
+
+/**
+ * @defgroup lpc32xx LPC32XX Support
+ *
+ * @ingroup bsp_kit
+ *
+ * @brief LPC32XX support package.
+ *
+ * @{
+ */
+
+/**
+ * @brief Network driver attach and detach function.
+ */
+int lpc32xx_eth_attach_detach(
+  struct rtems_bsdnet_ifconfig *config,
+  int attaching
+);
+
+/**
+ * @brief Standard network driver attach and detach function.
+ */
+#define RTEMS_BSP_NETWORK_DRIVER_ATTACH	lpc32xx_eth_attach_detach
+
+/**
+ * @brief Standard network driver name.
+ */
+#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
+
+/**
+ * @brief Optimized idle task.
+ *
+ * This idle task sets the power mode to idle.  This causes the processor clock
+ * to be stopped, while on-chip peripherals remain active.  Any enabled
+ * interrupt from a peripheral or an external interrupt source will cause the
+ * processor to resume execution.
+ *
+ * To enable the idle task use the following in the system configuration:
+ *
+ * @code
+ * #include <bsp.h>
+ *
+ * #define CONFIGURE_INIT
+ *
+ * #define CONFIGURE_IDLE_TASK_BODY lpc32xx_idle
+ *
+ * #include <confdefs.h>
+ * @endcode
+ */
+void *lpc32xx_idle(uintptr_t ignored);
+
+/** @} */
+
+#endif /* ASM */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_LPC32XX_BSP_H */
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in b/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in
new file mode 100644
index 0000000000..bcf5f8fa42
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in
@@ -0,0 +1,61 @@
+/* include/bspopts.h.in.  Generated from configure.ac by autoheader.  */
+
+/* If defined, then the BSP Framework will put a non-zero pattern into the
+   RTEMS Workspace and C program heap. This should assist in finding code that
+   assumes memory starts set to zero. */
+#undef BSP_DIRTY_MEMORY
+
+/* If defined, print a message and wait until pressed before resetting board
+   when application exits. */
+#undef BSP_PRESS_KEY_FOR_RESET
+
+/* If defined, reset the board when the application exits. */
+#undef BSP_RESET_BOARD_AT_EXIT
+
+/* reset vector address for BSP start */
+#undef BSP_START_RESET_VECTOR
+
+/* ARM clock in Hz */
+#undef LPC32XX_ARM_CLK
+
+/* clock configuration for UART 3 */
+#undef LPC32XX_CONFIG_U3CLK
+
+/* clock configuration for UART 4 */
+#undef LPC32XX_CONFIG_U4CLK
+
+/* clock configuration for UART 5 */
+#undef LPC32XX_CONFIG_U5CLK
+
+/* clock configuration for UART 6 */
+#undef LPC32XX_CONFIG_U6CLK
+
+/* clock mode configuration for UARTs */
+#undef LPC32XX_CONFIG_UART_CLKMODE
+
+/* AHB bus clock in Hz */
+#undef LPC32XX_HCLK
+
+/* main oscillator frequency in Hz */
+#undef LPC32XX_OSCILLATOR_MAIN
+
+/* RTC oscillator frequency in Hz */
+#undef LPC32XX_OSCILLATOR_RTC
+
+/* peripheral clock in Hz */
+#undef LPC32XX_PERIPH_CLK
+
+/* Define to the address where bug reports for this package should be sent. */
+#undef PACKAGE_BUGREPORT
+
+/* Define to the full name of this package. */
+#undef PACKAGE_NAME
+
+/* Define to the full name and version of this package. */
+#undef PACKAGE_STRING
+
+/* Define to the one symbol short name of this package. */
+#undef PACKAGE_TARNAME
+
+/* Define to the version of this package. */
+#undef PACKAGE_VERSION
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/irq-config.h b/c/src/lib/libbsp/arm/lpc32xx/include/irq-config.h
new file mode 100644
index 0000000000..659e2ea56e
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/irq-config.h
@@ -0,0 +1,27 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief Interrupt support configuration.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_LPC32XX_IRQ_CONFIG_H
+#define LIBBSP_ARM_LPC32XX_IRQ_CONFIG_H
+
+#include <bsp/irq.h>
+
+#endif /* LIBBSP_ARM_LPC32XX_IRQ_CONFIG_H */
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/irq.h b/c/src/lib/libbsp/arm/lpc32xx/include/irq.h
new file mode 100644
index 0000000000..62d28fe7e0
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/irq.h
@@ -0,0 +1,165 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief Interrupt definitions.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_LPC32XX_IRQ_H
+#define LIBBSP_ARM_LPC32XX_IRQ_H
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+#define LPC32XX_IRQ_INDEX(module, subindex) ((module) + (subindex))
+
+#define LPC32XX_IRQ_MODULE_MIC 0U
+#define LPC32XX_IRQ_MODULE_SIC_1 32U
+#define LPC32XX_IRQ_MODULE_SIC_2 64U
+#define LPC32XX_IRQ_MODULE_COUNT 3U
+
+/* MIC interrupts */
+#define LPC32XX_IRQ_SIC_1_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 0)
+#define LPC32XX_IRQ_SIC_2_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 1)
+#define LPC32XX_IRQ_TIMER_4_OR_MCPWM LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 3)
+#define LPC32XX_IRQ_TIMER_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 4)
+#define LPC32XX_IRQ_TIMER_HS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 5)
+#define LPC32XX_IRQ_WDG LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 6)
+#define LPC32XX_IRQ_UART_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 7)
+#define LPC32XX_IRQ_UART_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 8)
+#define LPC32XX_IRQ_UART_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 9)
+#define LPC32XX_IRQ_UART_6 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 10)
+#define LPC32XX_IRQ_NAND_FLASH LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 11)
+#define LPC32XX_IRQ_SDCARD_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 13)
+#define LPC32XX_IRQ_LCD LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 14)
+#define LPC32XX_IRQ_SDCARD_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 15)
+#define LPC32XX_IRQ_TIMER_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 16)
+#define LPC32XX_IRQ_TIMER_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 17)
+#define LPC32XX_IRQ_TIMER_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 18)
+#define LPC32XX_IRQ_TIMER_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 19)
+#define LPC32XX_IRQ_SSP_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 20)
+#define LPC32XX_IRQ_SSP_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 21)
+#define LPC32XX_IRQ_I2S_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 22)
+#define LPC32XX_IRQ_I2S_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 23)
+#define LPC32XX_IRQ_UART_7 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 24)
+#define LPC32XX_IRQ_UART_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 25)
+#define LPC32XX_IRQ_UART_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 26)
+#define LPC32XX_IRQ_TIMER_MS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 27)
+#define LPC32XX_IRQ_DMA LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 28)
+#define LPC32XX_IRQ_ETHERNET LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 29)
+#define LPC32XX_IRQ_SIC_1_FIQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 30)
+#define LPC32XX_IRQ_SIC_2_FIQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 31)
+
+/* SIC 1 interrupts */
+#define LPC32XX_IRQ_JTAG_COMM_TX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 1)
+#define LPC32XX_IRQ_JTAG_COMM_RX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 2)
+#define LPC32XX_IRQ_GPI_28 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 4)
+#define LPC32XX_IRQ_TS_P LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 6)
+#define LPC32XX_IRQ_TS_IRQ_OR_ADC LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 7)
+#define LPC32XX_IRQ_TS_AUX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 8)
+#define LPC32XX_IRQ_SPI_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 12)
+#define LPC32XX_IRQ_PLL_USB LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 13)
+#define LPC32XX_IRQ_PLL_HCLK LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 14)
+#define LPC32XX_IRQ_PLL_397 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 17)
+#define LPC32XX_IRQ_I2C_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 18)
+#define LPC32XX_IRQ_I2C_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 19)
+#define LPC32XX_IRQ_RTC LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 20)
+#define LPC32XX_IRQ_KEYSCAN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 22)
+#define LPC32XX_IRQ_SPI_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 23)
+#define LPC32XX_IRQ_SW LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 24)
+#define LPC32XX_IRQ_USB_OTG_TIMER LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 25)
+#define LPC32XX_IRQ_USB_OTG_ATX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 26)
+#define LPC32XX_IRQ_USB_HOST LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 27)
+#define LPC32XX_IRQ_USB_DEV_DMA LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 28)
+#define LPC32XX_IRQ_USB_DEV_LP LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 29)
+#define LPC32XX_IRQ_USB_DEV_HP LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 30)
+#define LPC32XX_IRQ_USB_I2C LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 31)
+
+/* SIC 2 interrupts */
+#define LPC32XX_IRQ_GPIO_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 0)
+#define LPC32XX_IRQ_GPIO_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 1)
+#define LPC32XX_IRQ_GPIO_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 2)
+#define LPC32XX_IRQ_GPIO_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 3)
+#define LPC32XX_IRQ_GPIO_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 4)
+#define LPC32XX_IRQ_GPIO_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 5)
+#define LPC32XX_IRQ_SPI_2_DATAIN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 6)
+#define LPC32XX_IRQ_UART_2_HCTS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 7)
+#define LPC32XX_IRQ_GPIO_P0_P1_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 8)
+#define LPC32XX_IRQ_GPI_8 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 9)
+#define LPC32XX_IRQ_GPI_9 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 10)
+#define LPC32XX_IRQ_GPI_19 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 11)
+#define LPC32XX_IRQ_UART_7_HCTS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 12)
+#define LPC32XX_IRQ_GPI_7 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 15)
+#define LPC32XX_IRQ_SDIO LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 18)
+#define LPC32XX_IRQ_UART_5_RX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 19)
+#define LPC32XX_IRQ_SPI_1_DATAIN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 20)
+#define LPC32XX_IRQ_GPI_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 22)
+#define LPC32XX_IRQ_GPI_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 23)
+#define LPC32XX_IRQ_GPI_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 24)
+#define LPC32XX_IRQ_GPI_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 25)
+#define LPC32XX_IRQ_GPI_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 26)
+#define LPC32XX_IRQ_GPI_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 27)
+#define LPC32XX_IRQ_GPI_6 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 28)
+#define LPC32XX_IRQ_SYSCLK LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 31)
+
+#define LPC32XX_IRQ_PRIORITY_VALUE_MIN 0U
+#define LPC32XX_IRQ_PRIORITY_VALUE_MAX 15U
+#define LPC32XX_IRQ_PRIORITY_COUNT (LPC32XX_IRQ_PRIORITY_VALUE_MAX + 1U)
+#define LPC32XX_IRQ_PRIORITY_HIGHEST LPC32XX_IRQ_PRIORITY_VALUE_MIN
+#define LPC32XX_IRQ_PRIORITY_LOWEST LPC32XX_IRQ_PRIORITY_VALUE_MAX
+
+#define BSP_INTERRUPT_VECTOR_MIN LPC32XX_IRQ_SIC_1_IRQ
+#define BSP_INTERRUPT_VECTOR_MAX LPC32XX_IRQ_SYSCLK
+
+#define LPC32XX_IRQ_COUNT (BSP_INTERRUPT_VECTOR_MAX + 1)
+
+void lpc32xx_irq_set_priority(rtems_vector_number vector, unsigned priority);
+
+unsigned lpc32xx_irq_get_priority(rtems_vector_number vector);
+
+typedef enum {
+  LPC32XX_IRQ_ACTIVE_LOW_OR_FALLING_EDGE,
+  LPC32XX_IRQ_ACTIVE_HIGH_OR_RISING_EDGE
+} lpc32xx_irq_activation_polarity;
+
+void lpc32xx_irq_set_activation_polarity(rtems_vector_number vector, lpc32xx_irq_activation_polarity activation_polarity);
+
+lpc32xx_irq_activation_polarity lpc32xx_irq_get_activation_polarity(rtems_vector_number vector);
+
+typedef enum {
+  LPC32XX_IRQ_LEVEL_SENSITIVE,
+  LPC32XX_IRQ_EDGE_SENSITIVE
+} lpc32xx_irq_activation_type;
+
+void lpc32xx_irq_set_activation_type(rtems_vector_number vector, lpc32xx_irq_activation_type activation_type);
+
+lpc32xx_irq_activation_type lpc32xx_irq_get_activation_type(rtems_vector_number vector);
+
+/** @} */
+
+#endif /* ASM */
+
+#endif /* LIBBSP_ARM_LPC32XX_IRQ_H */
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/lpc-clock-config.h b/c/src/lib/libbsp/arm/lpc32xx/include/lpc-clock-config.h
new file mode 100644
index 0000000000..c4d7906632
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/lpc-clock-config.h
@@ -0,0 +1,45 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx
+ *
+ * @brief Clock driver configuration.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H
+#define LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H
+
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/lpc32xx.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define LPC_CLOCK_INTERRUPT LPC32XX_IRQ_TIMER_0
+
+#define LPC_CLOCK_TIMER_BASE LPC32XX_BASE_TIMER_0
+
+#define LPC_CLOCK_REFERENCE LPC32XX_PERIPH_CLK
+
+#define LPC_CLOCK_MODULE_ENABLE()
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H */
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h b/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h
new file mode 100644
index 0000000000..2e82d34b80
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h
@@ -0,0 +1,94 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx
+ *
+ * @brief Register base addresses.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http:
+ */
+
+#ifndef LIBBSP_ARM_LPC32XX_LPC32XX_H
+#define LIBBSP_ARM_LPC32XX_LPC32XX_H
+
+#define LPC32XX_BASE_ADC 0x40048000
+#define LPC32XX_BASE_SYSCON 0x40004000
+#define LPC32XX_BASE_DEBUG_CTRL 0x40040000
+#define LPC32XX_BASE_DMA 0x31000000
+#define LPC32XX_BASE_EMC 0x31080000
+#define LPC32XX_BASE_EMC_CS_0 0xe0000000
+#define LPC32XX_BASE_EMC_CS_1 0xe1000000
+#define LPC32XX_BASE_EMC_CS_2 0xe2000000
+#define LPC32XX_BASE_EMC_CS_3 0xe3000000
+#define LPC32XX_BASE_EMC_DYCS_0 0x80000000
+#define LPC32XX_BASE_EMC_DYCS_1 0xa0000000
+#define LPC32XX_BASE_ETB_CFG 0x310c0000
+#define LPC32XX_BASE_ETB_DATA 0x310e0000
+#define LPC32XX_BASE_ETHERNET 0x31060000
+#define LPC32XX_BASE_GPIO 0x40028000
+#define LPC32XX_BASE_I2C_1 0x400a0000
+#define LPC32XX_BASE_I2C_2 0x400a8000
+#define LPC32XX_BASE_I2S_0 0x20094000
+#define LPC32XX_BASE_I2S_1 0x2009c000
+#define LPC32XX_BASE_IRAM 0x08000000
+#define LPC32XX_BASE_IROM 0x0c000000
+#define LPC32XX_BASE_KEYSCAN 0x40050000
+#define LPC32XX_BASE_LCD 0x31040000
+#define LPC32XX_BASE_MCPWM 0x400e8000
+#define LPC32XX_BASE_MIC 0x40008000
+#define LPC32XX_BASE_NAND_MLC 0x200a8000
+#define LPC32XX_BASE_NAND_SLC 0x20020000
+#define LPC32XX_BASE_PWM_1 0x4005c000
+#define LPC32XX_BASE_PWM_2 0x4005c004
+#define LPC32XX_BASE_PWM_3 0x4002c000
+#define LPC32XX_BASE_PWM_4 0x40030000
+#define LPC32XX_BASE_RTC 0x40024000
+#define LPC32XX_BASE_RTC_RAM 0x40024080
+#define LPC32XX_BASE_SDCARD 0x20098000
+#define LPC32XX_BASE_SIC_1 0x4000c000
+#define LPC32XX_BASE_SIC_2 0x40010000
+#define LPC32XX_BASE_SPI_1 0x20088000
+#define LPC32XX_BASE_SPI_2 0x20090000
+#define LPC32XX_BASE_SSP_0 0x20084000
+#define LPC32XX_BASE_SSP_1 0x2008c000
+#define LPC32XX_BASE_TIMER_0 0x40044000
+#define LPC32XX_BASE_TIMER_1 0x4004c000
+#define LPC32XX_BASE_TIMER_2 0x40058000
+#define LPC32XX_BASE_TIMER_3 0x40060000
+#define LPC32XX_BASE_TIMER_5 0x4002c000
+#define LPC32XX_BASE_TIMER_6 0x40030000
+#define LPC32XX_BASE_TIMER_HS 0x40038000
+#define LPC32XX_BASE_TIMER_MS 0x40034000
+#define LPC32XX_BASE_UART_1 0x40014000
+#define LPC32XX_BASE_UART_2 0x40018000
+#define LPC32XX_BASE_UART_3 0x40080000
+#define LPC32XX_BASE_UART_4 0x40088000
+#define LPC32XX_BASE_UART_5 0x40090000
+#define LPC32XX_BASE_UART_6 0x40098000
+#define LPC32XX_BASE_UART_7 0x4001c000
+#define LPC32XX_BASE_USB 0x31020000
+#define LPC32XX_BASE_USB_OTG_I2C 0x31020300
+#define LPC32XX_BASE_WDT 0x4003c000
+
+#define LPC32XX_U3CLK (*(volatile uint32_t *) 0x400040d0)
+#define LPC32XX_U4CLK (*(volatile uint32_t *) 0x400040d4)
+#define LPC32XX_U5CLK (*(volatile uint32_t *) 0x400040d8)
+#define LPC32XX_U6CLK (*(volatile uint32_t *) 0x400040dc)
+#define LPC32XX_IRDACLK (*(volatile uint32_t *) 0x400040e0)
+#define LPC32XX_UART_CTRL (*(volatile uint32_t *) 0x40054000)
+#define LPC32XX_UART_CLKMODE (*(volatile uint32_t *) 0x40054004)
+#define LPC32XX_UART_LOOP (*(volatile uint32_t *) 0x40054008)
+#define LPC32XX_SW_INT (*(volatile uint32_t *) 0x400040a8)
+
+#endif /* LIBBSP_ARM_LPC32XX_LPC32XX_H */
diff --git a/c/src/lib/libbsp/arm/lpc32xx/irq/irq.c b/c/src/lib/libbsp/arm/lpc32xx/irq/irq.c
new file mode 100644
index 0000000000..187b4b310b
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/irq/irq.c
@@ -0,0 +1,372 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief Interrupt support.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+#include <bsp/lpc32xx.h>
+
+/*
+ * Mask out SIC 1 and 2 IRQ request. There is no need to mask out the FIQ,
+ * since a pending FIQ would be a fatal error.  The default handler will be
+ * invoked in this case.
+ */
+#define LPC32XX_MIC_STATUS_MASK (~0x3U)
+
+typedef union {
+  struct {
+    uint32_t mic;
+    uint32_t sic_1;
+    uint32_t sic_2;
+  } field;
+  uint32_t fields_table [LPC32XX_IRQ_MODULE_COUNT];
+} lpc32xx_irq_fields;
+
+typedef struct {
+  uint32_t er;
+  uint32_t rsr;
+  uint32_t sr;
+  uint32_t apr;
+  uint32_t atr;
+  uint32_t itr;
+} lpc32xx_irq_controller;
+
+static volatile lpc32xx_irq_controller *const lpc32xx_mic = (volatile lpc32xx_irq_controller *) LPC32XX_BASE_MIC;
+
+static volatile lpc32xx_irq_controller *const lpc32xx_sic_1 = (volatile lpc32xx_irq_controller *) LPC32XX_BASE_SIC_1;
+
+static volatile lpc32xx_irq_controller *const lpc32xx_sic_2 = (volatile lpc32xx_irq_controller *) LPC32XX_BASE_SIC_2;
+
+static uint8_t lpc32xx_irq_priority_table [LPC32XX_IRQ_COUNT];
+
+static lpc32xx_irq_fields lpc32xx_irq_priority_masks [LPC32XX_IRQ_PRIORITY_COUNT];
+
+static lpc32xx_irq_fields lpc32xx_irq_enable;
+
+static inline bool lpc32xx_irq_is_valid(rtems_vector_number vector)
+{
+  return vector <= BSP_INTERRUPT_VECTOR_MAX;
+}
+
+static inline bool lpc32xx_irq_priority_is_valid(unsigned priority)
+{
+  return priority <= LPC32XX_IRQ_PRIORITY_LOWEST;
+}
+
+#define LPC32XX_IRQ_BIT_OPS_DEFINE \
+  unsigned bit = index & 0x1fU; \
+  unsigned module = index >> 5
+
+#define LPC32XX_IRQ_BIT_OPS_FOR_REG_DEFINE \
+  LPC32XX_IRQ_BIT_OPS_DEFINE; \
+  unsigned module_offset = module << 14; \
+  volatile uint32_t *reg =  \
+    (volatile uint32_t *) (LPC32XX_BASE_MIC + module_offset + register_offset)
+
+#define LPC32XX_IRQ_OFFSET_ER 0U
+#define LPC32XX_IRQ_OFFSET_RSR 4U
+#define LPC32XX_IRQ_OFFSET_SR 8U
+#define LPC32XX_IRQ_OFFSET_APR 12U
+#define LPC32XX_IRQ_OFFSET_ATR 16U
+#define LPC32XX_IRQ_OFFSET_ITR 20U
+
+static inline bool lpc32xx_irq_is_bit_set_in_register(unsigned index, unsigned register_offset)
+{
+  LPC32XX_IRQ_BIT_OPS_FOR_REG_DEFINE;
+
+  return *reg & (1U << bit);
+}
+
+static inline void lpc32xx_irq_set_bit_in_register(unsigned index, unsigned register_offset)
+{
+  LPC32XX_IRQ_BIT_OPS_FOR_REG_DEFINE;
+
+  *reg |= 1U << bit;
+}
+
+static inline void lpc32xx_irq_clear_bit_in_register(unsigned index, unsigned register_offset)
+{
+  LPC32XX_IRQ_BIT_OPS_FOR_REG_DEFINE;
+
+  *reg &= ~(1U << bit);
+}
+
+static inline void lpc32xx_irq_set_bit_in_field(unsigned index, lpc32xx_irq_fields *fields)
+{
+  LPC32XX_IRQ_BIT_OPS_DEFINE;
+
+  fields->fields_table [module] |= 1U << bit;
+}
+
+static inline void lpc32xx_irq_clear_bit_in_field(unsigned index, lpc32xx_irq_fields *fields)
+{
+  LPC32XX_IRQ_BIT_OPS_DEFINE;
+
+  fields->fields_table [module] &= ~bit;
+}
+
+static inline unsigned lpc32xx_irq_get_index(uint32_t val)
+{
+  uint32_t reg;
+
+  asm volatile (
+    THUMB_TO_ARM
+    "clz %1, %1\n"
+    "rsb %1, %1, #31\n"
+    ARM_TO_THUMB
+    : "=&r" (reg), "=r" (val)
+    : "1" (val)
+  );
+
+  return val;
+}
+
+void lpc32xx_irq_set_priority(rtems_vector_number vector, unsigned priority)
+{
+  if (lpc32xx_irq_is_valid(vector)) {
+    rtems_interrupt_level level;
+    unsigned i = 0;
+
+    if (priority > LPC32XX_IRQ_PRIORITY_LOWEST) {
+      priority = LPC32XX_IRQ_PRIORITY_LOWEST;
+    }
+
+    lpc32xx_irq_priority_table [vector] = (uint8_t) priority;
+
+    for (i = LPC32XX_IRQ_PRIORITY_HIGHEST; i <= priority; ++i) {
+      rtems_interrupt_disable(level);
+      lpc32xx_irq_clear_bit_in_field(vector, &lpc32xx_irq_priority_masks [i]);
+      rtems_interrupt_enable(level);
+    }
+
+    for (i = priority + 1; i <= LPC32XX_IRQ_PRIORITY_LOWEST; ++i) {
+      rtems_interrupt_disable(level);
+      lpc32xx_irq_set_bit_in_field(vector, &lpc32xx_irq_priority_masks [i]);
+      rtems_interrupt_enable(level);
+    }
+  }
+}
+
+unsigned lpc32xx_irq_get_priority(rtems_vector_number vector)
+{
+  if (lpc32xx_irq_is_valid(vector)) {
+    return lpc32xx_irq_priority_table [vector];
+  } else {
+    return LPC32XX_IRQ_PRIORITY_LOWEST;
+  }
+}
+
+void lpc32xx_irq_set_activation_polarity(rtems_vector_number vector, lpc32xx_irq_activation_polarity activation_polarity)
+{
+  if (lpc32xx_irq_is_valid(vector)) {
+    rtems_interrupt_level level;
+
+    rtems_interrupt_disable(level);
+    if (activation_polarity == LPC32XX_IRQ_ACTIVE_HIGH_OR_RISING_EDGE) {
+      lpc32xx_irq_set_bit_in_register(vector, LPC32XX_IRQ_OFFSET_APR);
+    } else {
+      lpc32xx_irq_clear_bit_in_register(vector, LPC32XX_IRQ_OFFSET_APR);
+    }
+    rtems_interrupt_enable(level);
+  }
+}
+
+lpc32xx_irq_activation_polarity lpc32xx_irq_get_activation_polarity(rtems_vector_number vector)
+{
+  if (lpc32xx_irq_is_valid(vector)) {
+    if (lpc32xx_irq_is_bit_set_in_register(vector, LPC32XX_IRQ_OFFSET_APR)) {
+      return LPC32XX_IRQ_ACTIVE_HIGH_OR_RISING_EDGE;
+    } else {
+      return LPC32XX_IRQ_ACTIVE_LOW_OR_FALLING_EDGE;
+    }
+  } else {
+    return LPC32XX_IRQ_ACTIVE_LOW_OR_FALLING_EDGE;
+  }
+}
+
+void lpc32xx_irq_set_activation_type(rtems_vector_number vector, lpc32xx_irq_activation_type activation_type)
+{
+  if (lpc32xx_irq_is_valid(vector)) {
+    rtems_interrupt_level level;
+
+    rtems_interrupt_disable(level);
+    if (activation_type == LPC32XX_IRQ_EDGE_SENSITIVE) {
+      lpc32xx_irq_set_bit_in_register(vector, LPC32XX_IRQ_OFFSET_ATR);
+    } else {
+      lpc32xx_irq_clear_bit_in_register(vector, LPC32XX_IRQ_OFFSET_ATR);
+    }
+    rtems_interrupt_enable(level);
+  }
+}
+
+lpc32xx_irq_activation_type lpc32xx_irq_get_activation_type(rtems_vector_number vector)
+{
+  if (lpc32xx_irq_is_valid(vector)) {
+    if (lpc32xx_irq_is_bit_set_in_register(vector, LPC32XX_IRQ_OFFSET_ATR)) {
+      return LPC32XX_IRQ_EDGE_SENSITIVE;
+    } else {
+      return LPC32XX_IRQ_LEVEL_SENSITIVE;
+    }
+  } else {
+    return LPC32XX_IRQ_LEVEL_SENSITIVE;
+  }
+}
+
+void bsp_interrupt_dispatch(void)
+{
+  uint32_t status = lpc32xx_mic->sr & LPC32XX_MIC_STATUS_MASK;
+  uint32_t er_mic = lpc32xx_mic->er;
+  uint32_t er_sic_1 = lpc32xx_sic_1->er;
+  uint32_t er_sic_2 = lpc32xx_sic_2->er;
+  uint32_t psr = 0;
+  lpc32xx_irq_fields *masks = NULL;
+  rtems_vector_number vector = 0;
+  unsigned priority = 0;
+
+  if (status != 0) {
+    vector = lpc32xx_irq_get_index(status);
+  } else {
+    status = lpc32xx_sic_1->sr;
+    if (status != 0) {
+      vector = lpc32xx_irq_get_index(status) + LPC32XX_IRQ_MODULE_SIC_1;
+    } else {
+      status = lpc32xx_sic_2->sr;
+      if (status != 0) {
+        vector = lpc32xx_irq_get_index(status) + LPC32XX_IRQ_MODULE_SIC_2;
+      } else {
+        return;
+      }
+    }
+  }
+
+  priority = lpc32xx_irq_priority_table [vector];
+
+  masks = &lpc32xx_irq_priority_masks [priority];
+
+  lpc32xx_mic->er = er_mic & masks->field.mic;
+  lpc32xx_sic_1->er = er_sic_1 & masks->field.sic_1;
+  lpc32xx_sic_2->er = er_sic_2 & masks->field.sic_2;
+
+  psr = arm_status_irq_enable();
+
+  bsp_interrupt_handler_dispatch(vector);
+
+  arm_status_restore(psr);
+
+  lpc32xx_mic->er = er_mic & lpc32xx_irq_enable.field.mic;
+  lpc32xx_sic_1->er = er_sic_1 & lpc32xx_irq_enable.field.sic_1;
+  lpc32xx_sic_2->er = er_sic_2 & lpc32xx_irq_enable.field.sic_2;
+}
+
+rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
+{
+  if (lpc32xx_irq_is_valid(vector)) {
+    rtems_interrupt_level level;
+
+    rtems_interrupt_disable(level);
+    lpc32xx_irq_set_bit_in_register(vector, LPC32XX_IRQ_OFFSET_ER);
+    lpc32xx_irq_set_bit_in_field(vector, &lpc32xx_irq_enable);
+    rtems_interrupt_enable(level);
+  }
+
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
+{
+  if (lpc32xx_irq_is_valid(vector)) {
+    rtems_interrupt_level level;
+
+    rtems_interrupt_disable(level);
+    lpc32xx_irq_clear_bit_in_field(vector, &lpc32xx_irq_enable);
+    lpc32xx_irq_clear_bit_in_register(vector, LPC32XX_IRQ_OFFSET_ER);
+    rtems_interrupt_enable(level);
+  }
+
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code bsp_interrupt_facility_initialize(void)
+{
+  size_t i = 0;
+
+  /* Set default priority */
+  for (i = 0; i < LPC32XX_IRQ_COUNT; ++i) {
+    lpc32xx_irq_priority_table [i] = LPC32XX_IRQ_PRIORITY_LOWEST;
+  }
+
+  /* Enable SIC 1 and 2 at all priorities */
+  for (i = 0; i < LPC32XX_IRQ_PRIORITY_COUNT; ++i) {
+    lpc32xx_irq_priority_masks [i].field.mic = 0xc0000003;
+  }
+
+  /* Disable all interrupts except SIC 1 and 2 */
+  lpc32xx_irq_enable.field.sic_2 = 0x0;
+  lpc32xx_irq_enable.field.sic_1 = 0x0;
+  lpc32xx_irq_enable.field.mic = 0xc0000003;
+  lpc32xx_sic_1->er = 0x0;
+  lpc32xx_sic_2->er = 0x0;
+  lpc32xx_mic->er = 0xc0000003;
+
+  /* Set interrupt types to IRQ */
+  lpc32xx_mic->itr = 0x0;
+  lpc32xx_sic_1->itr = 0x0;
+  lpc32xx_sic_2->itr = 0x0;
+
+  /* Set interrupt activation polarities */
+  lpc32xx_mic->apr = 0x3ff0efe0;
+  lpc32xx_sic_1->apr = 0xfbd27184;
+  lpc32xx_sic_2->apr = 0x801810c0;
+
+  /* Set interrupt activation types */
+  lpc32xx_mic->atr = 0x0;
+  lpc32xx_sic_1->atr = 0x26000;
+  lpc32xx_sic_2->atr = 0x0;
+
+  _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
+
+  return RTEMS_SUCCESSFUL;
+}
+
+void bsp_interrupt_handler_default(rtems_vector_number vector)
+{
+  printk("spurious interrupt: %u\n", vector);
+}
+
+static void lpc32xx_irq_dump_controller(volatile lpc32xx_irq_controller *controller)
+{
+  printk(
+    "er  %08x\nrsr %08x\nsr  %08x\napr %08x\natr %08x\nitr %08x\n",
+    controller->er,
+    controller->rsr,
+    controller->sr,
+    controller->apr,
+    controller->atr,
+    controller->itr
+  );
+}
+
+void lpc32xx_irq_dump(void)
+{
+  lpc32xx_irq_dump_controller(lpc32xx_mic);
+  lpc32xx_irq_dump_controller(lpc32xx_sic_1);
+  lpc32xx_irq_dump_controller(lpc32xx_sic_2);
+}
diff --git a/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_phycore.cfg b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_phycore.cfg
new file mode 100644
index 0000000000..3dbb643ba1
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_phycore.cfg
@@ -0,0 +1,14 @@
+#
+#  Config file for Phycore LPC3250 board.
+#
+#  $Id$
+#
+
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU = arm
+
+CPU_CFLAGS = -mcpu=arm926ej-s -mthumb -mstructure-size-boundary=8 \
+	-Wextra -Wno-unused -Wpointer-arith -Wcast-qual -Wconversion -Wmissing-prototypes
+
+CFLAGS_OPTIMIZE_V = -Os -g
diff --git a/c/src/lib/libbsp/arm/lpc32xx/misc/timer.c b/c/src/lib/libbsp/arm/lpc32xx/misc/timer.c
new file mode 100644
index 0000000000..5c0246133c
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/misc/timer.c
@@ -0,0 +1,55 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx
+ *
+ * @brief Benchmark timer support.
+ */
+
+/*
+ * Copyright (c) 2008, 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <rtems/timerdrv.h>
+
+static bool benchmark_timer_find_average_overhead = false;
+
+static uint32_t benchmark_timer_base;
+
+/* TODO */
+static uint32_t lpc32xx_timer(void)
+{
+  return 0;
+}
+
+void benchmark_timer_initialize(void)
+{
+  benchmark_timer_base = lpc32xx_timer();
+}
+
+uint32_t benchmark_timer_read(void)
+{
+  uint32_t delta = lpc32xx_timer() - benchmark_timer_base;
+
+  if (benchmark_timer_find_average_overhead) {
+    return delta;
+  } else {
+    /* TODO */
+    return 0;
+  }
+}
+
+void benchmark_timer_disable_subtracting_average_overhead(bool find_average_overhead)
+{
+  benchmark_timer_find_average_overhead = find_average_overhead;
+}
diff --git a/c/src/lib/libbsp/arm/lpc32xx/preinstall.am b/c/src/lib/libbsp/arm/lpc32xx/preinstall.am
new file mode 100644
index 0000000000..3f2aa0c774
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/preinstall.am
@@ -0,0 +1,119 @@
+## Automatically generated by ampolish3 - Do not edit
+
+if AMPOLISH3
+$(srcdir)/preinstall.am: Makefile.am
+	$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
+endif
+
+PREINSTALL_DIRS =
+DISTCLEANFILES += $(PREINSTALL_DIRS)
+
+all-local: $(TMPINSTALL_FILES)
+
+TMPINSTALL_FILES =
+CLEANFILES = $(TMPINSTALL_FILES)
+
+all-am: $(PREINSTALL_FILES)
+
+PREINSTALL_FILES =
+CLEANFILES += $(PREINSTALL_FILES)
+
+$(PROJECT_LIB)/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_LIB)
+	@: > $(PROJECT_LIB)/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
+
+$(PROJECT_INCLUDE)/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)
+	@: > $(PROJECT_INCLUDE)/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
+
+$(PROJECT_INCLUDE)/bsp/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
+	@: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+
+$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
+PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
+
+$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
+
+$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
+
+$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
+
+$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h
+
+$(PROJECT_INCLUDE)/bsp/utility.h: ../../shared/include/utility.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/utility.h
+
+$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
+
+$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
+
+$(PROJECT_INCLUDE)/bsp/stackalloc.h: ../../shared/include/stackalloc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stackalloc.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stackalloc.h
+
+$(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tod.h
+
+$(PROJECT_INCLUDE)/bsp/linker-symbols.h: ../shared/include/linker-symbols.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/linker-symbols.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/linker-symbols.h
+
+$(PROJECT_INCLUDE)/bsp/start.h: ../shared/include/start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/start.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/start.h
+
+$(PROJECT_INCLUDE)/bsp/lpc-timer.h: ../shared/lpc/include/lpc-timer.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc-timer.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc-timer.h
+
+$(PROJECT_INCLUDE)/bsp/irq-config.h: include/irq-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-config.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-config.h
+
+$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
+
+$(PROJECT_INCLUDE)/bsp/lpc32xx.h: include/lpc32xx.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc32xx.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc32xx.h
+
+$(PROJECT_INCLUDE)/bsp/lpc-clock-config.h: include/lpc-clock-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc-clock-config.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc-clock-config.h
+
+$(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
+
+$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
+TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
+
+$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
+TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds
+
+$(PROJECT_LIB)/linkcmds.base: ../shared/startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base
+TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base
+
diff --git a/c/src/lib/libbsp/arm/lpc32xx/rtc/rtc-config.c b/c/src/lib/libbsp/arm/lpc32xx/rtc/rtc-config.c
new file mode 100644
index 0000000000..35a2c75be9
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/rtc/rtc-config.c
@@ -0,0 +1,93 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx
+ *
+ * @brief RTC configuration.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <libchip/rtc.h>
+
+#include <bsp/lpc32xx.h>
+
+#define LPC32XX_RTC_COUNT 1
+
+static void lpc32xx_rtc_initialize(int minor)
+{
+  /* TODO */
+}
+
+static int lpc32xx_rtc_get_time(int minor, rtems_time_of_day *tod)
+{
+  /* TODO */
+
+#if 0
+  tod->ticks = 0;
+  tod->second = RTC_SEC;
+  tod->minute = RTC_MIN;
+  tod->hour = RTC_HOUR;
+  tod->day = RTC_DOM;
+  tod->month = RTC_MONTH;
+  tod->year = RTC_YEAR;
+#endif
+
+  return 0;
+}
+
+static int lpc32xx_rtc_set_time(int minor, const rtems_time_of_day *tod)
+{
+  /* TODO */
+
+#if 0
+  RTC_SEC = tod->second;
+  RTC_MIN = tod->minute;
+  RTC_HOUR = tod->hour;
+  RTC_DOM = tod->day;
+  RTC_MONTH = tod->month;
+  RTC_YEAR = tod->year;
+#endif
+
+  return 0;
+}
+
+static bool lpc32xx_rtc_probe(int minor)
+{
+  return true;
+}
+
+const rtc_fns lpc32xx_rtc_ops = {
+  .deviceInitialize = lpc32xx_rtc_initialize,
+  .deviceGetTime = lpc32xx_rtc_get_time,
+  .deviceSetTime = lpc32xx_rtc_set_time
+};
+
+unsigned long RTC_Count = LPC32XX_RTC_COUNT;
+
+rtems_device_minor_number RTC_Minor = 0;
+
+rtc_tbl	RTC_Table [LPC32XX_RTC_COUNT] = {
+  {
+    .sDeviceName = "/dev/rtc",
+    .deviceType = RTC_CUSTOM,
+    .pDeviceFns = &lpc32xx_rtc_ops,
+    .deviceProbe = lpc32xx_rtc_probe,
+    .pDeviceParams = NULL,
+    .ulCtrlPort1 = 0,
+    .ulDataPort = 0,
+    .getRegister = NULL,
+    .setRegister = NULL
+  }
+};
diff --git a/c/src/lib/libbsp/arm/lpc32xx/startup/bspreset.c b/c/src/lib/libbsp/arm/lpc32xx/startup/bspreset.c
new file mode 100644
index 0000000000..76534449fd
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/startup/bspreset.c
@@ -0,0 +1,31 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx
+ *
+ * @brief Reset code.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <rtems.h>
+
+#include <bsp/bootcard.h>
+
+void bsp_reset( void)
+{
+  while (true) {
+    /* Do nothing */
+  }
+}
diff --git a/c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c
new file mode 100644
index 0000000000..02247bb96c
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c
@@ -0,0 +1,123 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx
+ *
+ * @brief Startup code.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <bsp/irq-generic.h>
+#include <bsp/irq.h>
+#include <bsp/linker-symbols.h>
+#include <bsp/stackalloc.h>
+#include <bsp/lpc32xx.h>
+
+/* FIXME */
+#define CONSOLE_RBR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x00))
+#define CONSOLE_THR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x00))
+#define CONSOLE_DLL (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x00))
+#define CONSOLE_DLM (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x04))
+#define CONSOLE_IER (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x04))
+#define CONSOLE_IIR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x08))
+#define CONSOLE_FCR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x08))
+#define CONSOLE_LCR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x0C))
+#define CONSOLE_LSR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x14))
+#define CONSOLE_SCR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x1C))
+#define CONSOLE_ACR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x20))
+#define CONSOLE_ICR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x24))
+#define CONSOLE_FDR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x28))
+#define CONSOLE_TER (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x30))
+
+void bsp_start(void)
+{
+  #ifdef LPC32XX_CONFIG_U3CLK
+    LPC32XX_U3CLK = LPC32XX_CONFIG_U3CLK;
+  #endif
+  #ifdef LPC32XX_CONFIG_U4CLK
+    LPC32XX_U4CLK = LPC32XX_CONFIG_U4CLK;
+  #endif
+  #ifdef LPC32XX_CONFIG_U5CLK
+    LPC32XX_U5CLK = LPC32XX_CONFIG_U5CLK;
+  #endif
+  #ifdef LPC32XX_CONFIG_U6CLK
+    LPC32XX_U6CLK = LPC32XX_CONFIG_U6CLK;
+  #endif
+
+  #ifdef LPC32XX_CONFIG_UART_CLKMODE
+    LPC32XX_UART_CLKMODE = LPC32XX_CONFIG_UART_CLKMODE;
+  #endif
+
+  LPC32XX_UART_CTRL = 0x0;
+  LPC32XX_UART_LOOP = 0x0;
+
+  /* FIXME */
+  CONSOLE_LCR = 0x0;
+  CONSOLE_IER = 0x0;
+  CONSOLE_LCR = 0x80;
+  CONSOLE_DLL = 0x1; /* Clock is already set in LPC32XX_U5CLK */
+  CONSOLE_DLM = 0x0;
+  CONSOLE_LCR = 0x3;
+  CONSOLE_FCR = 0x7;
+
+#if 0
+  /* FIXME */
+  printk("LPC32XX_U3CLK %08x\n", LPC32XX_U3CLK);
+  printk("LPC32XX_U4CLK %08x\n", LPC32XX_U4CLK);
+  printk("LPC32XX_U5CLK %08x\n", LPC32XX_U5CLK);
+  printk("LPC32XX_U6CLK %08x\n", LPC32XX_U6CLK);
+  printk("LPC32XX_IRDACLK %08x\n", LPC32XX_IRDACLK);
+  printk("LPC32XX_UART_CTRL %08x\n", LPC32XX_UART_CTRL);
+  printk("LPC32XX_UART_CLKMODE %08x\n", LPC32XX_UART_CLKMODE);
+  printk("LPC32XX_UART_LOOP %08x\n", LPC32XX_UART_LOOP);
+#endif
+
+  /* Interrupts */
+  if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
+    _CPU_Fatal_halt(0xe);
+  }
+
+  /* Task stacks */
+  bsp_stack_initialize(
+    bsp_section_stack_begin,
+    (uintptr_t) bsp_section_stack_size
+  );
+}
+
+#define UART_LSR_THRE 0x00000020U
+
+static void lpc32xx_console_wait(void)
+{
+  while ((CONSOLE_LSR & UART_LSR_THRE) == 0) {
+    /* Wait */
+  }
+}
+
+static void lpc32xx_BSP_output_char(char c)
+{
+  lpc32xx_console_wait();
+
+  CONSOLE_THR = c;
+
+  if (c == '\n') {
+    lpc32xx_console_wait();
+
+    CONSOLE_THR = '\r';
+  }
+}
+
+BSP_output_char_function_type BSP_output_char = lpc32xx_BSP_output_char;
diff --git a/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c
new file mode 100644
index 0000000000..7f668f83c5
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c
@@ -0,0 +1,84 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx
+ *
+ * @brief Startup code.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <stdbool.h>
+
+#include <bspopts.h>
+#include <bsp/start.h>
+#include <bsp/lpc32xx.h>
+#include <bsp/linker-symbols.h>
+
+#define BSP_START_SECTION __attribute__((section(".bsp_start")))
+
+static void BSP_START_SECTION lpc32xx_clear_bss(void)
+{
+  const int *end = (const int *) bsp_section_bss_end;
+  int *out = (int *) bsp_section_bss_begin;
+
+  /* Clear BSS */
+  while (out != end) {
+    *out = 0;
+    ++out;
+  }
+}
+
+void BSP_START_SECTION bsp_start_hook_0(void)
+{
+  /* TODO */
+}
+
+void BSP_START_SECTION bsp_start_hook_1(void)
+{
+  /* TODO */
+
+  /* Copy .text section */
+  bsp_start_memcpy_arm(
+    (int *) bsp_section_text_begin,
+    (const int *) bsp_section_text_load_begin,
+    (size_t) bsp_section_text_size
+  );
+
+  /* Copy .rodata section */
+  bsp_start_memcpy_arm(
+    (int *) bsp_section_rodata_begin,
+    (const int *) bsp_section_rodata_load_begin,
+    (size_t) bsp_section_rodata_size
+  );
+
+  /* Copy .data section */
+  bsp_start_memcpy_arm(
+    (int *) bsp_section_data_begin,
+    (const int *) bsp_section_data_load_begin,
+    (size_t) bsp_section_data_size
+  );
+
+  /* Copy .fast section */
+  bsp_start_memcpy_arm(
+    (int *) bsp_section_fast_begin,
+    (const int *) bsp_section_fast_load_begin,
+    (size_t) bsp_section_fast_size
+  );
+
+  /* Clear .bss section */
+  lpc32xx_clear_bss();
+
+  /* At this point we can use objects outside the .start section */
+}
diff --git a/c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_phycore b/c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_phycore
new file mode 100644
index 0000000000..8003ecc996
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_phycore
@@ -0,0 +1,60 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx_linker_phycore
+ *
+ * @brief Memory map.
+ */
+
+/**
+ * @defgroup lpc32xx_linker_phycore phyCORE-LPC3250 Memory Map
+ *
+ * @ingroup bsp_linker
+ *
+ * @brief phyCORE-LPC3250 memory map.
+ *
+ * <table>
+ *   <tr><th>Region Name</th><th>Region Begin</th><th>Region Size</th></tr>
+ *   <tr><td>RAM_INT</td><td>0x08000000</td><td>256k</td></tr>
+ *   <tr><td>RAM_EXT</td><td>0x80000000</td><td>64M</td></tr>
+ *   <tr><td>ROM_EXT</td><td>0xe0000000</td><td>2M</td></tr>
+ * </table>
+ *
+ * <table>
+ *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
+ *   <tr><td>.start</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.vector</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.text</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.rodata</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.data</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.fast</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.bss</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.work</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.stack</td><td>RAM_INT</td><td></td></tr>
+ * </table>
+ */
+
+MEMORY {
+        RAM_INT (AIW) : ORIGIN = 0x08000000, LENGTH = 256k
+        RAM_EXT (AIW) : ORIGIN = 0x80000000, LENGTH = 64M /* SDRAM on DYCS0 */
+        ROM_EXT (RX) : ORIGIN = 0xe0000000, LENGTH = 2M /* NOR flash on CS0 */
+        NIRVANA : ORIGIN = 0, LENGTH = 0
+}
+
+REGION_ALIAS ("REGION_START", RAM_EXT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", RAM_EXT);
+REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_BSS", RAM_EXT);
+REGION_ALIAS ("REGION_WORK", RAM_EXT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+
+bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096;
+
+INCLUDE linkcmds.base
diff --git a/c/src/lib/libbsp/arm/shared/include/linker-symbols.h b/c/src/lib/libbsp/arm/shared/include/linker-symbols.h
index 817a97ec29..75f7d942e0 100644
--- a/c/src/lib/libbsp/arm/shared/include/linker-symbols.h
+++ b/c/src/lib/libbsp/arm/shared/include/linker-symbols.h
@@ -22,6 +22,10 @@
 #ifndef LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H
 #define LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H
 
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
 /**
  * @defgroup bsp_linker Linker Support
  *
@@ -100,4 +104,8 @@ LINKER_SYMBOL(bsp_section_stack_size)
 
 /** @} */
 
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
 #endif /* LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H */
diff --git a/c/src/lib/libbsp/arm/shared/lpc/clock/lpc-clock-config.c b/c/src/lib/libbsp/arm/shared/lpc/clock/lpc-clock-config.c
new file mode 100644
index 0000000000..7dbb6c4b32
--- /dev/null
+++ b/c/src/lib/libbsp/arm/shared/lpc/clock/lpc-clock-config.c
@@ -0,0 +1,121 @@
+/**
+ * @file
+ *
+ * @ingroup lpc
+ *
+ * @brief Clock driver configuration.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp/lpc-clock-config.h>
+#include <bsp/lpc-timer.h>
+
+/* This is defined in ../../../shared/clockdrv_shell.h */
+rtems_isr Clock_isr(rtems_vector_number vector);
+
+static volatile lpc_timer *const lpc_clock = 
+  (volatile lpc_timer *) LPC_CLOCK_TIMER_BASE;
+
+static void lpc_clock_at_tick(void)
+{
+  lpc_clock->ir = LPC_TIMER_IR_MR0;
+}
+
+static void lpc_clock_handler_install(void)
+{
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+  sc = rtems_interrupt_handler_install(
+    LPC_CLOCK_INTERRUPT,
+    "Clock",
+    RTEMS_INTERRUPT_UNIQUE,
+    (rtems_interrupt_handler) Clock_isr,
+    NULL
+  );
+  if (sc != RTEMS_SUCCESSFUL) {
+    rtems_fatal_error_occurred(0xdeadbeef);
+  }
+}
+
+static void lpc_clock_initialize(void)
+{
+  uint64_t interval = ((uint64_t) LPC_CLOCK_REFERENCE
+    * (uint64_t) rtems_configuration_get_microseconds_per_tick()) / 1000000;
+
+  /* Enable module */
+  LPC_CLOCK_MODULE_ENABLE();
+
+  /* Reset timer */
+  lpc_clock->tcr = LPC_TIMER_TCR_RST;
+
+  /* Clear interrupt flags */
+  lpc_clock->ir = LPC_TIMER_IR_ALL;
+
+  /* Set timer mode */
+  lpc_clock->ccr = 0;
+
+  /* Timer is incremented every PERIPH_CLK tick */
+  lpc_clock->pr = 0;
+
+  /* Set match registers */
+  lpc_clock->mr0 = (uint32_t) interval;
+
+  /* Generate interrupt and reset counter on match with MR0 */
+  lpc_clock->mcr = LPC_TIMER_MCR_MR0_INTR | LPC_TIMER_MCR_MR0_RST;
+
+  /* No external match */
+  lpc_clock->emr = 0x0;
+
+  /* Enable timer */
+  lpc_clock->tcr = LPC_TIMER_TCR_EN;
+}
+
+static void lpc_clock_cleanup(void)
+{
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+  /* Disable timer */
+  lpc_clock->tcr = 0x0;
+
+  /* Remove interrupt handler */
+  sc = rtems_interrupt_handler_remove(
+    LPC_CLOCK_INTERRUPT,
+    (rtems_interrupt_handler) Clock_isr,
+    NULL
+  );
+  if (sc != RTEMS_SUCCESSFUL) {
+    rtems_fatal_error_occurred(0xdeadbeef);
+  }
+}
+
+static uint32_t lpc_clock_nanoseconds_since_last_tick(void)
+{
+  uint64_t clock = LPC_CLOCK_REFERENCE;
+  uint64_t clicks = lpc_clock->tc;
+  uint64_t ns = (clicks * 1000000000) / clock;
+
+  return (uint32_t) ns;
+}
+
+#define Clock_driver_support_at_tick() lpc_clock_at_tick()
+#define Clock_driver_support_initialize_hardware() lpc_clock_initialize()
+#define Clock_driver_support_install_isr(isr, old_isr) \
+  lpc_clock_handler_install()
+#define Clock_driver_support_shutdown_hardware() lpc_clock_cleanup()
+#define Clock_driver_nanoseconds_since_last_tick \
+  lpc_clock_nanoseconds_since_last_tick
+
+/* Include shared source clock driver code */
+#include "../../../../shared/clockdrv_shell.h"
diff --git a/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h b/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h
new file mode 100644
index 0000000000..2adf0bec19
--- /dev/null
+++ b/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h
@@ -0,0 +1,103 @@
+/**
+ * @file
+ *
+ * @ingroup lpc
+ *
+ * @brief Timer API.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_LPC_TIMER_H
+#define LIBBSP_ARM_SHARED_LPC_TIMER_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LPC_TIMER_IR_MR0 0x1U
+#define LPC_TIMER_IR_MR1 0x2U
+#define LPC_TIMER_IR_MR2 0x4U
+#define LPC_TIMER_IR_MR3 0x8U
+#define LPC_TIMER_IR_CR0 0x10U
+#define LPC_TIMER_IR_CR1 0x20U
+#define LPC_TIMER_IR_CR2 0x40U
+#define LPC_TIMER_IR_CR3 0x80U
+#define LPC_TIMER_IR_ALL 0xffU
+
+#define LPC_TIMER_TCR_EN 0x1U
+#define LPC_TIMER_TCR_RST 0x2U
+
+#define LPC_TIMER_MCR_MR0_INTR 0x1U
+#define LPC_TIMER_MCR_MR0_RST 0x2U
+#define LPC_TIMER_MCR_MR0_STOP 0x4U
+#define LPC_TIMER_MCR_MR1_INTR 0x8U
+#define LPC_TIMER_MCR_MR1_RST 0x10U
+#define LPC_TIMER_MCR_MR1_STOP 0x20U
+#define LPC_TIMER_MCR_MR2_INTR 0x40U
+#define LPC_TIMER_MCR_MR2_RST 0x80U
+#define LPC_TIMER_MCR_MR2_STOP 0x100U
+#define LPC_TIMER_MCR_MR3_INTR 0x200U
+#define LPC_TIMER_MCR_MR3_RST 0x400U
+#define LPC_TIMER_MCR_MR3_STOP 0x800U
+
+#define LPC_TIMER_CCR_CAP0_RE 0x1U
+#define LPC_TIMER_CCR_CAP0_FE 0x2U
+#define LPC_TIMER_CCR_CAP0_INTR 0x4U
+#define LPC_TIMER_CCR_CAP1_RE 0x8U
+#define LPC_TIMER_CCR_CAP1_FE 0x10U
+#define LPC_TIMER_CCR_CAP1_INTR 0x20U
+#define LPC_TIMER_CCR_CAP2_RE 0x40U
+#define LPC_TIMER_CCR_CAP2_FE 0x80U
+#define LPC_TIMER_CCR_CAP2_INTR 0x100U
+#define LPC_TIMER_CCR_CAP3_RE 0x200U
+#define LPC_TIMER_CCR_CAP3_FE 0x400U
+#define LPC_TIMER_CCR_CAP3_INTR 0x800U
+
+#define LPC_TIMER_EMR_EM0_RE 0x1U
+#define LPC_TIMER_EMR_EM1_FE 0x2U
+#define LPC_TIMER_EMR_EM2_INTR 0x4U
+#define LPC_TIMER_EMR_EM3_RE 0x8U
+#define LPC_TIMER_EMR_EMC0_FE 0x10U
+#define LPC_TIMER_EMR_EMC1_INTR 0x20U
+#define LPC_TIMER_EMR_EMC2_RE 0x40U
+#define LPC_TIMER_EMR_EMC3_FE 0x80U
+
+typedef struct {
+  uint32_t ir;
+  uint32_t tcr;
+  uint32_t tc;
+  uint32_t pr;
+  uint32_t pc;
+  uint32_t mcr;
+  uint32_t mr0;
+  uint32_t mr1;
+  uint32_t mr2;
+  uint32_t mr3;
+  uint32_t ccr;
+  uint32_t cr0;
+  uint32_t cr1;
+  uint32_t cr2;
+  uint32_t cr3;
+  uint32_t emr;
+  uint32_t ctcr;
+} lpc_timer;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_LPC_TIMER_H */