This is a large patch from Eric Valette <valette@crf.canon.fr> that was

described in the message following this paragraph.  This patch also includes
a mcp750 BSP.

From valette@crf.canon.fr Mon Jun 14 10:03:08 1999
Date: Tue, 18 May 1999 01:30:14 +0200 (CEST)
From: VALETTE Eric <valette@crf.canon.fr>
To: joel@oarcorp.com
Cc: raguet@crf.canon.fr, rtems-snapshots@oarcorp.com, valette@crf.canon.fr
Subject: Questions/Suggestion regarding RTEMS PowerPC code (long)


Dear knowledgeable RTEMS powerpc users,

As some of you may know, I'm currently finalizing a port
of RTEMS on a MCP750 Motorola board. I have done most
of it but have some questions to ask before submitting
the port.

In order to understand some of the changes I have made
or would like to make, maybe it is worth describing the
MCP750 Motorola board.

the MCP750 is a COMPACT PCI powerpc board with :

	1) a MPC750 233 MHz processor,
	2) a raven bus bridge/PCI controller that
	implement an OPENPIC compliant interrupt controller,
	3) a VIA 82C586 PCI/ISA bridge that offers a PC
	compliant IO for keyboard, serial line, IDE, and
	the well known PC 8259 cascaded PIC interrupt
	architecture model,
	4) a DEC 21140 Ethernet controller,
	5) the PPCBUG Motorola firmware in flash,
	6) A DEC PCI bridge,

This architecture is common to most Motorola 60x/7xx
board except that :
	1) on VME board, the DEC PCI bridge is replaced by
	a VME chipset,
	2) the VIA 82C586 PCI/ISA bridge is replaced by
	another bridge that is almost fully compatible
	with the via bridge...

So the port should be a rather close basis for many
60x/7xx motorola board...

On this board, I already have ported Linux 2.2.3 and
use it both as a development and target board.

Now the questions/suggestions I have :

1)  EXCEPTION CODE
-------------------

As far as I know exceptions on PPC are handled like
interrupts. I dislike this very much as :

	a) Except for the decrementer exception (and
	maybe some other on mpc8xx), exceptions are
	not recoverable and the handler just need to print
	the full context and go to the firmware or debugger...
	b) The interrupt switch is only necessary for the
	decrementer and external interrupt (at least on
	6xx,7xx).
	c) The full context for exception is never saved and
	thus cannot be used by debugger... I do understand
	the most important for interrupts low level code
	is to save the minimal context enabling	to call C
	code for performance reasons. On non recoverable
	exception on the other hand, the most important is
	to save the maximum information concerning proc status
	in order to analyze the reason of the fault. At
	least we will need this in order to implement the
	port of RGDB on PPC

==> I wrote an API for connecting raw exceptions (and thus
raw interrupts) for mpc750. It should be valid for most
powerpc processors... I hope to find a way to make this coexist
with actual code layout. The code is actually located
in lib/libcpu/powerpc/mpc750 and is thus optional
(provided I write my own version of exec/score/cpu/powerpc/cpu.c ...)

See remark about files/directory layout organization in 4)

2) Current Implementation of ISR low level code
-----------------------------------------------

I do not understand why the MSR EE flags is cleared
again in exec/score/cpu/powerpc/irq_stubs.S

#if (PPC_USE_SPRG)
	mfmsr	r5
	mfspr   r6, sprg2
#else
        lwz	r6,msr_initial(r11)
	lis     r5,~PPC_MSR_DISABLE_MASK@ha
        ori     r5,r5,~PPC_MSR_DISABLE_MASK@l
	and	r6,r6,r5
	mfmsr	r5
#endif

Reading the doc, when a decrementer interrupt or an
external interrupt is active, the MSR EE flag is already
cleared. BTW if exception/interrupt could occur, it would
trash SRR0 and SRR1. In fact the code may be useful to set
MSR[RI] that re-enables exception processing. BTW I will need
to set other value in MSR to handle interrupts :

	a) I want the MSR[IR] and MSR[DR] to be set for
	performance reasons and also because I need DBAT
	support to have access to PCI memory space as the
	interrupt controller is in the PCI space.

Reading the code, I see others have the same kind of request :

/* SCE 980217
 *
 * We need address translation ON when we call our ISR routine

	mtmsr	r5

 */

This is just another prof that even the lowest level
IRQ code is fundamentally board dependent and
not simply processor dependent especially when
the processor use external interrupt controller
because it has a single interrupt request line...

Note that if you look at the PPC code high level interrupt
handling code, as the "set_vector" routine that really connects
the interrupt is in the BSP/startup/genpvec.c,
the fact that IRQ handling is BSP specific is DE-FACTO
acknowledged.

I know I have already expressed this and understand that this
would require some heavy change in the code but believe
me you will reach a point where you will not be able
to find a compatible while optimum implementation for low level
interrupt handling code...) In my case this is already true...

So please consider removing low level IRQ handling from
exec/score/cpu/* and only let there exception handling code...
Exceptions are usually only processor dependent and do
not depend on external hardware mechanism to be masked or
acknowledged or re-enabled (there are probably exception but ...)

I have already done this for pc386 bsp but need to make it again.
This time I will even propose an API.

3) R2/R13 manipulation for EABI implementation
----------------------------------------------

I do not understand the handling of r2 and r13 in the
EABI case. The specification for r2 says pointer to sdata2,
sbss2 section => constant. However I do not see -ffixed-r2
passed to any compilation system in make/custom/*
(for info linux does this on PPC).

So either this is a default compiler option when choosing
powerpc-rtems and thus we do not need to do anything with
this register as all the code is compiled with this compiler
and linked together OR this register may be used by rtems code
and then we do not need any special initialization or
handling.

The specification for r13 says pointer to the small data
area. r13 argumentation is the same except that as far
as I know the usage of the small data area requires
specific compiler support so that access to variables is
compiled via loading the LSB in a register and then
using r13 to get full address... It is like a small
memory model and it was present in IBM C compilers.

=> I propose to suppress any specific code for r2 and
r13 in the EABI case.

4) Code layout organization (yes again :-))
-------------------------------------------

I think there are a number of design flaws in the way
the code is for ppc organized and I will try to point them out.
I have been beaten by this again on this new port, and
was beaten last year while modifying code for pc386.

a) exec/score/cpu/* vs lib/libcpu/cpu/*.

I think that too many things are put in exec/score/cpu that
have nothing to do with RTEMS internals but are rather
related to CPU feature.

This include at least :

	a) registers access routine (e.g GET_MSR_Value),
	b) interrupt masking/unmasking routines,
	c) cache_mngt_routine,
	d) mmu_mngt_routine,
	e) Routines to connect the raw_exception, raw_interrupt
	handler,

b) lib/libcpu/cpu/powerpc/*

With a processor family as exuberant as the powerpc family,
and their well known subtle differences (604 vs 750) or
unfortunately majors (8xx vs 60x)  the directory structure
is fine (except maybe the names that are not homogeneous)

	powerpc

ppc421 mpc821 ...

I only needed to add mpc750. But the fact that libcpu.a was not
produced was a pain and the fact that this organization may
duplicates code is also problematic.

So, except if the support of automake provides a better solution
I would like to propose something like this :

		powerpc

mpc421 	mpc821	...	mpc750	shared wrapup

with the following rules :

	a) "shared" would act as a source container for sources that may
	be shared among processors. Needed files would be compiled inside
	the processor specific directory using the vpath Makefile
	mechanism. "shared" may also contain compilation code
	for routine that are really shared and not worth to inline...
	(did not found many things so far as registers access routine
	ARE WORTH INLINING)... In the case something is compiled there,
	it should create libcpushared.a

	b) layout under processor specific directory is free provided
	that
		1)the result of the compilation process exports :

		libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu

		2) each processor specific directory creates
		a library called libcpuspecific.a
	Note that this organization enables to have a file that
	is nearly the same than in shared but that must differ
	because of processor differences...

	c) "wrapup" should create libcpu.a using libcpushared.a
	libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu

The only thing I have no ideal solution is the way to put shared
definitions in "shared" and only processor specific definition
in "proc". To give a concrete example, most MSR bit definition
are shared among PPC processors and only some differs. if we create
a single msr.h in shared it will have ifdef. If in msr.h we
include libcpu/msr_c.h we will need to have it in each prowerpc
specific directory (even empty). Opinions are welcomed ...

Note that a similar mechanism exist in libbsp/i386 that also
contains a shared directory that is used by several bsp
like pc386 and i386ex and a similar wrapup mechanism...

NB: I have done this for mpc750 and other processors could just use
similar Makefiles...

c) The exec/score/cpu/powerpc directory layout.

I think the directory layout should be the same than the
libcpu/powerpc. As it is not, there are a lot of ifdefs
inside the code... And of course low level interrupt handling
code should be removed...

Besides that I do not understand why

	1) things are compiled in the wrap directory,
	2) some includes are moved to rtems/score,

I think the "preinstall" mechanism enables to put
everything in the current directory (or better in a per processor
directory),


5) Interrupt handling API
-------------------------

Again :-). But I think that using all the features the PIC
offers is a MUST for RT system. I already explained in the
prologue of this (long and probably boring) mail that the MCP750
boards offers an OPENPIC compliant architecture and that
the VIA 82586 PCI/ISA bridge offers a PC compatible IO and
PIC mapping. Here is a logical view of the RAVEN/VIA 82586
interrupt mapping :


---------    0  ------
| OPEN	| <-----|8259|
| PIC	|	|    |    2  ------
|(RAVEN)|	|    | <-----|8259|
|	|	|    |	     |    |   11
|	|	|    |	     |    | <----
|	|	|    |	     |    |
|	|	|    |	     |    |
---------       ------	     |    |
    ^			     ------
    |		VIA PCI/ISA bridge
    |  x
    -------- PCI interrupts

OPENPIC offers interrupt priorities among PCI interrupts
and interrupt selective masking. The 8259 offers the same kind
of feature. With actual powerpc interrupt code :

	1) there is no way to specify priorities among
	interrupts handler. This is REALLY a bad thing.
	For me it is as importnat as having priorities
	for threads...
	2) for my implementation, each ISR should
	contain the code that acknowledge the RAVEN
	and 8259 cascade, modify interrupt mask on both
	chips, and reenable interrupt at processor level,
	..., restore then on interrupt return,.... This code
	is actually similar to code located in some
	genpvec.c powerpc files,
	3) I must update _ISR_Nesting_level because
	irq.inl use it...
	4) the libchip code connects the ISR via set_vector
	but the libchip handler code does not contain any code to
	manipulate external interrupt controller hardware
	in order to acknoledge the interrupt or re-enable
	them (except for the target hardware of course)
	So this code is broken unless set_vector adds an
	additionnal prologue/epilogue before calling/returning
	from in order to acknoledge/mask the raven and the
	8259 PICS... => Anyway already EACH BSP MUST REWRITE
	PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT
	SET_VECTOR.

I would rather offer an API similar to the one provided
in libbsp/i386/shared/irq/irq.h so that :

	1) Once the driver supplied methods is called the
	only things the ISR has to do is to worry about the
	external hardware that triggered the interrupt.
	Everything on openpic/VIA/processor would have been
	done by the low levels (same things as set-vector)
	2) The caller will need to supply the on/off/isOn
	routine that are fundamental to correctly implements
	debuggers/performance monitoring is a portable way
	3) A globally configurable interrupt priorities
	mechanism...

I have nothing against providing a compatible
set_vector just to make libchip happy but
as I have already explained in  other
mails (months ago), I really think that the ISR
connection should be handled by the BSP and that no
code containing irq connection should exist the
rtems generic layers... Thus I really dislike
libchip on this aspect because in a long term
it will force to adopt the less reach API
for interrupt handling that exists (set_vector).

Additional note : I think the _ISR_Is_in_progress()
inline routine should be :

	1) Put in a processor specific section,
	2) Should not rely on a global variable,

As :
	a) on symmetric MP, there is one interrupt level
	per CPU,
	b) On processor that have an ISP (e,g 68040),
	this variable is useless (MSR bit testing could
	be used)
	c) On PPC, instead of using the address of the
	variable via __CPU_IRQ_info.Nest_level a dedicated
	SPR could be used.

NOTE:	most of this is also true for _Thread_Dispatch_disable_level


END NOTE
--------

Please do not take what I said in the mail as a criticism for
anyone who submitted ppc code. Any code present helped me
a lot understanding PPC behavior. I just wanted by this
mail to :
	1) try to better understand the actual code,
	2) propose concrete ways of enhancing current code
	by providing an alternative implementation for MCP750. I
	will make my best effort to try to brake nothing but this
	is actually hard due to the file layout organisation.
	3) make understandable some changes I will probably make
	if joel let me do them :-)

Any comments/objections are welcomed as usual.



--
   __
  /  `                   	Eric Valette
 /--   __  o _.          	Canon CRF
(___, / (_(_(__         	Rue de la touche lambert
				35517 Cesson-Sevigne  Cedex
				FRANCE
Tel: +33 (0)2 99 87 68 91	Fax: +33 (0)2 99 84 11 30
E-mail: valette@crf.canon.fr

1 files changed, 0 insertions, 853 deletions

diff --git a/c/src/exec/score/cpu/powerpc/cpu.c b/c/src/exec/score/cpu/powerpc/cpu.c
deleted file mode 100644
index 1e1a7379f0..0000000000
--- a/c/src/exec/score/cpu/powerpc/cpu.c
+++ /dev/null
@@ -1,853 +0,0 @@
-/*
- *  PowerPC CPU Dependent Source
- *
- *  Author:	Andrew Bray <andy@i-cubed.co.uk>
- *
- *  COPYRIGHT (c) 1995 by i-cubed ltd.
- *
- *  To anyone who acknowledges that this file is provided "AS IS"
- *  without any express or implied warranty:
- *      permission to use, copy, modify, and distribute this file
- *      for any purpose is hereby granted without fee, provided that
- *      the above copyright notice and this notice appears in all
- *      copies, and that the name of i-cubed limited not be used in
- *      advertising or publicity pertaining to distribution of the
- *      software without specific, written prior permission.
- *      i-cubed limited makes no representations about the suitability
- *      of this software for any purpose.
- *
- *  Derived from c/src/exec/cpu/no_cpu/cpu.c:
- *
- *  COPYRIGHT (c) 1989-1997.
- *  On-Line Applications Research Corporation (OAR).
- *  Copyright assigned to U.S. Government, 1994.
- *
- *  The license and distribution terms for this file may be found in
- *  the file LICENSE in this distribution or at
- *  http://www.OARcorp.com/rtems/license.html.
- *
- *  $Id$
- */
-
-#include <rtems/system.h>
-#include <rtems/score/isr.h>
-#include <rtems/score/context.h>
-#include <rtems/score/thread.h>
-#include <rtems/score/interr.h>
-
-/*
- *  These are for testing purposes.
- */
-
-/*  _CPU_Initialize
- *
- *  This routine performs processor dependent initialization.
- *
- *  INPUT PARAMETERS:
- *    cpu_table       - CPU table to initialize
- *    thread_dispatch - address of disptaching routine
- */
-
-static void ppc_spurious(int, CPU_Interrupt_frame *);
-
-void _CPU_Initialize(
-  rtems_cpu_table  *cpu_table,
-  void      (*thread_dispatch)      /* ignored on this CPU */
-)
-{
-  proc_ptr handler = (proc_ptr)ppc_spurious;
-  int i;
-#if (PPC_ABI != PPC_ABI_POWEROPEN)
-  register unsigned32 r2 = 0;
-#if (PPC_ABI != PPC_ABI_GCC27)
-  register unsigned32 r13 = 0;
-
-  asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13)));
-  _CPU_IRQ_info.Default_r13 = r13;
-#endif
-
-  asm ("mr %0,2" : "=r" ((r2)) : "0" ((r2)));
-  _CPU_IRQ_info.Default_r2 = r2;
-#endif
-
-  _CPU_IRQ_info.Nest_level = &_ISR_Nest_level;
-  _CPU_IRQ_info.Disable_level = &_Thread_Dispatch_disable_level;
-  _CPU_IRQ_info.Vector_table = _ISR_Vector_table;
-#if (PPC_ABI == PPC_ABI_POWEROPEN)
-  _CPU_IRQ_info.Dispatch_r2 = ((unsigned32 *)_Thread_Dispatch)[1];
-#endif
-  _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary;
-  _CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing;
-
-#if (PPC_USE_SPRG)
-  i = (int)&_CPU_IRQ_info;
-  asm volatile("mtspr 0x113, %0" : "=r" (i) : "0" (i)); /* SPRG 3 */
-#endif
-
-  /*
-   * Store Msr Value in the IRQ info structure.
-   */
-   _CPU_MSR_Value(_CPU_IRQ_info.msr_initial);
-  
-#if (PPC_USE_SPRG)
-  i = _CPU_IRQ_info.msr_initial;
-  asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */
-#endif
-
-  if ( cpu_table->spurious_handler )
-    handler = (proc_ptr)cpu_table->spurious_handler;
-
-  for (i = 0; i < PPC_INTERRUPT_MAX;  i++)
-    _ISR_Vector_table[i] = handler;
-
-  _CPU_Table = *cpu_table;
-}
-
-/*PAGE
- *
- *  _CPU_ISR_Calculate_level
- *
- *  The PowerPC puts its interrupt enable status in the MSR register
- *  which also contains things like endianness control.  To be more
- *  awkward, the layout varies from processor to processor.  This
- *  is why it was necessary to adopt a scheme which allowed the user
- *  to specify specifically which interrupt sources were enabled.
- */
- 
-unsigned32 _CPU_ISR_Calculate_level(
-  unsigned32 new_level
-)
-{
-  register unsigned32 new_msr = 0;
-
-  /*
-   *  Set the critical interrupt enable bit
-   */
-
-#if (PPC_HAS_RFCI)
-  if ( !(new_level & PPC_INTERRUPT_LEVEL_CE) )
-    new_msr |= PPC_MSR_CE;
-#endif
-
-  if ( !(new_level & PPC_INTERRUPT_LEVEL_ME) )
-    new_msr |= PPC_MSR_ME;
-
-  if ( !(new_level & PPC_INTERRUPT_LEVEL_EE) )
-    new_msr |= PPC_MSR_EE;
-
-  return new_msr;
-}
-
-/*PAGE
- *
- *  _CPU_ISR_Set_level
- *
- *  This routine sets the requested level in the MSR.
- */
-
-void _CPU_ISR_Set_level(
-  unsigned32 new_level
-)
-{
-  register unsigned32 tmp = 0;
-  register unsigned32 new_msr;
-
-  new_msr = _CPU_ISR_Calculate_level( new_level );
-
-  asm volatile (
-    "mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" :
-    "=&r" ((tmp)) :
-    "r" ((PPC_MSR_DISABLE_MASK)), "r" ((new_msr)), "0" ((tmp))
-  );
-}
-
-/*PAGE
- *
- *  _CPU_ISR_Get_level
- *
- *  This routine gets the current interrupt level from the MSR and 
- *  converts it to an RTEMS interrupt level.
- */
-
-unsigned32 _CPU_ISR_Get_level( void )
-{
-  unsigned32 level = 0;
-  unsigned32 msr;
- 
-  asm volatile("mfmsr %0" : "=r" ((msr)));
- 
-  msr &= PPC_MSR_DISABLE_MASK;
-
-  /*
-   *  Set the critical interrupt enable bit
-   */
-
-#if (PPC_HAS_RFCI)
-  if ( !(msr & PPC_MSR_CE) )
-    level |= PPC_INTERRUPT_LEVEL_CE;
-#endif
-
-  if ( !(msr & PPC_MSR_ME) )
-    level |= PPC_INTERRUPT_LEVEL_ME;
-
-  if ( !(msr & PPC_MSR_EE) )
-    level |= PPC_INTERRUPT_LEVEL_EE;
-
-  return level;
-}
-
-/*PAGE
- *
- *  _CPU_Context_Initialize
- */
-
-#if (PPC_ABI == PPC_ABI_POWEROPEN)
-#define CPU_MINIMUM_STACK_FRAME_SIZE 56
-#else /* PPC_ABI_SVR4 or PPC_ABI_EABI */
-#define CPU_MINIMUM_STACK_FRAME_SIZE 8
-#endif
-
-void _CPU_Context_Initialize(
-  Context_Control  *the_context,
-  unsigned32       *stack_base,
-  unsigned32        size,
-  unsigned32        new_level,
-  void             *entry_point,
-  boolean           is_fp
-)
-{
-  unsigned32 msr_value;
-  unsigned32 sp;
-
-  sp = (unsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
-  *((unsigned32 *)sp) = 0;
-  the_context->gpr1 = sp;
-   
-  the_context->msr = _CPU_ISR_Calculate_level( new_level );
-
-  /*
-   *  The FP bit of the MSR should only be enabled if this is a floating
-   *  point task.  Unfortunately, the vfprintf_r routine in newlib 
-   *  ends up pushing a floating point register regardless of whether or
-   *  not a floating point number is being printed.  Serious restructuring
-   *  of vfprintf.c will be required to avoid this behavior.  At this
-   *  time (7 July 1997), this restructuring is not being done.
-   */
-
-  /*if ( is_fp ) */
-    the_context->msr |= PPC_MSR_FP;
-
-  /*
-   *  Calculate the task's MSR value:
-   *
-   *     + Set the exception prefix bit to point to the exception table
-   *     + Force the RI bit
-   *     + Use the DR and IR bits 
-   */
-  _CPU_MSR_Value( msr_value );
-  the_context->msr |= (msr_value & PPC_MSR_EP);
-  the_context->msr |= PPC_MSR_RI;
-  the_context->msr |= msr_value & (PPC_MSR_DR|PPC_MSR_IR);
-
-#if (PPC_ABI == PPC_ABI_POWEROPEN)
-  { unsigned32 *desc = (unsigned32 *)entry_point;
-
-    the_context->pc = desc[0];
-    the_context->gpr2 = desc[1];
-  }
-#endif
-
-#if (PPC_ABI == PPC_ABI_SVR4)
-  { unsigned    r13 = 0;
-    asm volatile ("mr %0, 13" : "=r" ((r13)));
-   
-    the_context->pc = (unsigned32)entry_point;
-    the_context->gpr13 = r13;
-  }
-#endif
-
-#if (PPC_ABI == PPC_ABI_EABI)
-  { unsigned32  r2 = 0;
-    unsigned    r13 = 0;
-    asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
- 
-    the_context->pc = (unsigned32)entry_point;
-    the_context->gpr2 = r2;
-    the_context->gpr13 = r13;
-  }
-#endif
-}
-
-
-/*  _CPU_ISR_install_vector
- *
- *  This kernel routine installs the RTEMS handler for the
- *  specified vector.
- *
- *  Input parameters:
- *    vector      - interrupt vector number
- *    old_handler - former ISR for this vector number
- *    new_handler - replacement ISR for this vector number
- *
- *  Output parameters:  NONE
- *
- */
-
-void _CPU_ISR_install_vector(
-  unsigned32  vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-)
-{
-   proc_ptr   ignored;
-   *old_handler = _ISR_Vector_table[ vector ];
-
-   /*
-    *  If the interrupt vector table is a table of pointer to isr entry
-    *  points, then we need to install the appropriate RTEMS interrupt
-    *  handler for this vector number.
-    */
-
-   /*
-    * Install the wrapper so this ISR can be invoked properly.
-    */
-   if (_CPU_Table.exceptions_in_RAM) 
-      _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
-
-   /*
-    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
-    *  be used by the _ISR_Handler so the user gets control.
-    */
-
-    _ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler :
-       _CPU_Table.spurious_handler ? 
-          (ISR_Handler_entry)_CPU_Table.spurious_handler :
-          (ISR_Handler_entry)ppc_spurious;
-}
-
-/*PAGE
- *
- *  _CPU_Install_interrupt_stack
- */
-
-void _CPU_Install_interrupt_stack( void )
-{
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
-  _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 56;
-#else
-  _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 8;
-#endif
-}
-
-/* Handle a spurious interrupt */
-static void ppc_spurious(int v, CPU_Interrupt_frame *i)
-{
-#if 0
-    printf("Spurious interrupt on vector %d from %08.8x\n",
-	   v, i->pc);
-#endif
-#ifdef ppc403
-    if (v == PPC_IRQ_EXTERNAL)
-	{
-	    register int r = 0;
-
-	    asm volatile("mtdcr 0x42, %0" :
-                "=&r" ((r)) : "0" ((r))); /* EXIER */
-	}
-    else if (v == PPC_IRQ_PIT)
-	{
-	    register int r = 0x08000000;
-
-	    asm volatile("mtspr 0x3d8, %0" :
-                "=&r" ((r)) : "0" ((r))); /* TSR */
-	}
-    else if (v == PPC_IRQ_FIT)
-	{
-	    register int r = 0x04000000;
-
-	    asm volatile("mtspr 0x3d8, %0" :
-                "=&r" ((r)) : "0" ((r))); /* TSR */
-	}
-#endif
-}
-
-void _CPU_Fatal_error(unsigned32 _error)
-{
-  asm volatile ("mr 3, %0" : : "r" ((_error)));
-  asm volatile ("tweq 5,5");
-  asm volatile ("li 0,0; mtmsr 0");
-  while (1) ;
-}
-
-#define PPC_SYNCHRONOUS_TRAP_BIT_MASK    0x100
-#define PPC_ASYNCHRONOUS_TRAP( _trap ) (_trap)
-#define PPC_SYNCHRONOUS_TRAP ( _trap ) ((_trap)+PPC_SYNCHRONOUS_TRAP_BIT_MASK)
-#define PPC_REAL_TRAP_NUMBER ( _trap ) ((_trap)%PPC_SYNCHRONOUS_TRAP_BIT_MASK)
-
-
-const CPU_Trap_table_entry _CPU_Trap_slot_template = {
-
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
-#error " Vector install not tested."
-#if (PPC_HAS_FPU)
-#error " Vector install not tested."
-  0x9421feb0,           /* stwu r1, -(20*4 + 18*8 + IP_END)(r1) */
-#else
-#error " Vector install not tested."
-  0x9421ff40,           /* stwu    r1, -(20*4 + IP_END)(r1)     */
-#endif
-#else
-  0x9421ff90,           /* stwu    r1, -(IP_END)(r1)            */
-#endif
-
-  0x90010008,           /* stw   %r0, IP_0(%r1)                 */
-  0x38000000,           /* li    %r0, PPC_IRQ                   */
-  0x48000002            /* ba    PROC (_ISR_Handler)            */
-};
-
-#if defined(mpc860) || defined(mpc821)
-const CPU_Trap_table_entry _CPU_Trap_slot_template_m860 = {
-  0x7c0803ac,           /* mtlr  %r0                            */
-  0x81210028,           /* lwz   %r9, IP_9(%r1)                 */
-  0x38000000,           /* li    %r0, PPC_IRQ                   */
-  0x48000002            /* b     PROC (_ISR_Handler)            */
-};
-#endif /* mpc860 */
-
-unsigned32  ppc_exception_vector_addr( 
-  unsigned32 vector
-);
-
-
-/*PAGE
- *
- *  _CPU_ISR_install_raw_handler
- *
- *  This routine installs the specified handler as a "raw" non-executive
- *  supported trap handler (a.k.a. interrupt service routine).
- *
- *  Input Parameters:
- *    vector      - trap table entry number plus synchronous 
- *                    vs. asynchronous information
- *    new_handler - address of the handler to be installed
- *    old_handler - pointer to an address of the handler previously installed
- *
- *  Output Parameters: NONE
- *    *new_handler - address of the handler previously installed
- * 
- *  NOTE: 
- *
- *  This routine is based on the SPARC routine _CPU_ISR_install_raw_handler.
- *  Install a software trap handler as an executive interrupt handler 
- *  (which is desirable since RTEMS takes care of window and register issues),
- *  then the executive needs to know that the return address is to the trap 
- *  rather than the instruction following the trap.
- *
- */
- 
-void _CPU_ISR_install_raw_handler(
-  unsigned32  vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-)
-{
-  unsigned32             real_vector;
-  CPU_Trap_table_entry  *slot;
-  unsigned32             u32_handler=0;
-
-  /*
-   *  Get the "real" trap number for this vector ignoring the synchronous
-   *  versus asynchronous indicator included with our vector numbers.
-   */
-
-  real_vector = vector;
-
-  /*
-   *  Get the current base address of the trap table and calculate a pointer
-   *  to the slot we are interested in.
-   */
-  slot = (CPU_Trap_table_entry  *)ppc_exception_vector_addr( real_vector );
-
-  /*
-   *  Get the address of the old_handler from the trap table.
-   *
-   *  NOTE: The old_handler returned will be bogus if it does not follow
-   *        the RTEMS model.
-   */
-
-#define HIGH_BITS_MASK   0xFFFFFC00
-#define HIGH_BITS_SHIFT  10
-#define LOW_BITS_MASK    0x000003FF
-
-  if (slot->stwu_r1 == _CPU_Trap_slot_template.stwu_r1) {
-    /* 
-     * Set u32_handler = to target address  
-     */
-    u32_handler = slot->b_Handler & 0x03fffffc;
-
-    /* IMD FIX: sign extend address fragment... */
-    if (u32_handler & 0x02000000) {
-      u32_handler  |= 0xfc000000;
-    }
-
-    *old_handler =  (proc_ptr) u32_handler;
-  } else
-/* There are two kinds of handlers for the MPC860. One is the 'standard' 
- *  one like above. The other is for the cascaded interrupts from the SIU
- *  and CPM. Therefore we must check for the alternate one if the standard
- *  one is not present
- */
-#if defined(mpc860) || defined(mpc821)
-  if (slot->stwu_r1 == _CPU_Trap_slot_template_m860.stwu_r1) {
-    /* 
-     * Set u32_handler = to target address  
-     */
-    u32_handler = slot->b_Handler & 0x03fffffc;
-    *old_handler =  (proc_ptr) u32_handler;
-  } else
-#endif /* mpc860 */
-
-    *old_handler = 0;
-
-  /*
-   *  Copy the template to the slot and then fix it.
-   */
-#if defined(mpc860) || defined(mpc821)
-  if (vector >= PPC_IRQ_IRQ0)
-    *slot = _CPU_Trap_slot_template_m860;
-  else
-#endif /* mpc860 */
-  *slot = _CPU_Trap_slot_template;
-
-  u32_handler = (unsigned32) new_handler;
-
-  /* 
-   * IMD FIX: insert address fragment only (bits 6..29) 
-   *          therefore check for proper address range 
-   *          and remove unwanted bits
-   */
-  if ((u32_handler & 0xfc000000) == 0xfc000000) {
-    u32_handler  &= ~0xfc000000;
-  }
-  else if ((u32_handler & 0xfc000000) != 0x00000000) {
-    _Internal_error_Occurred(INTERNAL_ERROR_CORE,
-			     TRUE,
-			     u32_handler);
-  }
-
-  slot->b_Handler |= u32_handler;
-
-  slot->li_r0_IRQ  |= vector;
-
-  _CPU_Data_Cache_Block_Flush( slot );
-}
-
-unsigned32  ppc_exception_vector_addr( 
-  unsigned32 vector
-)
-{
-#if (!PPC_HAS_EVPR)
-  unsigned32 Msr;
-#endif
-  unsigned32 Top = 0;
-  unsigned32 Offset = 0x000;
-
-#if (PPC_HAS_EXCEPTION_PREFIX)
-  _CPU_MSR_Value ( Msr );
-  if ( ( Msr & PPC_MSR_EP) != 0 ) /* Vectors at FFFx_xxxx */
-    Top = 0xfff00000;
-#elif (PPC_HAS_EVPR)
-  asm volatile( "mfspr %0,0x3d6" : "=r" (Top)); /* EVPR */
-  Top = Top & 0xffff0000;
-#endif
-
-  switch ( vector ) {
-    case PPC_IRQ_SYSTEM_RESET:   /* on 40x aka PPC_IRQ_CRIT */
-      Offset = 0x00100;
-      break;
-    case PPC_IRQ_MCHECK:
-      Offset = 0x00200;
-      break;
-    case PPC_IRQ_PROTECT:
-      Offset = 0x00300;
-      break;
-    case PPC_IRQ_ISI:
-      Offset = 0x00400;
-      break;
-    case PPC_IRQ_EXTERNAL:
-      Offset = 0x00500;
-      break;
-    case PPC_IRQ_ALIGNMENT:
-      Offset = 0x00600;
-      break;
-    case PPC_IRQ_PROGRAM:
-      Offset = 0x00700;
-      break;
-    case PPC_IRQ_NOFP:
-      Offset = 0x00800;
-      break;
-    case PPC_IRQ_DECREMENTER:
-      Offset = 0x00900;
-      break;
-    case PPC_IRQ_RESERVED_A:
-      Offset = 0x00a00;
-      break;
-    case PPC_IRQ_RESERVED_B:
-      Offset = 0x00b00;
-      break;
-    case PPC_IRQ_SCALL:
-      Offset = 0x00c00;
-      break;
-    case PPC_IRQ_TRACE:
-      Offset = 0x00d00;
-      break;
-    case PPC_IRQ_FP_ASST:
-      Offset = 0x00e00;
-      break;
-
-#if defined(ppc403)
-                                  
-/*  PPC_IRQ_CRIT is the same vector as PPC_IRQ_RESET
-    case PPC_IRQ_CRIT:
-      Offset = 0x00100;
-      break;
-*/
-    case PPC_IRQ_PIT:
-      Offset = 0x01000;
-      break;
-    case PPC_IRQ_FIT:
-      Offset = 0x01010;
-      break;
-    case PPC_IRQ_WATCHDOG:
-      Offset = 0x01020;
-      break;
-    case PPC_IRQ_DEBUG:
-      Offset = 0x02000;
-      break;
-
-#elif defined(ppc601)
-    case PPC_IRQ_TRACE:
-      Offset = 0x02000;
-      break;
-
-#elif defined(ppc603)
-    case PPC_IRQ_TRANS_MISS:
-      Offset = 0x1000;
-      break;
-    case PPC_IRQ_DATA_LOAD:
-      Offset = 0x1100;
-      break;
-    case PPC_IRQ_DATA_STORE:
-      Offset = 0x1200;
-      break;
-    case PPC_IRQ_ADDR_BRK:
-      Offset = 0x1300;
-      break;
-    case PPC_IRQ_SYS_MGT:
-      Offset = 0x1400;
-      break;
-
-#elif defined(ppc603e)
-    case PPC_TLB_INST_MISS:
-      Offset = 0x1000;
-      break;
-    case PPC_TLB_LOAD_MISS:
-      Offset = 0x1100;
-      break;
-    case PPC_TLB_STORE_MISS:
-      Offset = 0x1200;
-      break;
-    case PPC_IRQ_ADDRBRK:
-      Offset = 0x1300;
-      break;
-    case PPC_IRQ_SYS_MGT:
-      Offset = 0x1400;
-      break;
-
-#elif defined(ppc604)
-    case PPC_IRQ_ADDR_BRK:
-      Offset = 0x1300;
-      break;
-    case PPC_IRQ_SYS_MGT:
-      Offset = 0x1400;
-      break;
-
-#elif defined(mpc860) || defined(mpc821)
-    case PPC_IRQ_EMULATE:
-      Offset = 0x1000;
-      break;
-    case PPC_IRQ_INST_MISS:
-      Offset = 0x1100;
-      break;
-    case PPC_IRQ_DATA_MISS:
-      Offset = 0x1200;
-      break;
-    case PPC_IRQ_INST_ERR:
-      Offset = 0x1300;
-      break;
-    case PPC_IRQ_DATA_ERR:
-      Offset = 0x1400;
-      break;
-    case PPC_IRQ_DATA_BPNT:
-      Offset = 0x1c00;
-      break;
-    case PPC_IRQ_INST_BPNT:
-      Offset = 0x1d00;
-      break;
-    case PPC_IRQ_IO_BPNT:
-      Offset = 0x1e00;
-      break;
-    case PPC_IRQ_DEV_PORT:
-      Offset = 0x1f00;
-      break;
-    case PPC_IRQ_IRQ0:
-      Offset = 0x2000;
-      break;
-    case PPC_IRQ_LVL0:
-      Offset = 0x2040;
-      break;
-    case PPC_IRQ_IRQ1:
-      Offset = 0x2080;
-      break;
-    case PPC_IRQ_LVL1:
-      Offset = 0x20c0;
-      break;
-    case PPC_IRQ_IRQ2:
-      Offset = 0x2100;
-      break;
-    case PPC_IRQ_LVL2:
-      Offset = 0x2140;
-      break;
-    case PPC_IRQ_IRQ3:
-      Offset = 0x2180;
-      break;
-    case PPC_IRQ_LVL3:
-      Offset = 0x21c0;
-      break;
-    case PPC_IRQ_IRQ4:
-      Offset = 0x2200;
-      break;
-    case PPC_IRQ_LVL4:
-      Offset = 0x2240;
-      break;
-    case PPC_IRQ_IRQ5:
-      Offset = 0x2280;
-      break;
-    case PPC_IRQ_LVL5:
-      Offset = 0x22c0;
-      break;
-    case PPC_IRQ_IRQ6:
-      Offset = 0x2300;
-      break;
-    case PPC_IRQ_LVL6:
-      Offset = 0x2340;
-      break;
-    case PPC_IRQ_IRQ7:
-      Offset = 0x2380;
-      break;
-    case PPC_IRQ_LVL7:
-      Offset = 0x23c0;
-      break;
-    case PPC_IRQ_CPM_RESERVED_0:
-      Offset = 0x2400;
-      break;
-    case PPC_IRQ_CPM_PC4:
-      Offset = 0x2410;
-      break;
-    case PPC_IRQ_CPM_PC5:
-      Offset = 0x2420;
-      break;
-    case PPC_IRQ_CPM_SMC2:
-      Offset = 0x2430;
-      break;
-    case PPC_IRQ_CPM_SMC1:
-      Offset = 0x2440;
-      break;
-    case PPC_IRQ_CPM_SPI:
-      Offset = 0x2450;
-      break;
-    case PPC_IRQ_CPM_PC6:
-      Offset = 0x2460;
-      break;
-    case PPC_IRQ_CPM_TIMER4:
-      Offset = 0x2470;
-      break;
-    case PPC_IRQ_CPM_RESERVED_8:
-      Offset = 0x2480;
-      break;
-    case PPC_IRQ_CPM_PC7:
-      Offset = 0x2490;
-      break;
-    case PPC_IRQ_CPM_PC8:
-      Offset = 0x24a0;
-      break;
-    case PPC_IRQ_CPM_PC9:
-      Offset = 0x24b0;
-      break;
-    case PPC_IRQ_CPM_TIMER3:
-      Offset = 0x24c0;
-      break;
-    case PPC_IRQ_CPM_RESERVED_D:
-      Offset = 0x24d0;
-      break;
-    case PPC_IRQ_CPM_PC10:
-      Offset = 0x24e0;
-      break;
-    case PPC_IRQ_CPM_PC11:
-      Offset = 0x24f0;
-      break;
-    case PPC_IRQ_CPM_I2C:
-      Offset = 0x2500;
-      break;
-    case PPC_IRQ_CPM_RISC_TIMER:
-      Offset = 0x2510;
-      break;
-    case PPC_IRQ_CPM_TIMER2:
-      Offset = 0x2520;
-      break;
-    case PPC_IRQ_CPM_RESERVED_13:
-      Offset = 0x2530;
-      break;
-    case PPC_IRQ_CPM_IDMA2:
-      Offset = 0x2540;
-      break;
-    case PPC_IRQ_CPM_IDMA1:
-      Offset = 0x2550;
-      break;
-    case PPC_IRQ_CPM_SDMA_ERROR:
-      Offset = 0x2560;
-      break;
-    case PPC_IRQ_CPM_PC12:
-      Offset = 0x2570;
-      break;
-    case PPC_IRQ_CPM_PC13:
-      Offset = 0x2580;
-      break;
-    case PPC_IRQ_CPM_TIMER1:
-      Offset = 0x2590;
-      break;
-    case PPC_IRQ_CPM_PC14:
-      Offset = 0x25a0;
-      break;
-    case PPC_IRQ_CPM_SCC4:
-      Offset = 0x25b0;
-      break;
-    case PPC_IRQ_CPM_SCC3:
-      Offset = 0x25c0;
-      break;
-    case PPC_IRQ_CPM_SCC2:
-      Offset = 0x25d0;
-      break;
-    case PPC_IRQ_CPM_SCC1:
-      Offset = 0x25e0;
-      break;
-    case PPC_IRQ_CPM_PC15:
-      Offset = 0x25f0;
-      break;
-#endif
-
-  }
-  Top += Offset;
-  return Top;
-}
-