This is a large patch from Eric Valette <valette@crf.canon.fr> that was

described in the message following this paragraph.  This patch also includes
a mcp750 BSP.

From valette@crf.canon.fr Mon Jun 14 10:03:08 1999
Date: Tue, 18 May 1999 01:30:14 +0200 (CEST)
From: VALETTE Eric <valette@crf.canon.fr>
To: joel@oarcorp.com
Cc: raguet@crf.canon.fr, rtems-snapshots@oarcorp.com, valette@crf.canon.fr
Subject: Questions/Suggestion regarding RTEMS PowerPC code (long)


Dear knowledgeable RTEMS powerpc users,

As some of you may know, I'm currently finalizing a port
of RTEMS on a MCP750 Motorola board. I have done most
of it but have some questions to ask before submitting
the port.

In order to understand some of the changes I have made
or would like to make, maybe it is worth describing the
MCP750 Motorola board.

the MCP750 is a COMPACT PCI powerpc board with :

	1) a MPC750 233 MHz processor,
	2) a raven bus bridge/PCI controller that
	implement an OPENPIC compliant interrupt controller,
	3) a VIA 82C586 PCI/ISA bridge that offers a PC
	compliant IO for keyboard, serial line, IDE, and
	the well known PC 8259 cascaded PIC interrupt
	architecture model,
	4) a DEC 21140 Ethernet controller,
	5) the PPCBUG Motorola firmware in flash,
	6) A DEC PCI bridge,

This architecture is common to most Motorola 60x/7xx
board except that :
	1) on VME board, the DEC PCI bridge is replaced by
	a VME chipset,
	2) the VIA 82C586 PCI/ISA bridge is replaced by
	another bridge that is almost fully compatible
	with the via bridge...

So the port should be a rather close basis for many
60x/7xx motorola board...

On this board, I already have ported Linux 2.2.3 and
use it both as a development and target board.

Now the questions/suggestions I have :

1)  EXCEPTION CODE
-------------------

As far as I know exceptions on PPC are handled like
interrupts. I dislike this very much as :

	a) Except for the decrementer exception (and
	maybe some other on mpc8xx), exceptions are
	not recoverable and the handler just need to print
	the full context and go to the firmware or debugger...
	b) The interrupt switch is only necessary for the
	decrementer and external interrupt (at least on
	6xx,7xx).
	c) The full context for exception is never saved and
	thus cannot be used by debugger... I do understand
	the most important for interrupts low level code
	is to save the minimal context enabling	to call C
	code for performance reasons. On non recoverable
	exception on the other hand, the most important is
	to save the maximum information concerning proc status
	in order to analyze the reason of the fault. At
	least we will need this in order to implement the
	port of RGDB on PPC

==> I wrote an API for connecting raw exceptions (and thus
raw interrupts) for mpc750. It should be valid for most
powerpc processors... I hope to find a way to make this coexist
with actual code layout. The code is actually located
in lib/libcpu/powerpc/mpc750 and is thus optional
(provided I write my own version of exec/score/cpu/powerpc/cpu.c ...)

See remark about files/directory layout organization in 4)

2) Current Implementation of ISR low level code
-----------------------------------------------

I do not understand why the MSR EE flags is cleared
again in exec/score/cpu/powerpc/irq_stubs.S

#if (PPC_USE_SPRG)
	mfmsr	r5
	mfspr   r6, sprg2
#else
        lwz	r6,msr_initial(r11)
	lis     r5,~PPC_MSR_DISABLE_MASK@ha
        ori     r5,r5,~PPC_MSR_DISABLE_MASK@l
	and	r6,r6,r5
	mfmsr	r5
#endif

Reading the doc, when a decrementer interrupt or an
external interrupt is active, the MSR EE flag is already
cleared. BTW if exception/interrupt could occur, it would
trash SRR0 and SRR1. In fact the code may be useful to set
MSR[RI] that re-enables exception processing. BTW I will need
to set other value in MSR to handle interrupts :

	a) I want the MSR[IR] and MSR[DR] to be set for
	performance reasons and also because I need DBAT
	support to have access to PCI memory space as the
	interrupt controller is in the PCI space.

Reading the code, I see others have the same kind of request :

/* SCE 980217
 *
 * We need address translation ON when we call our ISR routine

	mtmsr	r5

 */

This is just another prof that even the lowest level
IRQ code is fundamentally board dependent and
not simply processor dependent especially when
the processor use external interrupt controller
because it has a single interrupt request line...

Note that if you look at the PPC code high level interrupt
handling code, as the "set_vector" routine that really connects
the interrupt is in the BSP/startup/genpvec.c,
the fact that IRQ handling is BSP specific is DE-FACTO
acknowledged.

I know I have already expressed this and understand that this
would require some heavy change in the code but believe
me you will reach a point where you will not be able
to find a compatible while optimum implementation for low level
interrupt handling code...) In my case this is already true...

So please consider removing low level IRQ handling from
exec/score/cpu/* and only let there exception handling code...
Exceptions are usually only processor dependent and do
not depend on external hardware mechanism to be masked or
acknowledged or re-enabled (there are probably exception but ...)

I have already done this for pc386 bsp but need to make it again.
This time I will even propose an API.

3) R2/R13 manipulation for EABI implementation
----------------------------------------------

I do not understand the handling of r2 and r13 in the
EABI case. The specification for r2 says pointer to sdata2,
sbss2 section => constant. However I do not see -ffixed-r2
passed to any compilation system in make/custom/*
(for info linux does this on PPC).

So either this is a default compiler option when choosing
powerpc-rtems and thus we do not need to do anything with
this register as all the code is compiled with this compiler
and linked together OR this register may be used by rtems code
and then we do not need any special initialization or
handling.

The specification for r13 says pointer to the small data
area. r13 argumentation is the same except that as far
as I know the usage of the small data area requires
specific compiler support so that access to variables is
compiled via loading the LSB in a register and then
using r13 to get full address... It is like a small
memory model and it was present in IBM C compilers.

=> I propose to suppress any specific code for r2 and
r13 in the EABI case.

4) Code layout organization (yes again :-))
-------------------------------------------

I think there are a number of design flaws in the way
the code is for ppc organized and I will try to point them out.
I have been beaten by this again on this new port, and
was beaten last year while modifying code for pc386.

a) exec/score/cpu/* vs lib/libcpu/cpu/*.

I think that too many things are put in exec/score/cpu that
have nothing to do with RTEMS internals but are rather
related to CPU feature.

This include at least :

	a) registers access routine (e.g GET_MSR_Value),
	b) interrupt masking/unmasking routines,
	c) cache_mngt_routine,
	d) mmu_mngt_routine,
	e) Routines to connect the raw_exception, raw_interrupt
	handler,

b) lib/libcpu/cpu/powerpc/*

With a processor family as exuberant as the powerpc family,
and their well known subtle differences (604 vs 750) or
unfortunately majors (8xx vs 60x)  the directory structure
is fine (except maybe the names that are not homogeneous)

	powerpc

ppc421 mpc821 ...

I only needed to add mpc750. But the fact that libcpu.a was not
produced was a pain and the fact that this organization may
duplicates code is also problematic.

So, except if the support of automake provides a better solution
I would like to propose something like this :

		powerpc

mpc421 	mpc821	...	mpc750	shared wrapup

with the following rules :

	a) "shared" would act as a source container for sources that may
	be shared among processors. Needed files would be compiled inside
	the processor specific directory using the vpath Makefile
	mechanism. "shared" may also contain compilation code
	for routine that are really shared and not worth to inline...
	(did not found many things so far as registers access routine
	ARE WORTH INLINING)... In the case something is compiled there,
	it should create libcpushared.a

	b) layout under processor specific directory is free provided
	that
		1)the result of the compilation process exports :

		libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu

		2) each processor specific directory creates
		a library called libcpuspecific.a
	Note that this organization enables to have a file that
	is nearly the same than in shared but that must differ
	because of processor differences...

	c) "wrapup" should create libcpu.a using libcpushared.a
	libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu

The only thing I have no ideal solution is the way to put shared
definitions in "shared" and only processor specific definition
in "proc". To give a concrete example, most MSR bit definition
are shared among PPC processors and only some differs. if we create
a single msr.h in shared it will have ifdef. If in msr.h we
include libcpu/msr_c.h we will need to have it in each prowerpc
specific directory (even empty). Opinions are welcomed ...

Note that a similar mechanism exist in libbsp/i386 that also
contains a shared directory that is used by several bsp
like pc386 and i386ex and a similar wrapup mechanism...

NB: I have done this for mpc750 and other processors could just use
similar Makefiles...

c) The exec/score/cpu/powerpc directory layout.

I think the directory layout should be the same than the
libcpu/powerpc. As it is not, there are a lot of ifdefs
inside the code... And of course low level interrupt handling
code should be removed...

Besides that I do not understand why

	1) things are compiled in the wrap directory,
	2) some includes are moved to rtems/score,

I think the "preinstall" mechanism enables to put
everything in the current directory (or better in a per processor
directory),


5) Interrupt handling API
-------------------------

Again :-). But I think that using all the features the PIC
offers is a MUST for RT system. I already explained in the
prologue of this (long and probably boring) mail that the MCP750
boards offers an OPENPIC compliant architecture and that
the VIA 82586 PCI/ISA bridge offers a PC compatible IO and
PIC mapping. Here is a logical view of the RAVEN/VIA 82586
interrupt mapping :


---------    0  ------
| OPEN	| <-----|8259|
| PIC	|	|    |    2  ------
|(RAVEN)|	|    | <-----|8259|
|	|	|    |	     |    |   11
|	|	|    |	     |    | <----
|	|	|    |	     |    |
|	|	|    |	     |    |
---------       ------	     |    |
    ^			     ------
    |		VIA PCI/ISA bridge
    |  x
    -------- PCI interrupts

OPENPIC offers interrupt priorities among PCI interrupts
and interrupt selective masking. The 8259 offers the same kind
of feature. With actual powerpc interrupt code :

	1) there is no way to specify priorities among
	interrupts handler. This is REALLY a bad thing.
	For me it is as importnat as having priorities
	for threads...
	2) for my implementation, each ISR should
	contain the code that acknowledge the RAVEN
	and 8259 cascade, modify interrupt mask on both
	chips, and reenable interrupt at processor level,
	..., restore then on interrupt return,.... This code
	is actually similar to code located in some
	genpvec.c powerpc files,
	3) I must update _ISR_Nesting_level because
	irq.inl use it...
	4) the libchip code connects the ISR via set_vector
	but the libchip handler code does not contain any code to
	manipulate external interrupt controller hardware
	in order to acknoledge the interrupt or re-enable
	them (except for the target hardware of course)
	So this code is broken unless set_vector adds an
	additionnal prologue/epilogue before calling/returning
	from in order to acknoledge/mask the raven and the
	8259 PICS... => Anyway already EACH BSP MUST REWRITE
	PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT
	SET_VECTOR.

I would rather offer an API similar to the one provided
in libbsp/i386/shared/irq/irq.h so that :

	1) Once the driver supplied methods is called the
	only things the ISR has to do is to worry about the
	external hardware that triggered the interrupt.
	Everything on openpic/VIA/processor would have been
	done by the low levels (same things as set-vector)
	2) The caller will need to supply the on/off/isOn
	routine that are fundamental to correctly implements
	debuggers/performance monitoring is a portable way
	3) A globally configurable interrupt priorities
	mechanism...

I have nothing against providing a compatible
set_vector just to make libchip happy but
as I have already explained in  other
mails (months ago), I really think that the ISR
connection should be handled by the BSP and that no
code containing irq connection should exist the
rtems generic layers... Thus I really dislike
libchip on this aspect because in a long term
it will force to adopt the less reach API
for interrupt handling that exists (set_vector).

Additional note : I think the _ISR_Is_in_progress()
inline routine should be :

	1) Put in a processor specific section,
	2) Should not rely on a global variable,

As :
	a) on symmetric MP, there is one interrupt level
	per CPU,
	b) On processor that have an ISP (e,g 68040),
	this variable is useless (MSR bit testing could
	be used)
	c) On PPC, instead of using the address of the
	variable via __CPU_IRQ_info.Nest_level a dedicated
	SPR could be used.

NOTE:	most of this is also true for _Thread_Dispatch_disable_level


END NOTE
--------

Please do not take what I said in the mail as a criticism for
anyone who submitted ppc code. Any code present helped me
a lot understanding PPC behavior. I just wanted by this
mail to :
	1) try to better understand the actual code,
	2) propose concrete ways of enhancing current code
	by providing an alternative implementation for MCP750. I
	will make my best effort to try to brake nothing but this
	is actually hard due to the file layout organisation.
	3) make understandable some changes I will probably make
	if joel let me do them :-)

Any comments/objections are welcomed as usual.



--
   __
  /  `                   	Eric Valette
 /--   __  o _.          	Canon CRF
(___, / (_(_(__         	Rue de la touche lambert
				35517 Cesson-Sevigne  Cedex
				FRANCE
Tel: +33 (0)2 99 87 68 91	Fax: +33 (0)2 99 84 11 30
E-mail: valette@crf.canon.fr

27 files changed, 3677 insertions, 2583 deletions

diff --git a/c/src/exec/score/cpu/powerpc/Makefile.in b/c/src/exec/score/cpu/powerpc/Makefile.in
index ba8afaf90e..231f199ef3 100644
--- a/c/src/exec/score/cpu/powerpc/Makefile.in
+++ b/c/src/exec/score/cpu/powerpc/Makefile.in
@@ -1,4 +1,7 @@
 #
+# $Id$
+#
+#	
 #  $Id$
 #
 
@@ -18,8 +21,13 @@ VPATH = @srcdir@
 include $(RTEMS_ROOT)/make/custom/${RTEMS_BSP}.cfg
 include $(RTEMS_ROOT)/make/directory.cfg
 
-SUB_DIRS = rtems wrap
+SHARED_LIB=shared
+
+ifeq ($(RTEMS_CPU_MODEL),mpc750)
+CPUDIR=mpc750
+else
+CPUDIR=other_cpu
+endif
+
+SUB_DIRS=$(CPUDIR) $(SHARED_LIB)
 
-Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
-	cd $(top_builddir) \
-	 && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status
diff --git a/c/src/exec/score/cpu/powerpc/asm.h b/c/src/exec/score/cpu/powerpc/asm.h
new file mode 100644
index 0000000000..af14c95665
--- /dev/null
+++ b/c/src/exec/score/cpu/powerpc/asm.h
@@ -0,0 +1,275 @@
+/*  asm.h
+ *
+ *  This include file attempts to address the problems
+ *  caused by incompatible flavors of assemblers and
+ *  toolsets.  It primarily addresses variations in the
+ *  use of leading underscores on symbols and the requirement
+ *  that register names be preceded by a %.
+ *
+ *
+ *  NOTE: The spacing in the use of these macros
+ *        is critical to them working as advertised.
+ *
+ *  COPYRIGHT:
+ *
+ *  This file is based on similar code found in newlib available
+ *  from ftp.cygnus.com.  The file which was used had no copyright
+ *  notice.  This file is freely distributable as long as the source
+ *  of the file is noted.  This file is:
+ *
+ *  COPYRIGHT (c) 1995.
+ *  i-cubed ltd.
+ *
+ *  COPYRIGHT (c) 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  $Id$
+ */
+
+#ifndef __PPC_ASM_h
+#define __PPC_ASM_h
+
+/*
+ *  Indicate we are in an assembly file and get the basic CPU definitions.
+ */
+
+#ifndef ASM
+#define ASM
+#endif
+#include <rtems/score/targopts.h>
+#include <rtems/score/ppc.h>
+
+/*
+ *  Recent versions of GNU cpp define variables which indicate the
+ *  need for underscores and percents.  If not using GNU cpp or
+ *  the version does not support this, then you will obviously
+ *  have to define these as appropriate.
+ */
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__ 
+#endif
+
+#ifndef __REGISTER_PREFIX__
+#define __REGISTER_PREFIX__
+#endif
+
+#ifndef __FLOAT_REGISTER_PREFIX__
+#define __FLOAT_REGISTER_PREFIX__  __REGISTER_PREFIX__
+#endif
+
+#if (PPC_ABI == PPC_ABI_POWEROPEN)
+#ifndef __PROC_LABEL_PREFIX__
+#define __PROC_LABEL_PREFIX__ .
+#endif
+#endif
+
+#ifndef __PROC_LABEL_PREFIX__
+#define __PROC_LABEL_PREFIX__  __USER_LABEL_PREFIX__
+#endif
+
+/* ANSI concatenation macros.  */
+
+#define CONCAT1(a, b) CONCAT2(a, b)
+#define CONCAT2(a, b) a ## b
+
+/* Use the right prefix for global labels.  */
+
+#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
+
+/* Use the right prefix for procedure labels.  */
+
+#define PROC(x) CONCAT1 (__PROC_LABEL_PREFIX__, x)
+
+/* Use the right prefix for registers.  */
+
+#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
+
+/* Use the right prefix for floating point registers.  */
+
+#define FREG(x) CONCAT1 (__FLOAT_REGISTER_PREFIX__, x)
+
+/*
+ *  define macros for all of the registers on this CPU
+ *
+ *  EXAMPLE:     #define d0 REG (d0)
+ */
+#define r0 REG(0)
+#define r1 REG(1)
+#define r2 REG(2)
+#define r3 REG(3)
+#define r4 REG(4)
+#define r5 REG(5)
+#define r6 REG(6)
+#define r7 REG(7)
+#define r8 REG(8)
+#define r9 REG(9)
+#define r10 REG(10)
+#define r11 REG(11)
+#define r12 REG(12)
+#define r13 REG(13)
+#define r14 REG(14)
+#define r15 REG(15)
+#define r16 REG(16)
+#define r17 REG(17)
+#define r18 REG(18)
+#define r19 REG(19)
+#define r20 REG(20)
+#define r21 REG(21)
+#define r22 REG(22)
+#define r23 REG(23)
+#define r24 REG(24)
+#define r25 REG(25)
+#define r26 REG(26)
+#define r27 REG(27)
+#define r28 REG(28)
+#define r29 REG(29)
+#define r30 REG(30)
+#define r31 REG(31)
+#define f0 FREG(0)
+#define f1 FREG(1)
+#define f2 FREG(2)
+#define f3 FREG(3)
+#define f4 FREG(4)
+#define f5 FREG(5)
+#define f6 FREG(6)
+#define f7 FREG(7)
+#define f8 FREG(8)
+#define f9 FREG(9)
+#define f10 FREG(10)
+#define f11 FREG(11)
+#define f12 FREG(12)
+#define f13 FREG(13)
+#define f14 FREG(14)
+#define f15 FREG(15)
+#define f16 FREG(16)
+#define f17 FREG(17)
+#define f18 FREG(18)
+#define f19 FREG(19)
+#define f20 FREG(20)
+#define f21 FREG(21)
+#define f22 FREG(22)
+#define f23 FREG(23)
+#define f24 FREG(24)
+#define f25 FREG(25)
+#define f26 FREG(26)
+#define f27 FREG(27)
+#define f28 FREG(28)
+#define f29 FREG(29)
+#define f30 FREG(30)
+#define f31 FREG(31)
+
+/*
+ * Some special purpose registers (SPRs).
+ */
+#define srr0	0x01a
+#define srr1	0x01b
+#define srr2	0x3de	/* IBM 400 series only */
+#define srr3	0x3df	/* IBM 400 series only */
+#define sprg0	0x110
+#define sprg1	0x111
+#define sprg2	0x112
+#define sprg3	0x113
+
+
+/* the following SPR/DCR registers exist only in IBM 400 series */
+#define dear	0x3d5	
+#define evpr    0x3d6   /* SPR: exception vector prefix register   */
+#define iccr    0x3fb   /* SPR: instruction cache control reg.     */
+#define dccr    0x3fa   /* SPR: data cache control reg.            */
+
+#define exisr   0x040   /* DCR: external interrupt status register */
+#define exier   0x042   /* DCR: external interrupt enable register */
+#define br0     0x080   /* DCR: memory bank register 0             */
+#define br1     0x081   /* DCR: memory bank register 1             */
+#define br2     0x082   /* DCR: memory bank register 2             */
+#define br3     0x083   /* DCR: memory bank register 3             */
+#define br4     0x084   /* DCR: memory bank register 4             */
+#define br5     0x085   /* DCR: memory bank register 5             */
+#define br6     0x086   /* DCR: memory bank register 6             */
+#define br7     0x087   /* DCR: memory bank register 7             */
+/* end of IBM400 series register definitions */
+
+/* The following registers are for the MPC8x0 */
+#define der     0x095   /* Debug Enable Register */
+/* end of MPC8x0 registers */
+
+/*
+ *  Following must be tailor for a particular flavor of the C compiler.
+ *  They may need to put underscores in front of the symbols.
+ */
+
+#define PUBLIC_VAR(sym) .globl SYM (sym)
+#define EXTERN_VAR(sym) .extern SYM (sym)
+#define PUBLIC_PROC(sym) .globl PROC (sym)
+#define EXTERN_PROC(sym) .extern PROC (sym)
+
+/* Other potentially assembler specific operations */
+#if PPC_ASM == PPC_ASM_ELF
+#define ALIGN(n,p)	.align	p
+#define DESCRIPTOR(x)	\
+	.section .descriptors,"aw";	\
+	PUBLIC_VAR (x);			\
+SYM (x):;				\
+	.long	PROC (x);		\
+	.long	s.got;			\
+	.long	0
+
+#define EXT_SYM_REF(x)	.long x
+#define EXT_PROC_REF(x)	.long x
+
+/*
+ *  Define macros to handle section beginning and ends.
+ */
+
+#define BEGIN_CODE_DCL .text
+#define END_CODE_DCL
+#define BEGIN_DATA_DCL .data
+#define END_DATA_DCL
+#define BEGIN_CODE .text
+#define END_CODE
+#define BEGIN_DATA .data
+#define END_DATA
+#define BEGIN_BSS  .bss
+#define END_BSS
+#define END
+
+#elif PPC_ASM == PPC_ASM_XCOFF
+#define ALIGN(n,p)	.align	p
+#define DESCRIPTOR(x)	\
+	.csect	x[DS];		\
+	.globl	x[DS];		\
+	.long	PROC (x)[PR];	\
+	.long	TOC[tc0]
+
+#define EXT_SYM_REF(x)	.long x[RW]
+#define EXT_PROC_REF(x)	.long x[DS]
+
+/*
+ *  Define macros to handle section beginning and ends.
+ */
+
+#define BEGIN_CODE_DCL .csect .text[PR]
+#define END_CODE_DCL
+#define BEGIN_DATA_DCL .csect .data[RW]
+#define END_DATA_DCL
+#define BEGIN_CODE .csect .text[PR]
+#define END_CODE
+#define BEGIN_DATA .csect .data[RW]
+#define END_DATA
+#define BEGIN_BSS  .bss
+#define END_BSS
+#define END
+
+#else
+#error "PPC_ASM_TYPE is not properly defined"
+#endif
+#ifndef PPC_ASM
+#error "PPC_ASM_TYPE is not properly defined"
+#endif
+
+
+#endif
+/* end of include file */
+
+
diff --git a/c/src/exec/score/cpu/powerpc/mpc750/Makefile.in b/c/src/exec/score/cpu/powerpc/mpc750/Makefile.in
new file mode 100644
index 0000000000..f50d88ca4d
--- /dev/null
+++ b/c/src/exec/score/cpu/powerpc/mpc750/Makefile.in
@@ -0,0 +1,83 @@
+#
+# $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+top_srcdir = @top_srcdir@
+top_builddir = ../../../../../../..
+subdir = c/src/exec/score/cpu/powerpc/wrap
+
+INSTALL = @INSTALL@
+
+RTEMS_ROOT = $(top_srcdir)/@RTEMS_TOPdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+VPATH = @srcdir@
+
+RELS=../$(ARCH)/rtems-cpu.rel
+
+# C source names, if any, go here -- minus the .c
+C_PIECES = cpu
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+ROOT_H_PIECES =
+ROOT_H_FILES=$(ROOT_H_PIECES:%=$(srcdir)/%)
+RTEMS_SCORE_H_PIECES=cpu.h
+RTEMS_SCORE_H_FILES=$(RTEMS_SCORE_H_PIECES:%=$(srcdir)/%)
+H_PIECES=$(ROOT_H_PIECES) $(RTEMS_SCORE_H_PIECES)
+H_FILES=$(H_PIECES%=$(srcdir)/%)
+I_PIECES= c_isr
+I_FILES=$(I_PIECES:%=$(srcdir)/%.inl)
+
+# Assembly source names, if any, go here -- minus the .S
+S_PIECES = cpu_asm 
+S_FILES=$(S_PIECES:%=%.S)
+S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
+
+SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES) $(I_FILES)
+OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/${RTEMS_BSP}.cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS += 
+CFLAGS   += $(CFLAGS_OS_V)
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS += 
+CLOBBER_ADDITIONS +=
+
+../$(ARCH)/rtems-cpu.rel: $(OBJS)
+	test -d ../$(ARCH) || mkdir ../$(ARCH)
+	$(make-rel)
+
+all:    ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
+
+# Install the program(s), appending _g or _p as appropriate.
+# for include files, just use $(INSTALL_CHANGE)
+install:  all
+
+preinstall: ${ARCH}
+	$(INSTALL_CHANGE) -m 444 ${RTEMS_SCORE_H_FILES} ${I_FILES} $(PROJECT_INCLUDE)/rtems/score
+	$(INSTALL_CHANGE) -m 444 ${ROOT_H_FILES} $(PROJECT_INCLUDE)
+
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+	cd $(top_builddir) \
+	 && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status
diff --git a/c/src/exec/score/cpu/powerpc/mpc750/c_isr.inl b/c/src/exec/score/cpu/powerpc/mpc750/c_isr.inl
new file mode 100644
index 0000000000..68f8116fe9
--- /dev/null
+++ b/c/src/exec/score/cpu/powerpc/mpc750/c_isr.inl
@@ -0,0 +1,9 @@
+RTEMS_INLINE_ROUTINE boolean _ISR_Is_in_progress( void )
+{
+	register unsigned int isr_nesting_level;
+	/*
+         * Move from special purpose register 0 (mfspr SPRG0, r3)
+	 */
+	asm volatile ("mfspr	%0, 272" : "=r" (isr_nesting_level));
+	return isr_nesting_level;
+}
diff --git a/c/src/exec/score/cpu/powerpc/mpc750/cpu.c b/c/src/exec/score/cpu/powerpc/mpc750/cpu.c
new file mode 100644
index 0000000000..b675f9e417
--- /dev/null
+++ b/c/src/exec/score/cpu/powerpc/mpc750/cpu.c
@@ -0,0 +1,118 @@
+/*
+ *  PowerPC CPU Dependent Source
+ *
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/cpu/no_cpu/cpu.c:
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be found in
+ *  the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/context.h>
+#include <rtems/score/thread.h>
+#include <rtems/score/interr.h>
+
+
+/*  _CPU_Initialize
+ *
+ *  This routine performs processor dependent initialization.
+ *
+ *  INPUT PARAMETERS:
+ *    cpu_table       - CPU table to initialize
+ *    thread_dispatch - address of disptaching routine
+ */
+
+void _CPU_Initialize(
+  rtems_cpu_table  *cpu_table,
+  void      (*thread_dispatch)      /* ignored on this CPU */
+)
+{
+  _CPU_Table = *cpu_table;
+}
+
+/*PAGE
+ *
+ *  _CPU_Context_Initialize
+ */
+
+#define CPU_MINIMUM_STACK_FRAME_SIZE 8
+
+void _CPU_Context_Initialize(
+  Context_Control  *the_context,
+  unsigned32       *stack_base,
+  unsigned32        size,
+  unsigned32        new_level,
+  void             *entry_point,
+  boolean           is_fp
+)
+{
+  unsigned32 msr_value;
+  unsigned32 sp;
+
+  sp = (unsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
+  *((unsigned32 *)sp) = 0;
+  the_context->gpr1 = sp;
+   
+  _CPU_MSR_GET( msr_value );
+
+  if (!(new_level & CPU_MODES_INTERRUPT_MASK)) {
+    msr_value |= MSR_EE;
+  }
+  else {
+    msr_value &= ~MSR_EE;
+  }
+
+  the_context->msr = msr_value;
+
+  /*
+   *  The FP bit of the MSR should only be enabled if this is a floating
+   *  point task.  Unfortunately, the vfprintf_r routine in newlib 
+   *  ends up pushing a floating point register regardless of whether or
+   *  not a floating point number is being printed.  Serious restructuring
+   *  of vfprintf.c will be required to avoid this behavior.  At this
+   *  time (7 July 1997), this restructuring is not being done.
+   */
+
+  /*if ( is_fp ) */
+    the_context->msr |= PPC_MSR_FP;
+
+  the_context->pc = (unsigned32)entry_point;
+}
+
+
+
+/*PAGE
+ *
+ *  _CPU_Install_interrupt_stack
+ */
+
+void _CPU_Install_interrupt_stack( void )
+{
+}
+
+
+
+
diff --git a/c/src/exec/score/cpu/powerpc/mpc750/cpu.h b/c/src/exec/score/cpu/powerpc/mpc750/cpu.h
new file mode 100644
index 0000000000..e3ea78eb82
--- /dev/null
+++ b/c/src/exec/score/cpu/powerpc/mpc750/cpu.h
@@ -0,0 +1,948 @@
+/*  cpu.h
+ *
+ *  This include file contains information pertaining to the PowerPC
+ *  processor.
+ *
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/cpu/no_cpu/cpu.h:
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be found in
+ *  the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __CPU_h
+#define __CPU_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems/score/ppc.h>               /* pick up machine definitions */
+#include <libcpu/cpu.h>
+  
+#ifndef ASM
+#include <rtems/score/ppctypes.h>
+#endif
+
+/* conditional compilation parameters */
+
+/*
+ *  Should the calls to _Thread_Enable_dispatch be inlined?
+ *
+ *  If TRUE, then they are inlined.
+ *  If FALSE, then a subroutine call is made.
+ *
+ *  Basically this is an example of the classic trade-off of size
+ *  versus speed.  Inlining the call (TRUE) typically increases the
+ *  size of RTEMS while speeding up the enabling of dispatching.
+ *  [NOTE: In general, the _Thread_Dispatch_disable_level will
+ *  only be 0 or 1 unless you are in an interrupt handler and that
+ *  interrupt handler invokes the executive.]  When not inlined
+ *  something calls _Thread_Enable_dispatch which in turns calls
+ *  _Thread_Dispatch.  If the enable dispatch is inlined, then
+ *  one subroutine call is avoided entirely.]
+ */
+
+#define CPU_INLINE_ENABLE_DISPATCH       FALSE
+
+/*
+ *  Should the body of the search loops in _Thread_queue_Enqueue_priority
+ *  be unrolled one time?  In unrolled each iteration of the loop examines
+ *  two "nodes" on the chain being searched.  Otherwise, only one node
+ *  is examined per iteration.
+ *
+ *  If TRUE, then the loops are unrolled.
+ *  If FALSE, then the loops are not unrolled.
+ *
+ *  The primary factor in making this decision is the cost of disabling
+ *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
+ *  body of the loop.  On some CPUs, the flash is more expensive than
+ *  one iteration of the loop body.  In this case, it might be desirable
+ *  to unroll the loop.  It is important to note that on some CPUs, this
+ *  code is the longest interrupt disable period in RTEMS.  So it is
+ *  necessary to strike a balance when setting this parameter.
+ */
+
+#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
+
+/*
+ *  Does RTEMS manage a dedicated interrupt stack in software?
+ *
+ *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
+ *  If FALSE, nothing is done.
+ *
+ *  If the CPU supports a dedicated interrupt stack in hardware,
+ *  then it is generally the responsibility of the BSP to allocate it
+ *  and set it up.
+ *
+ *  If the CPU does not support a dedicated interrupt stack, then
+ *  the porter has two options: (1) execute interrupts on the
+ *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
+ *  interrupt stack.
+ *
+ *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ *
+ *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ *  possible that both are FALSE for a particular CPU.  Although it
+ *  is unclear what that would imply about the interrupt processing
+ *  procedure on that CPU.
+ */
+
+#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
+
+/*
+ *  Does this CPU have hardware support for a dedicated interrupt stack?
+ *
+ *  If TRUE, then it must be installed during initialization.
+ *  If FALSE, then no installation is performed.
+ *
+ *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ *
+ *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ *  possible that both are FALSE for a particular CPU.  Although it
+ *  is unclear what that would imply about the interrupt processing
+ *  procedure on that CPU.
+ */
+
+#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
+
+/*
+ *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
+ *
+ *  If TRUE, then the memory is allocated during initialization.
+ *  If FALSE, then the memory is allocated during initialization.
+ *
+ *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
+ *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
+ */
+
+#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
+
+/*
+ *  Does the RTEMS invoke the user's ISR with the vector number and
+ *  a pointer to the saved interrupt frame (1) or just the vector 
+ *  number (0)?
+ */
+
+#define CPU_ISR_PASSES_FRAME_POINTER 0
+
+/*
+ *  Does the CPU have hardware floating point?
+ *
+ *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
+ *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
+ *
+ *  If there is a FP coprocessor such as the i387 or mc68881, then
+ *  the answer is TRUE.
+ *
+ *  The macro name "PPC_HAS_FPU" should be made CPU specific.
+ *  It indicates whether or not this CPU model has FP support.  For
+ *  example, it would be possible to have an i386_nofp CPU model
+ *  which set this to false to indicate that you have an i386 without
+ *  an i387 and wish to leave floating point support out of RTEMS.
+ */
+
+#if ( PPC_HAS_FPU == 1 )
+#define CPU_HARDWARE_FP     TRUE
+#else
+#define CPU_HARDWARE_FP     FALSE
+#endif
+
+/*
+ *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
+ *
+ *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
+ *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
+ *
+ *  So far, the only CPU in which this option has been used is the
+ *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
+ *  floating point registers to perform integer multiplies.  If
+ *  a function which you would not think utilize the FP unit DOES,
+ *  then one can not easily predict which tasks will use the FP hardware.
+ *  In this case, this option should be TRUE.
+ *
+ *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ */
+
+#define CPU_ALL_TASKS_ARE_FP     FALSE
+
+/*
+ *  Should the IDLE task have a floating point context?
+ *
+ *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
+ *  and it has a floating point context which is switched in and out.
+ *  If FALSE, then the IDLE task does not have a floating point context.
+ *
+ *  Setting this to TRUE negatively impacts the time required to preempt
+ *  the IDLE task from an interrupt because the floating point context
+ *  must be saved as part of the preemption.
+ */
+
+#define CPU_IDLE_TASK_IS_FP      FALSE
+
+/*
+ *  Should the saving of the floating point registers be deferred
+ *  until a context switch is made to another different floating point
+ *  task?
+ *
+ *  If TRUE, then the floating point context will not be stored until
+ *  necessary.  It will remain in the floating point registers and not
+ *  disturned until another floating point task is switched to.
+ *
+ *  If FALSE, then the floating point context is saved when a floating
+ *  point task is switched out and restored when the next floating point
+ *  task is restored.  The state of the floating point registers between
+ *  those two operations is not specified.
+ *
+ *  If the floating point context does NOT have to be saved as part of
+ *  interrupt dispatching, then it should be safe to set this to TRUE.
+ *
+ *  Setting this flag to TRUE results in using a different algorithm
+ *  for deciding when to save and restore the floating point context.
+ *  The deferred FP switch algorithm minimizes the number of times
+ *  the FP context is saved and restored.  The FP context is not saved
+ *  until a context switch is made to another, different FP task.
+ *  Thus in a system with only one FP task, the FP context will never
+ *  be saved or restored.
+ */
+/*
+ *  ACB Note:  This could make debugging tricky..
+ */
+
+#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
+
+/*
+ *  Does this port provide a CPU dependent IDLE task implementation?
+ *
+ *  If TRUE, then the routine _CPU_Thread_Idle_body
+ *  must be provided and is the default IDLE thread body instead of
+ *  _CPU_Thread_Idle_body.
+ *
+ *  If FALSE, then use the generic IDLE thread body if the BSP does
+ *  not provide one.
+ *
+ *  This is intended to allow for supporting processors which have
+ *  a low power or idle mode.  When the IDLE thread is executed, then
+ *  the CPU can be powered down.
+ *
+ *  The order of precedence for selecting the IDLE thread body is:
+ *
+ *    1.  BSP provided
+ *    2.  CPU dependent (if provided)
+ *    3.  generic (if no BSP and no CPU dependent)
+ */
+
+#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
+
+/*
+ *  Does the stack grow up (toward higher addresses) or down
+ *  (toward lower addresses)?
+ *
+ *  If TRUE, then the grows upward.
+ *  If FALSE, then the grows toward smaller addresses.
+ */
+
+#define CPU_STACK_GROWS_UP               FALSE
+
+/*
+ *  The following is the variable attribute used to force alignment
+ *  of critical RTEMS structures.  On some processors it may make
+ *  sense to have these aligned on tighter boundaries than
+ *  the minimum requirements of the compiler in order to have as
+ *  much of the critical data area as possible in a cache line.
+ *
+ *  The placement of this macro in the declaration of the variables
+ *  is based on the syntactically requirements of the GNU C
+ *  "__attribute__" extension.  For example with GNU C, use
+ *  the following to force a structures to a 32 byte boundary.
+ *
+ *      __attribute__ ((aligned (32)))
+ *
+ *  NOTE:  Currently only the Priority Bit Map table uses this feature.
+ *         To benefit from using this, the data must be heavily
+ *         used so it will stay in the cache and used frequently enough
+ *         in the executive to justify turning this on.
+ */
+
+#define CPU_STRUCTURE_ALIGNMENT \
+  __attribute__ ((aligned (PPC_CACHE_ALIGNMENT)))
+
+/*
+ *  Define what is required to specify how the network to host conversion
+ *  routines are handled.
+ */
+
+#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
+#define CPU_BIG_ENDIAN                           TRUE
+#define CPU_LITTLE_ENDIAN                        FALSE
+
+
+/*
+ *  Processor defined structures
+ *
+ *  Examples structures include the descriptor tables from the i386
+ *  and the processor control structure on the i960ca.
+ */
+
+/* may need to put some structures here.  */
+
+/*
+ * Contexts
+ *
+ *  Generally there are 2 types of context to save.
+ *     1. Interrupt registers to save
+ *     2. Task level registers to save
+ *
+ *  This means we have the following 3 context items:
+ *     1. task level context stuff::  Context_Control
+ *     2. floating point task stuff:: Context_Control_fp
+ *     3. special interrupt level context :: Context_Control_interrupt
+ *
+ *  On some processors, it is cost-effective to save only the callee
+ *  preserved registers during a task context switch.  This means
+ *  that the ISR code needs to save those registers which do not
+ *  persist across function calls.  It is not mandatory to make this
+ *  distinctions between the caller/callee saves registers for the
+ *  purpose of minimizing context saved during task switch and on interrupts.
+ *  If the cost of saving extra registers is minimal, simplicity is the
+ *  choice.  Save the same context on interrupt entry as for tasks in
+ *  this case.
+ *
+ *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
+ *  care should be used in designing the context area.
+ *
+ *  On some CPUs with hardware floating point support, the Context_Control_fp
+ *  structure will not be used or it simply consist of an array of a
+ *  fixed number of bytes.   This is done when the floating point context
+ *  is dumped by a "FP save context" type instruction and the format
+ *  is not really defined by the CPU.  In this case, there is no need
+ *  to figure out the exact format -- only the size.  Of course, although
+ *  this is enough information for RTEMS, it is probably not enough for
+ *  a debugger such as gdb.  But that is another problem.
+ */
+
+typedef struct {
+    unsigned32 gpr1;	/* Stack pointer for all */
+    unsigned32 gpr2;	/* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
+    unsigned32 gpr13;	/* First non volatile PowerOpen, section ptr SVR4/EABI */
+    unsigned32 gpr14;	/* Non volatile for all */
+    unsigned32 gpr15;	/* Non volatile for all */
+    unsigned32 gpr16;	/* Non volatile for all */
+    unsigned32 gpr17;	/* Non volatile for all */
+    unsigned32 gpr18;	/* Non volatile for all */
+    unsigned32 gpr19;	/* Non volatile for all */
+    unsigned32 gpr20;	/* Non volatile for all */
+    unsigned32 gpr21;	/* Non volatile for all */
+    unsigned32 gpr22;	/* Non volatile for all */
+    unsigned32 gpr23;	/* Non volatile for all */
+    unsigned32 gpr24;	/* Non volatile for all */
+    unsigned32 gpr25;	/* Non volatile for all */
+    unsigned32 gpr26;	/* Non volatile for all */
+    unsigned32 gpr27;	/* Non volatile for all */
+    unsigned32 gpr28;	/* Non volatile for all */
+    unsigned32 gpr29;	/* Non volatile for all */
+    unsigned32 gpr30;	/* Non volatile for all */
+    unsigned32 gpr31;	/* Non volatile for all */
+    unsigned32 cr;	/* PART of the CR is non volatile for all */
+    unsigned32 pc;	/* Program counter/Link register */
+    unsigned32 msr;	/* Initial interrupt level */
+} Context_Control;
+
+typedef struct {
+    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
+     * procedure calls.  However, this would mean that the interrupt
+     * frame had to hold f0-f13, and the fpscr.  And as the majority
+     * of tasks will not have an FP context, we will save the whole
+     * context here.
+     */
+#if (PPC_HAS_DOUBLE == 1)
+    double	f[32];
+    double	fpscr;
+#else
+    float	f[32];
+    float	fpscr;
+#endif
+} Context_Control_fp;
+
+typedef struct CPU_Interrupt_frame {
+    unsigned32 stacklink;	/* Ensure this is a real frame (also reg1 save) */
+    unsigned32 calleeLr;	/* link register used by callees: SVR4/EABI */
+  /* This is what is left out of the primary contexts */
+    unsigned32 gpr0;
+    unsigned32 gpr2;		/* play safe */
+    unsigned32 gpr3;
+    unsigned32 gpr4;
+    unsigned32 gpr5;
+    unsigned32 gpr6;
+    unsigned32 gpr7;
+    unsigned32 gpr8;
+    unsigned32 gpr9;
+    unsigned32 gpr10;
+    unsigned32 gpr11;
+    unsigned32 gpr12;
+    unsigned32 gpr13;   /* Play safe */
+    unsigned32 gpr28;   /* For internal use by the IRQ handler */
+    unsigned32 gpr29;   /* For internal use by the IRQ handler */
+    unsigned32 gpr30;   /* For internal use by the IRQ handler */
+    unsigned32 gpr31;   /* For internal use by the IRQ handler */
+    unsigned32 cr;	/* Bits of this are volatile, so no-one may save */
+    unsigned32 ctr;
+    unsigned32 xer;
+    unsigned32 lr;
+    unsigned32 pc;
+    unsigned32 msr;
+    unsigned32 pad[3];
+} CPU_Interrupt_frame;
+  
+/*
+ *  The following table contains the information required to configure
+ *  the PowerPC processor specific parameters.
+ */
+
+typedef struct {
+  void       (*pretasking_hook)( void );
+  void       (*predriver_hook)( void );
+  void       (*postdriver_hook)( void );
+  void       (*idle_task)( void );
+  boolean      do_zero_of_workspace;
+  unsigned32   idle_task_stack_size;
+  unsigned32   interrupt_stack_size;
+  unsigned32   extra_mpci_receive_server_stack;
+  void *     (*stack_allocate_hook)( unsigned32 );
+  void       (*stack_free_hook)( void* );
+  /* end of fields required on all CPUs */
+
+  unsigned32   clicks_per_usec;	       /* Timer clicks per microsecond */
+  boolean      exceptions_in_RAM;     /* TRUE if in RAM */
+
+}   rtems_cpu_table;
+
+/*
+ *  This variable is optional.  It is used on CPUs on which it is difficult
+ *  to generate an "uninitialized" FP context.  It is filled in by
+ *  _CPU_Initialize and copied into the task's FP context area during
+ *  _CPU_Context_Initialize.
+ */
+
+/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
+
+/*
+ *  On some CPUs, RTEMS supports a software managed interrupt stack.
+ *  This stack is allocated by the Interrupt Manager and the switch
+ *  is performed in _ISR_Handler.  These variables contain pointers
+ *  to the lowest and highest addresses in the chunk of memory allocated
+ *  for the interrupt stack.  Since it is unknown whether the stack
+ *  grows up or down (in general), this give the CPU dependent
+ *  code the option of picking the version it wants to use.
+ *
+ *  NOTE: These two variables are required if the macro
+ *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
+ */
+
+SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
+SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
+
+/*
+ *  This defines the number of levels and the mask used to pick those
+ *  bits out of a thread mode.
+ */
+
+#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
+#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
+
+/*
+ *  With some compilation systems, it is difficult if not impossible to
+ *  call a high-level language routine from assembly language.  This
+ *  is especially true of commercial Ada compilers and name mangling
+ *  C++ ones.  This variable can be optionally defined by the CPU porter
+ *  and contains the address of the routine _Thread_Dispatch.  This
+ *  can make it easier to invoke that routine at the end of the interrupt
+ *  sequence (if a dispatch is necessary).
+ */
+
+/* EXTERN void           (*_CPU_Thread_dispatch_pointer)(); */
+
+/*
+ *  Nothing prevents the porter from declaring more CPU specific variables.
+ */
+
+
+SCORE_EXTERN struct {
+  unsigned32 *Disable_level;
+  void *Stack;
+  volatile boolean *Switch_necessary;
+  boolean *Signal;
+
+} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
+
+/*
+ *  The size of the floating point context area.  On some CPUs this
+ *  will not be a "sizeof" because the format of the floating point
+ *  area is not defined -- only the size is.  This is usually on
+ *  CPUs with a "floating point save context" instruction.
+ */
+
+#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
+
+/*
+ * (Optional) # of bytes for libmisc/stackchk to check
+ * If not specifed, then it defaults to something reasonable
+ * for most architectures.
+ */
+
+#define CPU_STACK_CHECK_SIZE    (128)
+
+/*
+ *  Amount of extra stack (above minimum stack size) required by
+ *  MPCI receive server thread.  Remember that in a multiprocessor
+ *  system this thread must exist and be able to process all directives.
+ */
+
+#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
+
+/*
+ *  This defines the number of entries in the ISR_Vector_table managed
+ *  by RTEMS.
+ */
+
+#define CPU_INTERRUPT_NUMBER_OF_VECTORS     (PPC_INTERRUPT_MAX)
+#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1)
+
+/*
+ *  Should be large enough to run all RTEMS tests.  This insures
+ *  that a "reasonable" small application should not have any problems.
+ */
+
+#define CPU_STACK_MINIMUM_SIZE          (1024*3)
+
+/*
+ *  CPU's worst alignment requirement for data types on a byte boundary.  This
+ *  alignment does not take into account the requirements for the stack.
+ */
+
+#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
+
+/*
+ *  This number corresponds to the byte alignment requirement for the
+ *  heap handler.  This alignment requirement may be stricter than that
+ *  for the data types alignment specified by CPU_ALIGNMENT.  It is
+ *  common for the heap to follow the same alignment requirement as
+ *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
+ *  then this should be set to CPU_ALIGNMENT.
+ *
+ *  NOTE:  This does not have to be a power of 2.  It does have to
+ *         be greater or equal to than CPU_ALIGNMENT.
+ */
+
+#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
+
+/*
+ *  This number corresponds to the byte alignment requirement for memory
+ *  buffers allocated by the partition manager.  This alignment requirement
+ *  may be stricter than that for the data types alignment specified by
+ *  CPU_ALIGNMENT.  It is common for the partition to follow the same
+ *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
+ *  enough for the partition, then this should be set to CPU_ALIGNMENT.
+ *
+ *  NOTE:  This does not have to be a power of 2.  It does have to
+ *         be greater or equal to than CPU_ALIGNMENT.
+ */
+
+#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
+
+/*
+ *  This number corresponds to the byte alignment requirement for the
+ *  stack.  This alignment requirement may be stricter than that for the
+ *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
+ *  is strict enough for the stack, then this should be set to 0.
+ *
+ *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
+ */
+
+#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
+
+/* ISR handler macros */
+
+/*
+ *  Disable all interrupts for an RTEMS critical section.  The previous
+ *  level is returned in _isr_cookie.
+ */
+
+#define loc_string(a,b)	a " (" #b ")\n"
+
+  
+static inline unsigned32 _CPU_ISR_Get_level( void )
+{
+  register unsigned int msr;
+  _CPU_MSR_GET(msr);
+  if (msr & MSR_EE) return 0;
+  else	return 1;
+}
+
+static inline void _CPU_ISR_Set_level( unsigned32 level )
+{
+  register unsigned int msr;
+  _CPU_MSR_GET(msr);
+  if (!(level & CPU_MODES_INTERRUPT_MASK)) {
+    msr |= MSR_EE;
+  }
+  else {
+    msr &= ~MSR_EE;
+  }
+  _CPU_MSR_SET(msr);
+}
+  
+#define _CPU_ISR_install_vector(irq, new, old) {BSP_panic("_CPU_ISR_install_vector called\n");}
+
+/* Context handler macros */
+
+/*
+ *  Initialize the context to a state suitable for starting a
+ *  task after a context restore operation.  Generally, this
+ *  involves:
+ *
+ *     - setting a starting address
+ *     - preparing the stack
+ *     - preparing the stack and frame pointers
+ *     - setting the proper interrupt level in the context
+ *     - initializing the floating point context
+ *
+ *  This routine generally does not set any unnecessary register
+ *  in the context.  The state of the "general data" registers is
+ *  undefined at task start time.
+ *
+ *  NOTE:  Implemented as a subroutine for the SPARC port.
+ */
+
+void _CPU_Context_Initialize(
+  Context_Control  *the_context,
+  unsigned32       *stack_base,
+  unsigned32        size,
+  unsigned32        new_level,
+  void             *entry_point,
+  boolean           is_fp
+);
+
+/*
+ *  This routine is responsible for somehow restarting the currently
+ *  executing task.  If you are lucky, then all that is necessary
+ *  is restoring the context.  Otherwise, there will need to be
+ *  a special assembly routine which does something special in this
+ *  case.  Context_Restore should work most of the time.  It will
+ *  not work if restarting self conflicts with the stack frame
+ *  assumptions of restoring a context.
+ */
+
+#define _CPU_Context_Restart_self( _the_context ) \
+   _CPU_Context_restore( (_the_context) );
+
+/*
+ *  The purpose of this macro is to allow the initial pointer into
+ *  a floating point context area (used to save the floating point
+ *  context) to be at an arbitrary place in the floating point
+ *  context area.
+ *
+ *  This is necessary because some FP units are designed to have
+ *  their context saved as a stack which grows into lower addresses.
+ *  Other FP units can be saved by simply moving registers into offsets
+ *  from the base of the context area.  Finally some FP units provide
+ *  a "dump context" instruction which could fill in from high to low
+ *  or low to high based on the whim of the CPU designers.
+ */
+
+#define _CPU_Context_Fp_start( _base, _offset ) \
+   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
+
+/*
+ *  This routine initializes the FP context area passed to it to.
+ *  There are a few standard ways in which to initialize the
+ *  floating point context.  The code included for this macro assumes
+ *  that this is a CPU in which a "initial" FP context was saved into
+ *  _CPU_Null_fp_context and it simply copies it to the destination
+ *  context passed to it.
+ *
+ *  Other models include (1) not doing anything, and (2) putting
+ *  a "null FP status word" in the correct place in the FP context.
+ */
+
+#define _CPU_Context_Initialize_fp( _destination ) \
+  { \
+   ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \
+  }
+
+/* end of Context handler macros */
+
+/* Fatal Error manager macros */
+
+/*
+ *  This routine copies _error into a known place -- typically a stack
+ *  location or a register, optionally disables interrupts, and
+ *  halts/stops the CPU.
+ */
+
+#define _CPU_Fatal_halt( _error ) \
+  _BSP_Fatal_error(_error)
+
+/* end of Fatal Error manager macros */
+
+/* Bitfield handler macros */
+
+/*
+ *  This routine sets _output to the bit number of the first bit
+ *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
+ *  This type may be either 16 or 32 bits wide although only the 16
+ *  least significant bits will be used.
+ *
+ *  There are a number of variables in using a "find first bit" type
+ *  instruction.
+ *
+ *    (1) What happens when run on a value of zero?
+ *    (2) Bits may be numbered from MSB to LSB or vice-versa.
+ *    (3) The numbering may be zero or one based.
+ *    (4) The "find first bit" instruction may search from MSB or LSB.
+ *
+ *  RTEMS guarantees that (1) will never happen so it is not a concern.
+ *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
+ *  _CPU_Priority_Bits_index().  These three form a set of routines
+ *  which must logically operate together.  Bits in the _value are
+ *  set and cleared based on masks built by _CPU_Priority_mask().
+ *  The basic major and minor values calculated by _Priority_Major()
+ *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
+ *  to properly range between the values returned by the "find first bit"
+ *  instruction.  This makes it possible for _Priority_Get_highest() to
+ *  calculate the major and directly index into the minor table.
+ *  This mapping is necessary to ensure that 0 (a high priority major/minor)
+ *  is the first bit found.
+ *
+ *  This entire "find first bit" and mapping process depends heavily
+ *  on the manner in which a priority is broken into a major and minor
+ *  components with the major being the 4 MSB of a priority and minor
+ *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
+ *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
+ *  to the lowest priority.
+ *
+ *  If your CPU does not have a "find first bit" instruction, then
+ *  there are ways to make do without it.  Here are a handful of ways
+ *  to implement this in software:
+ *
+ *    - a series of 16 bit test instructions
+ *    - a "binary search using if's"
+ *    - _number = 0
+ *      if _value > 0x00ff
+ *        _value >>=8
+ *        _number = 8;
+ *
+ *      if _value > 0x0000f
+ *        _value >=8
+ *        _number += 4
+ *
+ *      _number += bit_set_table[ _value ]
+ *
+ *    where bit_set_table[ 16 ] has values which indicate the first
+ *      bit set
+ */
+
+#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
+  { \
+    asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
+		  "1" ((_value))); \
+  }
+
+/* end of Bitfield handler macros */
+
+/*
+ *  This routine builds the mask which corresponds to the bit fields
+ *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
+ *  for that routine.
+ */
+
+#define _CPU_Priority_Mask( _bit_number ) \
+  ( 0x80000000 >> (_bit_number) )
+
+/*
+ *  This routine translates the bit numbers returned by
+ *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
+ *  a major or minor component of a priority.  See the discussion
+ *  for that routine.
+ */
+
+#define _CPU_Priority_bits_index( _priority ) \
+  (_priority)
+
+/* end of Priority handler macros */
+
+/* variables */
+
+extern const unsigned32 _CPU_msrs[4];
+
+/* functions */
+
+/*
+ *  _CPU_Initialize
+ *
+ *  This routine performs CPU dependent initialization.
+ */
+
+void _CPU_Initialize(
+  rtems_cpu_table  *cpu_table,
+  void            (*thread_dispatch)
+);
+
+
+/*
+ *  _CPU_Install_interrupt_stack
+ *
+ *  This routine installs the hardware interrupt stack pointer.
+ *
+ *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
+ *         is TRUE.
+ */
+
+void _CPU_Install_interrupt_stack( void );
+
+/*
+ *  _CPU_Context_switch
+ *
+ *  This routine switches from the run context to the heir context.
+ */
+
+void _CPU_Context_switch(
+  Context_Control  *run,
+  Context_Control  *heir
+);
+
+/*
+ *  _CPU_Context_restore
+ *
+ *  This routine is generallu used only to restart self in an
+ *  efficient manner.  It may simply be a label in _CPU_Context_switch.
+ *
+ *  NOTE: May be unnecessary to reload some registers.
+ */
+
+void _CPU_Context_restore(
+  Context_Control *new_context
+);
+
+/*
+ *  _CPU_Context_save_fp
+ *
+ *  This routine saves the floating point context passed to it.
+ */
+
+void _CPU_Context_save_fp(
+  void **fp_context_ptr
+);
+
+/*
+ *  _CPU_Context_restore_fp
+ *
+ *  This routine restores the floating point context passed to it.
+ */
+
+void _CPU_Context_restore_fp(
+  void **fp_context_ptr
+);
+
+void _CPU_Fatal_error(
+  unsigned32 _error
+);
+
+/*  The following routine swaps the endian format of an unsigned int.
+ *  It must be static because it is referenced indirectly.
+ *
+ *  This version will work on any processor, but if there is a better
+ *  way for your CPU PLEASE use it.  The most common way to do this is to:
+ *
+ *     swap least significant two bytes with 16-bit rotate
+ *     swap upper and lower 16-bits
+ *     swap most significant two bytes with 16-bit rotate
+ *
+ *  Some CPUs have special instructions which swap a 32-bit quantity in
+ *  a single instruction (e.g. i486).  It is probably best to avoid
+ *  an "endian swapping control bit" in the CPU.  One good reason is
+ *  that interrupts would probably have to be disabled to insure that
+ *  an interrupt does not try to access the same "chunk" with the wrong
+ *  endian.  Another good reason is that on some CPUs, the endian bit
+ *  endianness for ALL fetches -- both code and data -- so the code
+ *  will be fetched incorrectly.
+ */
+ 
+static inline unsigned int CPU_swap_u32(
+  unsigned int value
+)
+{
+  unsigned32 swapped;
+ 
+  asm volatile("rlwimi %0,%1,8,24,31;"
+	       "rlwimi %0,%1,24,16,23;"
+	       "rlwimi %0,%1,8,8,15;"
+	       "rlwimi %0,%1,24,0,7;" :
+	       "=&r" ((swapped)) : "r" ((value)));
+
+  return( swapped );
+}
+
+#define CPU_swap_u16( value ) \
+  (((value&0xff) << 8) | ((value >> 8)&0xff))
+
+/*
+ *  Routines to access the decrementer register
+ */
+
+#define PPC_Set_decrementer( _clicks ) \
+  do { \
+    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
+  } while (0)
+
+/*
+ *  Routines to access the time base register
+ */
+
+static inline unsigned64 PPC_Get_timebase_register( void )
+{
+  unsigned32 tbr_low;
+  unsigned32 tbr_high;
+  unsigned32 tbr_high_old;
+  unsigned64 tbr;
+
+  do {
+    asm volatile( "mftbu %0" : "=r" (tbr_high_old));
+    asm volatile( "mftb  %0" : "=r" (tbr_low));
+    asm volatile( "mftbu %0" : "=r" (tbr_high));
+  } while ( tbr_high_old != tbr_high );
+
+  tbr = tbr_high;
+  tbr <<= 32;
+  tbr |= tbr_low;
+  return tbr;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/exec/score/cpu/powerpc/mpc750/cpu_asm.S b/c/src/exec/score/cpu/powerpc/mpc750/cpu_asm.S
new file mode 100644
index 0000000000..213e094fa6
--- /dev/null
+++ b/c/src/exec/score/cpu/powerpc/mpc750/cpu_asm.S
@@ -0,0 +1,396 @@
+
+/*  cpu_asm.s	1.1 - 95/12/04
+ *
+ *  This file contains the assembly code for the PowerPC implementation
+ *  of RTEMS.
+ *
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/cpu/no_cpu/cpu_asm.c:
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#include <asm.h>
+
+/*
+ * Offsets for various Contexts
+ */
+	.set	GP_1, 0
+	.set	GP_2, (GP_1 + 4)
+	.set	GP_13, (GP_2 + 4)
+	.set	GP_14, (GP_13 + 4)
+
+	.set	GP_15, (GP_14 + 4)
+	.set	GP_16, (GP_15 + 4)
+	.set	GP_17, (GP_16 + 4)
+	.set	GP_18, (GP_17 + 4)
+
+	.set	GP_19, (GP_18 + 4)
+	.set	GP_20, (GP_19 + 4)
+	.set	GP_21, (GP_20 + 4)
+	.set	GP_22, (GP_21 + 4)
+
+	.set	GP_23, (GP_22 + 4)
+	.set	GP_24, (GP_23 + 4)
+	.set	GP_25, (GP_24 + 4)
+	.set	GP_26, (GP_25 + 4)
+
+	.set	GP_27, (GP_26 + 4)
+	.set	GP_28, (GP_27 + 4)
+	.set	GP_29, (GP_28 + 4)
+	.set	GP_30, (GP_29 + 4)
+
+	.set	GP_31, (GP_30 + 4)
+	.set	GP_CR, (GP_31 + 4)
+	.set	GP_PC, (GP_CR + 4)
+	.set	GP_MSR, (GP_PC + 4)
+
+	.set	FP_0, 0
+	.set	FP_1, (FP_0 + 4)
+	.set	FP_2, (FP_1 + 4)
+	.set	FP_3, (FP_2 + 4)
+	.set	FP_4, (FP_3 + 4)
+	.set	FP_5, (FP_4 + 4)
+	.set	FP_6, (FP_5 + 4)
+	.set	FP_7, (FP_6 + 4)
+	.set	FP_8, (FP_7 + 4)
+	.set	FP_9, (FP_8 + 4)
+	.set	FP_10, (FP_9 + 4)
+	.set	FP_11, (FP_10 + 4)
+	.set	FP_12, (FP_11 + 4)
+	.set	FP_13, (FP_12 + 4)
+	.set	FP_14, (FP_13 + 4)
+	.set	FP_15, (FP_14 + 4)
+	.set	FP_16, (FP_15 + 4)
+	.set	FP_17, (FP_16 + 4)
+	.set	FP_18, (FP_17 + 4)
+	.set	FP_19, (FP_18 + 4)
+	.set	FP_20, (FP_19 + 4)
+	.set	FP_21, (FP_20 + 4)
+	.set	FP_22, (FP_21 + 4)
+	.set	FP_23, (FP_22 + 4)
+	.set	FP_24, (FP_23 + 4)
+	.set	FP_25, (FP_24 + 4)
+	.set	FP_26, (FP_25 + 4)
+	.set	FP_27, (FP_26 + 4)
+	.set	FP_28, (FP_27 + 4)
+	.set	FP_29, (FP_28 + 4)
+	.set	FP_30, (FP_29 + 4)
+	.set	FP_31, (FP_30 + 4)
+	.set	FP_FPSCR, (FP_31 + 4)
+	
+	.set	IP_LINK, 0
+	.set	IP_0, (IP_LINK + 8)
+	.set	IP_2, (IP_0 + 4)
+
+	.set	IP_3, (IP_2 + 4)
+	.set	IP_4, (IP_3 + 4)
+	.set	IP_5, (IP_4 + 4)
+	.set	IP_6, (IP_5 + 4)
+	
+	.set	IP_7, (IP_6 + 4)
+	.set	IP_8, (IP_7 + 4)
+	.set	IP_9, (IP_8 + 4)
+	.set	IP_10, (IP_9 + 4)
+	
+	.set	IP_11, (IP_10 + 4)
+	.set	IP_12, (IP_11 + 4)
+	.set	IP_13, (IP_12 + 4)
+	.set	IP_28, (IP_13 + 4)
+
+	.set	IP_29, (IP_28 + 4)
+	.set	IP_30, (IP_29 + 4)
+	.set	IP_31, (IP_30 + 4)
+	.set	IP_CR, (IP_31 + 4)
+	
+	.set	IP_CTR, (IP_CR + 4)
+	.set	IP_XER, (IP_CTR + 4)
+	.set	IP_LR, (IP_XER + 4)
+	.set	IP_PC, (IP_LR + 4)
+	
+	.set	IP_MSR, (IP_PC + 4)
+	.set	IP_END, (IP_MSR + 16)
+	
+	BEGIN_CODE
+/*
+ *  _CPU_Context_save_fp_context
+ *
+ *  This routine is responsible for saving the FP context
+ *  at *fp_context_ptr.  If the point to load the FP context
+ *  from is changed then the pointer is modified by this routine.
+ *
+ *  Sometimes a macro implementation of this is in cpu.h which dereferences
+ *  the ** and a similarly named routine in this file is passed something
+ *  like a (Context_Control_fp *).  The general rule on making this decision
+ *  is to avoid writing assembly language.
+ */
+
+	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
+	PUBLIC_PROC (_CPU_Context_save_fp)
+PROC (_CPU_Context_save_fp):
+#if (PPC_HAS_FPU == 1)
+	lwz	r3, 0(r3)
+	stfs	f0, FP_0(r3)
+	stfs	f1, FP_1(r3)
+	stfs	f2, FP_2(r3)
+	stfs	f3, FP_3(r3)
+	stfs	f4, FP_4(r3)
+	stfs	f5, FP_5(r3)
+	stfs	f6, FP_6(r3)
+	stfs	f7, FP_7(r3)
+	stfs	f8, FP_8(r3)
+	stfs	f9, FP_9(r3)
+	stfs	f10, FP_10(r3)
+	stfs	f11, FP_11(r3)
+	stfs	f12, FP_12(r3)
+	stfs	f13, FP_13(r3)
+	stfs	f14, FP_14(r3)
+	stfs	f15, FP_15(r3)
+	stfs	f16, FP_16(r3)
+	stfs	f17, FP_17(r3)
+	stfs	f18, FP_18(r3)
+	stfs	f19, FP_19(r3)
+	stfs	f20, FP_20(r3)
+	stfs	f21, FP_21(r3)
+	stfs	f22, FP_22(r3)
+	stfs	f23, FP_23(r3)
+	stfs	f24, FP_24(r3)
+	stfs	f25, FP_25(r3)
+	stfs	f26, FP_26(r3)
+	stfs	f27, FP_27(r3)
+	stfs	f28, FP_28(r3)
+	stfs	f29, FP_29(r3)
+	stfs	f30, FP_30(r3)
+	stfs	f31, FP_31(r3)
+	mffs	f2
+	stfs	f2, FP_FPSCR(r3)
+#endif
+	blr
+
+/*
+ *  _CPU_Context_restore_fp_context
+ *
+ *  This routine is responsible for restoring the FP context
+ *  at *fp_context_ptr.  If the point to load the FP context
+ *  from is changed then the pointer is modified by this routine.
+ *
+ *  Sometimes a macro implementation of this is in cpu.h which dereferences
+ *  the ** and a similarly named routine in this file is passed something
+ *  like a (Context_Control_fp *).  The general rule on making this decision
+ *  is to avoid writing assembly language.
+ */
+
+	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
+	PUBLIC_PROC (_CPU_Context_restore_fp)
+PROC (_CPU_Context_restore_fp):
+#if (PPC_HAS_FPU == 1)
+	lwz	r3, 0(r3)
+	lfs	f2, FP_FPSCR(r3)
+	mtfsf	255, f2
+	lfs	f0, FP_0(r3)
+	lfs	f1, FP_1(r3)
+	lfs	f2, FP_2(r3)
+	lfs	f3, FP_3(r3)
+	lfs	f4, FP_4(r3)
+	lfs	f5, FP_5(r3)
+	lfs	f6, FP_6(r3)
+	lfs	f7, FP_7(r3)
+	lfs	f8, FP_8(r3)
+	lfs	f9, FP_9(r3)
+	lfs	f10, FP_10(r3)
+	lfs	f11, FP_11(r3)
+	lfs	f12, FP_12(r3)
+	lfs	f13, FP_13(r3)
+	lfs	f14, FP_14(r3)
+	lfs	f15, FP_15(r3)
+	lfs	f16, FP_16(r3)
+	lfs	f17, FP_17(r3)
+	lfs	f18, FP_18(r3)
+	lfs	f19, FP_19(r3)
+	lfs	f20, FP_20(r3)
+	lfs	f21, FP_21(r3)
+	lfs	f22, FP_22(r3)
+	lfs	f23, FP_23(r3)
+	lfs	f24, FP_24(r3)
+	lfs	f25, FP_25(r3)
+	lfs	f26, FP_26(r3)
+	lfs	f27, FP_27(r3)
+	lfs	f28, FP_28(r3)
+	lfs	f29, FP_29(r3)
+	lfs	f30, FP_30(r3)
+	lfs	f31, FP_31(r3)
+#endif
+	blr
+
+
+/*  _CPU_Context_switch
+ *
+ *  This routine performs a normal non-FP context switch.
+ */
+	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
+	PUBLIC_PROC (_CPU_Context_switch)
+PROC (_CPU_Context_switch):
+	sync
+	isync
+	/* This assumes that all the registers are in the given order */
+	li	r5, 32
+	addi	r3,r3,-4
+#if ( PPC_USE_DATA_CACHE )
+	dcbz	r5, r3
+#endif
+	stw	r1, GP_1+4(r3)
+	stw	r2, GP_2+4(r3)
+#if (PPC_USE_MULTIPLE == 1)
+	addi	r3, r3, GP_18+4
+#if ( PPC_USE_DATA_CACHE )
+	dcbz	r5, r3
+#endif
+	stmw	r13, GP_13-GP_18(r3)
+#else
+	stw	r13, GP_13+4(r3)
+	stw	r14, GP_14+4(r3)
+	stw	r15, GP_15+4(r3)
+	stw	r16, GP_16+4(r3)
+	stw	r17, GP_17+4(r3)
+	stwu	r18, GP_18+4(r3)
+#if ( PPC_USE_DATA_CACHE )
+	dcbz	r5, r3
+#endif
+	stw	r19, GP_19-GP_18(r3)
+	stw	r20, GP_20-GP_18(r3)
+	stw	r21, GP_21-GP_18(r3)
+	stw	r22, GP_22-GP_18(r3)
+	stw	r23, GP_23-GP_18(r3)
+	stw	r24, GP_24-GP_18(r3)
+	stw	r25, GP_25-GP_18(r3)
+	stw	r26, GP_26-GP_18(r3)
+	stw	r27, GP_27-GP_18(r3)
+	stw	r28, GP_28-GP_18(r3)
+	stw	r29, GP_29-GP_18(r3)
+	stw	r30, GP_30-GP_18(r3)
+	stw	r31, GP_31-GP_18(r3)
+#endif
+#if ( PPC_USE_DATA_CACHE )
+	dcbt	r0, r4
+#endif
+	mfcr	r6
+	stw	r6, GP_CR-GP_18(r3)
+	mflr	r7
+	stw	r7, GP_PC-GP_18(r3)
+	mfmsr	r8
+	stw	r8, GP_MSR-GP_18(r3)
+
+#if ( PPC_USE_DATA_CACHE )
+	dcbt	r5, r4
+#endif
+	lwz	r1, GP_1(r4)
+	lwz	r2, GP_2(r4)
+#if (PPC_USE_MULTIPLE == 1)
+	addi	r4, r4, GP_19
+#if ( PPC_USE_DATA_CACHE )
+	dcbt	r5, r4
+#endif
+	lmw	r13, GP_13-GP_19(r4)
+#else
+	lwz	r13, GP_13(r4)
+	lwz	r14, GP_14(r4)
+	lwz	r15, GP_15(r4)
+	lwz	r16, GP_16(r4)
+	lwz	r17, GP_17(r4)
+	lwz	r18, GP_18(r4)
+	lwzu	r19, GP_19(r4)
+#if ( PPC_USE_DATA_CACHE )
+	dcbt	r5, r4
+#endif
+	lwz	r20, GP_20-GP_19(r4)
+	lwz	r21, GP_21-GP_19(r4)
+	lwz	r22, GP_22-GP_19(r4)
+	lwz	r23, GP_23-GP_19(r4)
+	lwz	r24, GP_24-GP_19(r4)
+	lwz	r25, GP_25-GP_19(r4)
+	lwz	r26, GP_26-GP_19(r4)
+	lwz	r27, GP_27-GP_19(r4)
+	lwz	r28, GP_28-GP_19(r4)
+	lwz	r29, GP_29-GP_19(r4)
+	lwz	r30, GP_30-GP_19(r4)
+	lwz	r31, GP_31-GP_19(r4)
+#endif
+	lwz	r6, GP_CR-GP_19(r4)
+	lwz	r7, GP_PC-GP_19(r4)
+	lwz	r8, GP_MSR-GP_19(r4)
+	mtcrf	255, r6
+	mtlr	r7
+	mtmsr	r8
+
+	blr
+
+/*
+ *  _CPU_Context_restore
+ *
+ *  This routine is generallu used only to restart self in an
+ *  efficient manner.  It may simply be a label in _CPU_Context_switch.
+ *
+ *  NOTE: May be unnecessary to reload some registers.
+ */
+/*
+ * ACB: Don't worry about cache optimisation here - this is not THAT critical.
+ */
+	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
+	PUBLIC_PROC (_CPU_Context_restore)
+PROC (_CPU_Context_restore):
+	lwz	r5, GP_CR(r3)
+	lwz	r6, GP_PC(r3)
+	lwz	r7, GP_MSR(r3)
+	mtcrf	255, r5
+	mtlr	r6
+	mtmsr	r7
+	lwz	r1, GP_1(r3)
+	lwz	r2, GP_2(r3)
+#if (PPC_USE_MULTIPLE == 1)
+	lmw	r13, GP_13(r3)
+#else
+	lwz	r13, GP_13(r3)
+	lwz	r14, GP_14(r3)
+	lwz	r15, GP_15(r3)
+	lwz	r16, GP_16(r3)
+	lwz	r17, GP_17(r3)
+	lwz	r18, GP_18(r3)
+	lwz	r19, GP_19(r3)
+	lwz	r20, GP_20(r3)
+	lwz	r21, GP_21(r3)
+	lwz	r22, GP_22(r3)
+	lwz	r23, GP_23(r3)
+	lwz	r24, GP_24(r3)
+	lwz	r25, GP_25(r3)
+	lwz	r26, GP_26(r3)
+	lwz	r27, GP_27(r3)
+	lwz	r28, GP_28(r3)
+	lwz	r29, GP_29(r3)
+	lwz	r30, GP_30(r3)
+	lwz	r31, GP_31(r3)
+#endif
+
+	blr
+
diff --git a/c/src/exec/score/cpu/powerpc/mpc821.h b/c/src/exec/score/cpu/powerpc/mpc821.h
deleted file mode 100644
index aa8c271f47..0000000000
--- a/c/src/exec/score/cpu/powerpc/mpc821.h
+++ /dev/null
@@ -1,1237 +0,0 @@
-/*
-**************************************************************************
-**************************************************************************
-**                                                                      **
-**  MOTOROLA MPC21 PORTABLE SYSTEMS MICROPROCESSOR                      **
-**                                                                      **
-**                        HARDWARE DECLARATIONS                         **
-**                                                                      **
-**                                                                      **
-**  Submitted By:                                                       **
-**                                                                      **
-**      W. Eric Norum                                                   **
-**      Saskatchewan Accelerator Laboratory                             **
-**      University of Saskatchewan                                      **
-**      107 North Road                                                  **
-**      Saskatoon, Saskatchewan, CANADA                                 **
-**      S7N 5C6                                                         **
-**                                                                      **
-**      eric@skatter.usask.ca                                           **
-**                                                                      **
-**  Modified for use with the MPC860 (original code was for MC68360)    **
-**  by                                                                  **
-**      Jay Monkman                                                     **
-**      Frasca International, Inc.                                      **
-**      906 E. Airport Rd.                                              **
-**      Urbana, IL, 61801                                               **
-**                                                                      **
-**      jmonkman@frasca.com                                             **
-**                                                                      **
-**  Modified further for use with the MPC821 by:                        **
-**      Andrew Bray <andy@chaos.org.uk>                                 **
-**                                                                      **
-**************************************************************************
-**************************************************************************
-*/
-
-#ifndef __MPC821_h
-#define __MPC821_h
-
-#ifndef ASM
-/*
-  Macros for SPRs
-*/
-
-#define M821_MI_CTR_GPM       (1<<31)
-#define M821_MI_CTR_PPM       (1<<30)
-#define M821_MI_CTR_CIDEF     (1<<29)
-#define M821_MI_CTR_RSV4I     (1<<27)
-#define M821_MI_CTR_PPCS      (1<<25)
-
-#define M821_MD_CTR_GPM       (1<<31)
-#define M821_MD_CTR_PPM       (1<<30)
-#define M821_MD_CTR_CIDEF     (1<<29)
-#define M821_MD_CTR_WTDEF     (1<<28)
-#define M821_MD_CTR_RSV4D     (1<<27)
-#define M821_MD_CTR_TWAM      (1<<26)
-#define M821_MD_CTR_PPCS      (1<<25)
-
-#define M821_MI_EPN_VALID     (1<<9)
-
-#define M821_MD_EPN_VALID     (1<<9)
-
-#define M821_MI_TWC_G         (1<<4)
-#define M821_MI_TWC_PSS       (0<<2)
-#define M821_MI_TWC_PS512     (1<<2)
-#define M821_MI_TWC_PS8       (3<<2)
-#define M821_MI_TWC_VALID     (1)
-
-#define M821_MD_TWC_G         (1<<4)
-#define M821_MD_TWC_PSS       (0<<2)
-#define M821_MD_TWC_PS512     (1<<2)
-#define M821_MD_TWC_PS8       (3<<2)
-#define M821_MD_TWC_WT        (1<<1)
-#define M821_MD_TWC_VALID     (1)
-
-#define M821_MI_RPN_F         (0xf<<4)
-#define M821_MI_RPN_16K       (1<<3)
-#define M821_MI_RPN_SHARED    (1<<2)
-#define M821_MI_RPN_CI        (1<<1)
-#define M821_MI_RPN_VALID     (1)
-
-#define M821_MD_RPN_CHANGE    (1<<8)
-#define M821_MD_RPN_F         (0xf<<4)
-#define M821_MD_RPN_16K       (1<<3)
-#define M821_MD_RPN_SHARED    (1<<2)
-#define M821_MD_RPN_CI        (1<<1)
-#define M821_MD_RPN_VALID     (1)
-
-#define M821_MI_AP_Kp         (1)
-
-#define M821_MD_AP_Kp         (1)
-
-#define M821_CACHE_CMD_SFWT          (0x1<<24)
-#define M821_CACHE_CMD_ENABLE        (0x2<<24)
-#define M821_CACHE_CMD_CFWT          (0x3<<24)
-#define M821_CACHE_CMD_DISABLE       (0x4<<24)
-#define M821_CACHE_CMD_STLES         (0x5<<24)
-#define M821_CACHE_CMD_LLCB          (0x6<<24)
-#define M821_CACHE_CMD_CLES          (0x7<<24)
-#define M821_CACHE_CMD_UNLOCK        (0x8<<24)
-#define M821_CACHE_CMD_UNLOCKALL     (0xa<<24)
-#define M821_CACHE_CMD_INVALIDATE    (0xc<<24)
-#define M821_CACHE_CMD_FLUSH         (0xe<<24)
-
-
-
-/*
-*************************************************************************
-*                         REGISTER SUBBLOCKS                            *
-*************************************************************************
-*/
-
-/*
- * Memory controller registers
- */
-typedef struct m821MEMCRegisters_ {
-  rtems_unsigned32        br;
-  rtems_unsigned32        or;
-} m821MEMCRegisters_t;
-
-/*
- * Serial Communications Controller registers
- */
-typedef struct m821SCCRegisters_ {
-  rtems_unsigned32        gsmr_l;
-  rtems_unsigned32        gsmr_h;
-  rtems_unsigned16        psmr;
-  rtems_unsigned16        _pad0;
-  rtems_unsigned16        todr;
-  rtems_unsigned16        dsr;
-  rtems_unsigned16        scce;
-  rtems_unsigned16        _pad1;
-  rtems_unsigned16        sccm;
-  rtems_unsigned8         _pad2;
-  rtems_unsigned8         sccs;
-  rtems_unsigned32        _pad3[2];
-} m821SCCRegisters_t;
-
-/*
- * Serial Management Controller registers
- */
-typedef struct m821SMCRegisters_ {
-  rtems_unsigned16        _pad0;
-  rtems_unsigned16        smcmr;
-  rtems_unsigned16        _pad1;
-  rtems_unsigned8         smce;
-  rtems_unsigned8         _pad2;
-  rtems_unsigned16        _pad3;
-  rtems_unsigned8         smcm;
-  rtems_unsigned8         _pad4;
-  rtems_unsigned32        _pad5;
-} m821SMCRegisters_t;
-
-/*
-*************************************************************************
-*                         Miscellaneous Parameters                      *
-*************************************************************************
-*/
-typedef struct m821MiscParms_ {
-  rtems_unsigned16        rev_num;
-  rtems_unsigned16        _res1;
-  rtems_unsigned32        _res2;
-  rtems_unsigned32        _res3;
-} m821MiscParms_t;
-
-/*
-*************************************************************************
-*                              RISC Timers                              *
-*************************************************************************
-*/
-typedef struct m821TimerParms_ {
-  rtems_unsigned16        tm_base;
-  rtems_unsigned16        _tm_ptr;
-  rtems_unsigned16        _r_tmr;
-  rtems_unsigned16        _r_tmv;
-  rtems_unsigned32        tm_cmd;
-  rtems_unsigned32        tm_cnt;
-} m821TimerParms_t;
-
-/*
- * RISC Controller Configuration Register (RCCR)
- * All other bits in this register are reserved.
- */
-#define M821_RCCR_TIME          (1<<15)    /* Enable timer */
-#define M821_RCCR_TIMEP(x)      ((x)<<8)   /* Timer period */
-#define M821_RCCR_DR1M          (1<<7)     /* IDMA Rqst 1 Mode */
-#define M821_RCCR_DR0M          (1<<6)     /* IDMA Rqst 0 Mode */
-#define M821_RCCR_DRQP(x)       ((x)<<4)   /* IDMA Rqst Priority */
-#define M821_RCCR_EIE           (1<<3)     /* External Interrupt Enable */
-#define M821_RCCR_SCD           (1<<2)     /* Scheduler Configuration */
-#define M821_RCCR_ERAM(x)       (x)        /* Enable RAM Microcode */
-
-/*
- * Command register
- * Set up this register before issuing a M821_CR_OP_SET_TIMER command.
- */
-#define M821_TM_CMD_V           (1<<31)         /* Set to enable timer */
-#define M821_TM_CMD_R           (1<<30)         /* Set for automatic restart */
-#define M821_TM_CMD_PWM         (1<<29)         /* Set for PWM operation */
-#define M821_TM_CMD_TIMER(x)    ((x)<<16)       /* Select timer */
-#define M821_TM_CMD_PERIOD(x)   (x)             /* Timer period (16 bits) */
-
-/*
-*************************************************************************
-*                               DMA Controllers                         *
-*************************************************************************
-*/
-typedef struct m821IDMAparms_ {
-  rtems_unsigned16        ibase;
-  rtems_unsigned16        dcmr;
-  rtems_unsigned32        _sapr;
-  rtems_unsigned32        _dapr;
-  rtems_unsigned16        ibptr;
-  rtems_unsigned16        _write_sp;
-  rtems_unsigned32        _s_byte_c;
-  rtems_unsigned32        _d_byte_c;
-  rtems_unsigned32        _s_state;
-  rtems_unsigned32        _itemp[4];
-  rtems_unsigned32        _sr_mem;
-  rtems_unsigned16        _read_sp;
-  rtems_unsigned16        _res0;
-  rtems_unsigned16        _res1;
-  rtems_unsigned16        _res2;
-  rtems_unsigned32        _d_state;
-} m821IDMAparms_t;
-
-
-/*
-*************************************************************************
-*                               DSP                                     *
-*************************************************************************
-*/
-typedef struct m821DSPparms_ {
-  rtems_unsigned32        fdbase;
-  rtems_unsigned32        _fd_ptr;
-  rtems_unsigned32        _dstate;
-  rtems_unsigned32        _pad0;
-  rtems_unsigned16        _dstatus;
-  rtems_unsigned16        _i;
-  rtems_unsigned16        _tap;
-  rtems_unsigned16        _cbase;
-  rtems_unsigned16        _pad1;
-  rtems_unsigned16        _xptr;
-  rtems_unsigned16        _pad2;
-  rtems_unsigned16        _yptr;
-  rtems_unsigned16        _m;
-  rtems_unsigned16        _pad3;
-  rtems_unsigned16        _n;
-  rtems_unsigned16        _pad4;
-  rtems_unsigned16        _k;
-  rtems_unsigned16        _pad5;
-} m821DSPparms_t;
-
-/*
-*************************************************************************
-*                   Serial Communication Controllers                    *
-*************************************************************************
-*/
-typedef struct m821SCCparms_ {
-  rtems_unsigned16        rbase;
-  rtems_unsigned16        tbase;
-  rtems_unsigned8         rfcr;
-  rtems_unsigned8         tfcr;
-  rtems_unsigned16        mrblr;
-  rtems_unsigned32        _rstate;
-  rtems_unsigned32        _pad0;
-  rtems_unsigned16        _rbptr;
-  rtems_unsigned16        _pad1;
-  rtems_unsigned32        _pad2;
-  rtems_unsigned32        _tstate;
-  rtems_unsigned32        _pad3;
-  rtems_unsigned16        _tbptr;
-  rtems_unsigned16        _pad4;
-  rtems_unsigned32        _pad5;
-  rtems_unsigned32        _rcrc;
-  rtems_unsigned32        _tcrc;
-  union {
-    struct {
-      rtems_unsigned32        _res0;
-      rtems_unsigned32        _res1;
-      rtems_unsigned16        max_idl;
-      rtems_unsigned16        _idlc;
-      rtems_unsigned16        brkcr;
-      rtems_unsigned16        parec;
-      rtems_unsigned16        frmec;
-      rtems_unsigned16        nosec;
-      rtems_unsigned16        brkec;
-      rtems_unsigned16        brklen;
-      rtems_unsigned16        uaddr[2];
-      rtems_unsigned16        _rtemp;
-      rtems_unsigned16        toseq;
-      rtems_unsigned16        character[8];
-      rtems_unsigned16        rccm;
-      rtems_unsigned16        rccr;
-      rtems_unsigned16        rlbc;
-    } uart;
-  } un;
-} m821SCCparms_t;
-
-typedef struct m821SCCENparms_ {
-  rtems_unsigned16        rbase;
-  rtems_unsigned16        tbase;
-  rtems_unsigned8         rfcr;
-  rtems_unsigned8         tfcr;
-  rtems_unsigned16        mrblr;
-  rtems_unsigned32        _rstate;
-  rtems_unsigned32        _pad0;
-  rtems_unsigned16        _rbptr;
-  rtems_unsigned16        _pad1;
-  rtems_unsigned32        _pad2;
-  rtems_unsigned32        _tstate;
-  rtems_unsigned32        _pad3;
-  rtems_unsigned16        _tbptr;
-  rtems_unsigned16        _pad4;
-  rtems_unsigned32        _pad5;
-  rtems_unsigned32        _rcrc;
-  rtems_unsigned32        _tcrc;
-  union {
-    struct {
-      rtems_unsigned32        _res0;
-      rtems_unsigned32        _res1;
-      rtems_unsigned16        max_idl;
-      rtems_unsigned16        _idlc;
-      rtems_unsigned16        brkcr;
-      rtems_unsigned16        parec;
-      rtems_unsigned16        frmec;
-      rtems_unsigned16        nosec;
-      rtems_unsigned16        brkec;
-      rtems_unsigned16        brklen;
-      rtems_unsigned16        uaddr[2];
-      rtems_unsigned16        _rtemp;
-      rtems_unsigned16        toseq;
-      rtems_unsigned16        character[8];
-      rtems_unsigned16        rccm;
-      rtems_unsigned16        rccr;
-      rtems_unsigned16        rlbc;
-    } uart;
-    struct {
-      rtems_unsigned32        c_pres;
-      rtems_unsigned32        c_mask;
-      rtems_unsigned32        crcec;
-      rtems_unsigned32        alec;
-      rtems_unsigned32        disfc;
-      rtems_unsigned16        pads;
-      rtems_unsigned16        ret_lim;
-      rtems_unsigned16        _ret_cnt;
-      rtems_unsigned16        mflr;
-      rtems_unsigned16        minflr;
-      rtems_unsigned16        maxd1;
-      rtems_unsigned16        maxd2;
-      rtems_unsigned16        _maxd;
-      rtems_unsigned16        dma_cnt;
-      rtems_unsigned16        _max_b;
-      rtems_unsigned16        gaddr1;
-      rtems_unsigned16        gaddr2;
-      rtems_unsigned16        gaddr3;
-      rtems_unsigned16        gaddr4;
-      rtems_unsigned32        _tbuf0data0;
-      rtems_unsigned32        _tbuf0data1;
-      rtems_unsigned32        _tbuf0rba0;
-      rtems_unsigned32        _tbuf0crc;
-      rtems_unsigned16        _tbuf0bcnt;
-      rtems_unsigned16        paddr_h;
-      rtems_unsigned16        paddr_m;
-      rtems_unsigned16        paddr_l;
-      rtems_unsigned16        p_per;
-      rtems_unsigned16        _rfbd_ptr;
-      rtems_unsigned16        _tfbd_ptr;
-      rtems_unsigned16        _tlbd_ptr;
-      rtems_unsigned32        _tbuf1data0;
-      rtems_unsigned32        _tbuf1data1;
-      rtems_unsigned32        _tbuf1rba0;
-      rtems_unsigned32        _tbuf1crc;
-      rtems_unsigned16        _tbuf1bcnt;
-      rtems_unsigned16        _tx_len;
-      rtems_unsigned16        iaddr1;
-      rtems_unsigned16        iaddr2;
-      rtems_unsigned16        iaddr3;
-      rtems_unsigned16        iaddr4;
-      rtems_unsigned16        _boff_cnt;
-      rtems_unsigned16        taddr_l;
-      rtems_unsigned16        taddr_m;
-      rtems_unsigned16        taddr_h;
-    } ethernet;
-  } un;
-} m821SCCENparms_t;
-
-/*
- * Receive and transmit function code register bits
- * These apply to the function code registers of all devices, not just SCC.
- */
-#define M821_RFCR_BO(x)         ((x)<<3)
-#define M821_RFCR_MOT           (2<<3)
-#define M821_RFCR_DMA_SPACE(x)  (x)
-#define M821_TFCR_BO(x)         ((x)<<3)
-#define M821_TFCR_MOT           (2<<3)
-#define M821_TFCR_DMA_SPACE(x)  (x)
-
-/*
-*************************************************************************
-*                     Serial Management Controllers                     *
-*************************************************************************
-*/
-typedef struct m821SMCparms_ {
-  rtems_unsigned16        rbase;
-  rtems_unsigned16        tbase;
-  rtems_unsigned8         rfcr;
-  rtems_unsigned8         tfcr;
-  rtems_unsigned16        mrblr;
-  rtems_unsigned32        _rstate;
-  rtems_unsigned32        _pad0;
-  rtems_unsigned16        _rbptr;
-  rtems_unsigned16        _pad1;
-  rtems_unsigned32        _pad2;
-  rtems_unsigned32        _tstate;
-  rtems_unsigned32        _pad3;
-  rtems_unsigned16        _tbptr;
-  rtems_unsigned16        _pad4;
-  rtems_unsigned32        _pad5;
-  union {
-    struct {
-      rtems_unsigned16        max_idl;
-      rtems_unsigned16        _idlc;
-      rtems_unsigned16        brklen;
-      rtems_unsigned16        brkec;
-      rtems_unsigned16        brkcr;
-      rtems_unsigned16        _r_mask;
-    } uart;
-    struct {
-      rtems_unsigned16        _pad0[5];
-    } transparent;
-  } un;
-} m821SMCparms_t;
-
-/*
- * Mode register
- */
-#define M821_SMCMR_CLEN(x)              ((x)<<11)    /* Character length */
-#define M821_SMCMR_2STOP                (1<<10)      /* 2 stop bits */
-#define M821_SMCMR_PARITY               (1<<9)       /* Enable parity */
-#define M821_SMCMR_EVEN                 (1<<8)       /* Even parity */
-#define M821_SMCMR_SM_GCI               (0<<4)       /* GCI Mode */
-#define M821_SMCMR_SM_UART              (2<<4)       /* UART Mode */
-#define M821_SMCMR_SM_TRANSPARENT       (3<<4)       /* Transparent Mode */
-#define M821_SMCMR_DM_LOOPBACK          (1<<2)       /* Local loopback mode */
-#define M821_SMCMR_DM_ECHO              (2<<2)       /* Echo mode */
-#define M821_SMCMR_TEN                  (1<<1)       /* Enable transmitter */
-#define M821_SMCMR_REN                  (1<<0)       /* Enable receiver */
-
-/*
- * Event and mask registers (SMCE, SMCM)
- */
-#define M821_SMCE_BRKE  (1<<6)
-#define M821_SMCE_BRK   (1<<4)
-#define M821_SMCE_BSY   (1<<2)
-#define M821_SMCE_TX    (1<<1)
-#define M821_SMCE_RX    (1<<0)
-
-/*
-*************************************************************************
-*                      Serial Peripheral Interface                      *
-*************************************************************************
-*/
-typedef struct m821SPIparms_ {
-  rtems_unsigned16        rbase;
-  rtems_unsigned16        tbase;
-  rtems_unsigned8         rfcr;
-  rtems_unsigned8         tfcr;
-  rtems_unsigned16        mrblr;
-  rtems_unsigned32        _rstate;
-  rtems_unsigned32        _pad0;
-  rtems_unsigned16        _rbptr;
-  rtems_unsigned16        _pad1;
-  rtems_unsigned32        _pad2;
-  rtems_unsigned32        _tstate;
-  rtems_unsigned32        _pad3;
-  rtems_unsigned16        _tbptr;
-  rtems_unsigned16        _pad4;
-  rtems_unsigned32        _pad5;
-} m821SPIparms_t;
-
-/*
- * Mode register (SPMODE)
- */
-#define M821_SPMODE_LOOP                (1<<14) /* Local loopback mode */
-#define M821_SPMODE_CI                  (1<<13) /* Clock invert */
-#define M821_SPMODE_CP                  (1<<12) /* Clock phase */
-#define M821_SPMODE_DIV16               (1<<11) /* Divide BRGCLK by 16 */
-#define M821_SPMODE_REV                 (1<<10) /* Reverse data */
-#define M821_SPMODE_MASTER              (1<<9)  /* SPI is master */
-#define M821_SPMODE_EN                  (1<<8)  /* Enable SPI */
-#define M821_SPMODE_CLEN(x)             ((x)<<4)        /* Character length */
-#define M821_SPMODE_PM(x)               (x)     /* Prescaler modulus */
-
-/*
- * Mode register (SPCOM)
- */
-#define M821_SPCOM_STR                  (1<<7)  /* Start transmit */
-
-/*
- * Event and mask registers (SPIE, SPIM)
- */
-#define M821_SPIE_MME   (1<<5)          /* Multi-master error */
-#define M821_SPIE_TXE   (1<<4)          /* Tx error */
-#define M821_SPIE_BSY   (1<<2)          /* Busy condition*/
-#define M821_SPIE_TXB   (1<<1)          /* Tx buffer */
-#define M821_SPIE_RXB   (1<<0)          /* Rx buffer */
-
-/*
-*************************************************************************
-*                 SDMA (SCC, SMC, SPI) Buffer Descriptors               *
-*************************************************************************
-*/
-typedef struct m821BufferDescriptor_ {
-  rtems_unsigned16        status;
-  rtems_unsigned16        length;
-  volatile void           *buffer;
-} m821BufferDescriptor_t;
-
-/*
- * Bits in receive buffer descriptor status word
- */
-#define M821_BD_EMPTY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
-#define M821_BD_WRAP            (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
-#define M821_BD_INTERRUPT       (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
-#define M821_BD_LAST            (1<<11) /* Ethernet, SPI */
-#define M821_BD_CONTROL_CHAR    (1<<11) /* SCC UART */
-#define M821_BD_FIRST_IN_FRAME  (1<<10) /* Ethernet */
-#define M821_BD_ADDRESS         (1<<10) /* SCC UART */
-#define M821_BD_CONTINUOUS      (1<<9)  /* SCC UART, SMC UART, SPI */
-#define M821_BD_MISS            (1<<8)  /* Ethernet */
-#define M821_BD_IDLE            (1<<8)  /* SCC UART, SMC UART */
-#define M821_BD_ADDRSS_MATCH    (1<<7)  /* SCC UART */
-#define M821_BD_LONG            (1<<5)  /* Ethernet */
-#define M821_BD_BREAK           (1<<5)  /* SCC UART, SMC UART */
-#define M821_BD_NONALIGNED      (1<<4)  /* Ethernet */
-#define M821_BD_FRAMING_ERROR   (1<<4)  /* SCC UART, SMC UART */
-#define M821_BD_SHORT           (1<<3)  /* Ethernet */
-#define M821_BD_PARITY_ERROR    (1<<3)  /* SCC UART, SMC UART */
-#define M821_BD_CRC_ERROR       (1<<2)  /* Ethernet */
-#define M821_BD_OVERRUN         (1<<1)  /* Ethernet, SCC UART, SMC UART, SPI */
-#define M821_BD_COLLISION       (1<<0)  /* Ethernet */
-#define M821_BD_CARRIER_LOST    (1<<0)  /* SCC UART, SMC UART */
-#define M821_BD_MASTER_ERROR    (1<<0)  /* SPI */
-
-/*
- * Bits in transmit buffer descriptor status word
- * Many bits have the same meaning as those in receiver buffer descriptors.
- */
-#define M821_BD_READY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
-#define M821_BD_PAD             (1<<14) /* Ethernet */
-#define M821_BD_CTS_REPORT      (1<<11) /* SCC UART */
-#define M821_BD_TX_CRC          (1<<10) /* Ethernet */
-#define M821_BD_DEFER           (1<<9)  /* Ethernet */
-#define M821_BD_HEARTBEAT       (1<<8)  /* Ethernet */
-#define M821_BD_PREAMBLE        (1<<8)  /* SCC UART, SMC UART */
-#define M821_BD_LATE_COLLISION  (1<<7)  /* Ethernet */
-#define M821_BD_NO_STOP_BIT     (1<<7)  /* SCC UART */
-#define M821_BD_RETRY_LIMIT     (1<<6)  /* Ethernet */
-#define M821_BD_RETRY_COUNT(x)  (((x)&0x3C)>>2) /* Ethernet */
-#define M821_BD_UNDERRUN        (1<<1)  /* Ethernet, SPI */
-#define M821_BD_CARRIER_LOST    (1<<0)  /* Ethernet */
-#define M821_BD_CTS_LOST        (1<<0)  /* SCC UART */
-
-/*
-*************************************************************************
-*                           IDMA Buffer Descriptors                     *
-*************************************************************************
-*/
-typedef struct m821IDMABufferDescriptor_ {
-  rtems_unsigned16        status;
-  rtems_unsigned8         dfcr;       
-  rtems_unsigned8         sfcr;       
-  rtems_unsigned32        length;
-  void                    *source;
-  void                    *destination;
-} m821IDMABufferDescriptor_t;
-
-/*
-*************************************************************************
-*       RISC Communication Processor Module Command Register (CR)       *
-*************************************************************************
-*/
-#define M821_CR_RST             (1<<15) /* Reset communication processor */
-#define M821_CR_OP_INIT_RX_TX   (0<<8)  /* SCC, SMC UART, SMC GCI, SPI */
-#define M821_CR_OP_INIT_RX      (1<<8)  /* SCC, SMC UART, SPI */
-#define M821_CR_OP_INIT_TX      (2<<8)  /* SCC, SMC UART, SPI */
-#define M821_CR_OP_INIT_HUNT    (3<<8)  /* SCC, SMC UART */
-#define M821_CR_OP_STOP_TX      (4<<8)  /* SCC, SMC UART */
-#define M821_CR_OP_GR_STOP_TX   (5<<8)  /* SCC */
-#define M821_CR_OP_INIT_IDMA    (5<<8)  /* IDMA */
-#define M821_CR_OP_RESTART_TX   (6<<8)  /* SCC, SMC UART */
-#define M821_CR_OP_CLOSE_RX_BD  (7<<8)  /* SCC, SMC UART, SPI */
-#define M821_CR_OP_SET_GRP_ADDR (8<<8)  /* SCC */
-#define M821_CR_OP_SET_TIMER    (8<<8)  /* Timer */
-#define M821_CR_OP_GCI_TIMEOUT  (9<<8)  /* SMC GCI */
-#define M821_CR_OP_RESERT_BCS   (10<<8) /* SCC */
-#define M821_CR_OP_GCI_ABORT    (10<<8) /* SMC GCI */
-#define M821_CR_OP_STOP_IDMA    (11<<8) /* IDMA */
-#define M821_CR_OP_START_DSP    (12<<8) /* DSP */
-#define M821_CR_OP_INIT_DSP     (13<<8) /* DSP */
-
-#define M821_CR_CHAN_SCC1       (0<<4)  /* Channel selection */
-#define M821_CR_CHAN_I2C        (1<<4)
-#define M821_CR_CHAN_IDMA1      (1<<4)
-#define M821_CR_CHAN_SCC2       (4<<4)
-#define M821_CR_CHAN_SPI        (5<<4)
-#define M821_CR_CHAN_IDMA2      (5<<4)
-#define M821_CR_CHAN_TIMER      (5<<4)
-#define M821_CR_CHAN_SCC3       (8<<4)
-#define M821_CR_CHAN_SMC1       (9<<4)
-#define M821_CR_CHAN_DSP1       (9<<4)
-#define M821_CR_CHAN_SCC4       (12<<4)
-#define M821_CR_CHAN_SMC2       (13<<4)
-#define M821_CR_CHAN_DSP2       (13<<4)
-#define M821_CR_FLG             (1<<0)  /* Command flag */
-
-/*
-*************************************************************************
-*                 System Protection Control Register (SYPCR)            *
-*************************************************************************
-*/
-#define M821_SYPCR_SWTC(x)      ((x)<<16)   /* Software watchdog timer count */
-#define M821_SYPCR_BMT(x)       ((x)<<8)    /* Bus monitor timing */
-#define M821_SYPCR_BME          (1<<7)      /* Bus monitor enable */
-#define M821_SYPCR_SWF          (1<<3)      /* Software watchdog freeze */
-#define M821_SYPCR_SWE          (1<<2)      /* Software watchdog enable */
-#define M821_SYPCR_SWRI         (1<<1)      /* Watchdog reset/interrupt sel. */
-#define M821_SYPCR_SWP          (1<<0)      /* Software watchdog prescale */
-
-/*
-*************************************************************************
-*                        Memory Control Registers                       *
-*************************************************************************
-*/
-#define M821_UPM_AMX_8col       (0<<20) /* 8 column DRAM */
-#define M821_UPM_AMX_9col       (1<<20) /* 9 column DRAM */
-#define M821_UPM_AMX_10col      (2<<20) /* 10 column DRAM */
-#define M821_UPM_AMX_11col      (3<<20) /* 11 column DRAM */
-#define M821_UPM_AMX_12col      (4<<20) /* 12 column DRAM */
-#define M821_UPM_AMX_13col      (5<<20) /* 13 column DRAM */
-#define M821_MSR_PER(x)         (0x100<<(7-x)) /* Perity error bank (x) */
-#define M821_MSR_WPER           (1<<7)  /* Write protection error */
-#define M821_MPTPR_PTP(x)       ((x)<<8) /* Periodic timer prescaler */
-#define M821_BR_BA(x)           ((x)&0xffff8000) /* Base address */
-#define M821_BR_AT(x)           ((x)<<12) /* Address type */
-#define M821_BR_PS8             (1<<10)  /* 8 bit port */
-#define M821_BR_PS16            (2<<10)  /* 16 bit port */
-#define M821_BR_PS32            (0<<10)  /* 32 bit port */
-#define M821_BR_PARE            (1<<9)   /* Parity checking enable */
-#define M821_BR_WP              (1<<8)   /* Write protect */
-#define M821_BR_MS_GPCM         (0<<6)   /* GPCM */
-#define M821_BR_MS_UPMA         (2<<6)   /* UPM A */
-#define M821_BR_MS_UPMB         (3<<6)   /* UPM B */
-#define M821_MEMC_BR_V          (1<<0)  /* Base/Option register are valid */
-
-#define M821_MEMC_OR_32K        0xffff8000      /* Address range */
-#define M821_MEMC_OR_64K        0xffff0000
-#define M821_MEMC_OR_128K       0xfffe0000
-#define M821_MEMC_OR_256K       0xfffc0000
-#define M821_MEMC_OR_512K       0xfff80000
-#define M821_MEMC_OR_1M         0xfff00000
-#define M821_MEMC_OR_2M         0xffe00000
-#define M821_MEMC_OR_4M         0xffc00000
-#define M821_MEMC_OR_8M         0xff800000
-#define M821_MEMC_OR_16M        0xff000000
-#define M821_MEMC_OR_32M        0xfe000000
-#define M821_MEMC_OR_64M        0xfc000000
-#define M821_MEMC_OR_128        0xf8000000
-#define M821_MEMC_OR_256M       0xf0000000
-#define M821_MEMC_OR_512M       0xe0000000
-#define M821_MEMC_OR_1G         0xc0000000
-#define M821_MEMC_OR_2G         0x80000000
-#define M821_MEMC_OR_4G         0x00000000
-#define M821_MEMC_OR_ATM(x)     ((x)<<12)   /* Address type mask */
-#define M821_MEMC_OR_CSNT       (1<<11)     /* Chip select is negated early */
-#define M821_MEMC_OR_SAM        (1<<11)     /* Address lines are multiplexed */
-#define M821_MEMC_OR_ACS_NORM   (0<<9)      /* *CS asserted with addr lines */
-#define M821_MEMC_OR_ACS_QRTR   (2<<9)      /* *CS asserted 1/4 after addr */
-#define M821_MEMC_OR_ACS_HALF   (3<<9)      /* *CS asserted 1/2 after addr */
-#define M821_MEMC_OR_BI         (1<8)       /* Burst inhibit */
-#define M821_MEMC_OR_SCY(x)     ((x)<<4)    /* Cycle length in clocks */
-#define M821_MEMC_OR_SETA       (1<<3)      /* *TA generated externally */
-#define M821_MEMC_OR_TRLX       (1<<2)      /* Relaxed timing in GPCM */
-#define M821_MEMC_OR_EHTR       (1<<1)      /* Extended hold time on reads */
-
-/*
-*************************************************************************
-*                         UPM Registers (MxMR)                          *
-*************************************************************************
-*/
-#define M821_MEMC_MMR_PTP(x)   ((x)<<24)    /* Periodic timer period */
-#define M821_MEMC_MMR_PTE      (1<<23)      /* Periodic timer enable */
-#define M821_MEMC_MMR_DSP(x)   ((x)<<17)    /* Disable timer period */
-#define M821_MEMC_MMR_G0CL(x)  ((x)<<13)    /* General line 0 control */
-#define M821_MEMC_MMR_UPWAIT   (1<<12)      /* GPL_x4 is UPWAITx */
-#define M821_MEMC_MMR_RLF(x)   ((x)<<8)     /* Read loop field */
-#define M821_MEMC_MMR_WLF(x)   ((x)<<4)     /* Write loop field */
-#define M821_MEMC_MMR_TLF(x)   ((x)<<0)     /* Timer loop field */
-/*
-*************************************************************************
-*                         Memory Command Register (MCR)                 *
-*************************************************************************
-*/
-#define M821_MEMC_MCR_WRITE     (0<<30)     /* WRITE command */
-#define M821_MEMC_MCR_READ      (1<<30)     /* READ command */
-#define M821_MEMC_MCR_RUN       (2<<30)     /* RUN command */
-#define M821_MEMC_MCR_UPMA      (0<<23)     /* Cmd is for UPMA */
-#define M821_MEMC_MCR_UPMB      (1<<23)     /* Cmd is for UPMB */
-#define M821_MEMC_MCR_MB(x)     ((x)<<13)   /* Memory bank when RUN cmd */
-#define M821_MEMC_MCR_MCLF(x)   ((x)<<8)    /* Memory command loop field */
-#define M821_MEMC_MCR_MAD(x)    (x)         /* Machine address */
-
-
-
-/*
-*************************************************************************
-*                         SI Mode Register (SIMODE)                     *
-*************************************************************************
-*/
-#define M821_SI_SMC2_BITS       0xFFFF0000      /* All SMC2 bits */
-#define M821_SI_SMC2_TDM        (1<<31) /* Multiplexed SMC2 */
-#define M821_SI_SMC2_BRG1       (0<<28) /* SMC2 clock souce */
-#define M821_SI_SMC2_BRG2       (1<<28)
-#define M821_SI_SMC2_BRG3       (2<<28)
-#define M821_SI_SMC2_BRG4       (3<<28)
-#define M821_SI_SMC2_CLK5       (0<<28)
-#define M821_SI_SMC2_CLK6       (1<<28)
-#define M821_SI_SMC2_CLK7       (2<<28)
-#define M821_SI_SMC2_CLK8       (3<<28)
-#define M821_SI_SMC1_BITS       0x0000FFFF      /* All SMC1 bits */
-#define M821_SI_SMC1_TDM        (1<<15) /* Multiplexed SMC1 */
-#define M821_SI_SMC1_BRG1       (0<<12) /* SMC1 clock souce */
-#define M821_SI_SMC1_BRG2       (1<<12)
-#define M821_SI_SMC1_BRG3       (2<<12)
-#define M821_SI_SMC1_BRG4       (3<<12)
-#define M821_SI_SMC1_CLK1       (0<<12)
-#define M821_SI_SMC1_CLK2       (1<<12)
-#define M821_SI_SMC1_CLK3       (2<<12)
-#define M821_SI_SMC1_CLK4       (3<<12)
-
-/*
-*************************************************************************
-*                  SDMA Configuration Register (SDCR)                   *
-*************************************************************************
-*/
-#define M821_SDCR_FREEZE        (2<<13) /* Freeze on next bus cycle */
-#define M821_SDCR_RAID_5        (1<<0)  /* Normal arbitration ID */
-
-/*
-*************************************************************************
-*                  SDMA Status Register (SDSR)                          *
-*************************************************************************
-*/
-#define M821_SDSR_SBER          (1<<7)  /* SDMA Channel bus error */
-#define M821_SDSR_DSP2          (1<<1)  /* DSP Chain 2 interrupt */
-#define M821_SDSR_DSP1          (1<<0)  /* DSP Chain 1 interrupt */
-
-/*
-*************************************************************************
-*                      Baud (sic) Rate Generators                       *
-*************************************************************************
-*/
-#define M821_BRG_RST            (1<<17)         /* Reset generator */
-#define M821_BRG_EN             (1<<16)         /* Enable generator */
-#define M821_BRG_EXTC_BRGCLK    (0<<14)         /* Source is BRGCLK */
-#define M821_BRG_EXTC_CLK2      (1<<14)         /* Source is CLK2 pin */
-#define M821_BRG_EXTC_CLK6      (2<<14)         /* Source is CLK6 pin */
-#define M821_BRG_ATB            (1<<13)         /* Autobaud */
-#define M821_BRG_115200         (21<<1)         /* Assume 40 MHz clock */
-#define M821_BRG_57600          (32<<1)
-#define M821_BRG_38400          (64<<1)
-#define M821_BRG_19200          (129<<1)
-#define M821_BRG_9600           (259<<1)
-#define M821_BRG_4800           (520<<1)
-#define M821_BRG_2400           (1040<<1)
-#define M821_BRG_1200           (2082<<1)
-#define M821_BRG_600            ((259<<1) | 1)
-#define M821_BRG_300            ((520<<1) | 1)
-#define M821_BRG_150            ((1040<<1) | 1)
-#define M821_BRG_75             ((2080<<1) | 1)
-
-#define M821_TGCR_CAS4          (1<<15)   /* Cascade timers 3 and 4 */
-#define M821_TGCR_CAS2          (1<<7)    /* Cascade timers 1 and 2 */
-#define M821_TGCR_FRZ1          (1<<2)    /* Halt timer if FREEZE asserted */
-#define M821_TGCR_FRZ2          (1<<6)    /* Halt timer if FREEZE asserted */
-#define M821_TGCR_FRZ3          (1<<10)   /* Halt timer if FREEZE asserted */
-#define M821_TGCR_FRZ4          (1<<14)   /* Halt timer if FREEZE asserted */
-#define M821_TGCR_STP1          (1<<1)    /* Stop timer */
-#define M821_TGCR_STP2          (1<<5)    /* Stop timer */
-#define M821_TGCR_STP3          (1<<9)    /* Stop timer */
-#define M821_TGCR_STP4          (1<<13)   /* Stop timer */
-#define M821_TGCR_RST1          (1<<0)    /* Enable timer */
-#define M821_TGCR_RST2          (1<<4)    /* Enable timer */
-#define M821_TGCR_RST3          (1<<8)    /* Enable timer */
-#define M821_TGCR_RST4          (1<<12)   /* Enable timer */
-#define M821_TGCR_GM1           (1<<3)    /* Gate Mode 1 for TMR1 or TMR2 */
-#define M821_TGCR_GM2           (1<<11)   /* Gate Mode 2 for TMR3 or TMR4 */
-
-#define M821_TMR_PS(x)          ((x)<<8)  /* Timer prescaler */
-#define M821_TMR_CE_RISE        (1<<6)    /* Capture on rising edge */
-#define M821_TMR_CE_FALL        (2<<6)    /* Capture on falling edge */
-#define M821_TMR_CE_ANY         (3<<6)    /* Capture on any edge */
-#define M821_TMR_OM_TOGGLE      (1<<5)    /* Toggle TOUTx pin */
-#define M821_TMR_ORI            (1<<4)    /* Interrupt on reaching reference */
-#define M821_TMR_RESTART        (1<<3)    /* Restart timer after reference */
-#define M821_TMR_ICLK_INT       (1<<1)    /* Internal clock is timer source */
-#define M821_TMR_ICLK_INT16     (2<<1)    /* Internal clock/16 is tmr src */
-#define M821_TMR_ICLK_TIN       (3<<1)    /* TIN pin is timer source */
-#define M821_TMR_TGATE          (1<<0)    /* TGATE controls timer */
-
-#define M821_PISCR_PIRQ(x)      (1<<(15-x))  /* PIT interrupt level */
-#define M821_PISCR_PS           (1<<7)    /* PIT Interrupt state */
-#define M821_PISCR_PIE          (1<<2)    /* PIT interrupt enable */
-#define M821_PISCR_PITF         (1<<1)    /* Stop timer when freeze asserted */
-#define M821_PISCR_PTE          (1<<0)    /* PIT enable */
-
-#define M821_TBSCR_TBIRQ(x)     (1<<(15-x))  /* TB interrupt level */
-#define M821_TBSCR_REFA         (1<<7)    /* TB matches TBREFF0 */
-#define M821_TBSCR_REFB         (1<<6)    /* TB matches TBREFF1 */
-#define M821_TBSCR_REFAE        (1<<3)    /* Enable ints for REFA */
-#define M821_TBSCR_REFBE        (1<<2)    /* Enable ints for REFB */
-#define M821_TBSCR_TBF          (1<<1)    /* TB stops on FREEZE */
-#define M821_TBSCR_TBE          (1<<0)    /* enable TB and decrementer */
-
-#define M821_SIMASK_IRM0        (1<<31)
-#define M821_SIMASK_LVM0        (1<<30)
-#define M821_SIMASK_IRM1        (1<<29)
-#define M821_SIMASK_LVM1        (1<<28)
-#define M821_SIMASK_IRM2        (1<<27)
-#define M821_SIMASK_LVM2        (1<<26)
-#define M821_SIMASK_IRM3        (1<<25)
-#define M821_SIMASK_LVM3        (1<<24)
-#define M821_SIMASK_IRM4        (1<<23)
-#define M821_SIMASK_LVM4        (1<<22)
-#define M821_SIMASK_IRM5        (1<<21)
-#define M821_SIMASK_LVM5        (1<<20)
-#define M821_SIMASK_IRM6        (1<<19)
-#define M821_SIMASK_LVM6        (1<<18)
-#define M821_SIMASK_IRM7        (1<<17)
-#define M821_SIMASK_LVM7        (1<<16)
-
-#define M821_SIUMCR_EARB        (1<<31)
-#define M821_SIUMCR_EARP0       (0<<28)
-#define M821_SIUMCR_EARP1       (1<<28)
-#define M821_SIUMCR_EARP2       (2<<28)
-#define M821_SIUMCR_EARP3       (3<<28)
-#define M821_SIUMCR_EARP4       (4<<28)
-#define M821_SIUMCR_EARP5       (5<<28)
-#define M821_SIUMCR_EARP6       (6<<28)
-#define M821_SIUMCR_EARP7       (7<<28)
-#define M821_SIUMCR_DSHW        (1<<23)
-#define M821_SIUMCR_DBGC0       (0<<21)
-#define M821_SIUMCR_DBGC1       (1<<21)
-#define M821_SIUMCR_DBGC2       (2<<21)
-#define M821_SIUMCR_DBGC3       (3<<21)
-#define M821_SIUMCR_DBPC0       (0<<19)
-#define M821_SIUMCR_DBPC1       (1<<19)
-#define M821_SIUMCR_DBPC2       (2<<19)
-#define M821_SIUMCR_DBPC3       (3<<19)
-#define M821_SIUMCR_FRC         (1<<17)
-#define M821_SIUMCR_DLK         (1<<16)
-#define M821_SIUMCR_PNCS        (1<<15)
-#define M821_SIUMCR_OPAR        (1<<14)
-#define M821_SIUMCR_DPC         (1<<13)
-#define M821_SIUMCR_MPRE        (1<<12)
-#define M821_SIUMCR_MLRC0       (0<<10)
-#define M821_SIUMCR_MLRC1       (1<<10)
-#define M821_SIUMCR_MLRC2       (2<<10)
-#define M821_SIUMCR_MLRC3       (3<<10)
-#define M821_SIUMCR_AEME        (1<<9)
-#define M821_SIUMCR_SEME        (1<<8)
-#define M821_SIUMCR_BSC         (1<<7)
-#define M821_SIUMCR_GB5E        (1<<6)
-#define M821_SIUMCR_B2DD        (1<<5)
-#define M821_SIUMCR_B3DD        (1<<4)
-/*
-*************************************************************************
-*                 MPC821 DUAL-PORT RAM AND REGISTERS                    *
-*************************************************************************
-*/
-typedef struct m821_ {
-        
-  /*
-   * SIU Block
-   */
-  rtems_unsigned32      siumcr;
-  rtems_unsigned32      sypcr;
-  rtems_unsigned32      _pad70;
-  rtems_unsigned16      _pad0;
-  rtems_unsigned16      swsr;
-  rtems_unsigned32      sipend;
-  rtems_unsigned32      simask;
-  rtems_unsigned32      siel;
-  rtems_unsigned32      sivec;
-  rtems_unsigned32      tesr;
-  rtems_unsigned32      _pad1[3];
-  rtems_unsigned32      sdcr;
-  rtems_unsigned8       _pad2[0x80-0x34];
-  
-  /*
-   * PCMCIA Block
-   */
-  rtems_unsigned32      pbr0;
-  rtems_unsigned32      por0;
-  rtems_unsigned32      pbr1;
-  rtems_unsigned32      por1;
-  rtems_unsigned32      pbr2;
-  rtems_unsigned32      por2;
-  rtems_unsigned32      pbr3;
-  rtems_unsigned32      por3;
-  rtems_unsigned32      pbr4;
-  rtems_unsigned32      por4;
-  rtems_unsigned32      pbr5;
-  rtems_unsigned32      por5;
-  rtems_unsigned32      pbr6;
-  rtems_unsigned32      por6;
-  rtems_unsigned32      pbr7;
-  rtems_unsigned32      por7;
-  rtems_unsigned8       _pad3[0xe0-0xc0];
-  rtems_unsigned32      pgcra;
-  rtems_unsigned32      pgcrb;
-  rtems_unsigned32      pscr;
-  rtems_unsigned32      _pad4;
-  rtems_unsigned32      pipr;
-  rtems_unsigned32      _pad5;
-  rtems_unsigned32      per;
-  rtems_unsigned32      _pad6;
-  
-  /*
-   * MEMC Block
-   */
-  m821MEMCRegisters_t   memc[8];
-  rtems_unsigned8       _pad7[0x164-0x140];
-  rtems_unsigned32      mar;
-  rtems_unsigned32      mcr;
-  rtems_unsigned32      _pad8;
-  rtems_unsigned32      mamr;
-  rtems_unsigned32      mbmr;
-  rtems_unsigned16      mstat;
-  rtems_unsigned16      mptpr;
-  rtems_unsigned32      mdr;
-  rtems_unsigned8       _pad9[0x200-0x180];
-  
-  /*
-   * System integration timers
-   */
-  rtems_unsigned16      tbscr;
-  rtems_unsigned16      _pad10;
-  rtems_unsigned32      tbreff0;
-  rtems_unsigned32      tbreff1;
-  rtems_unsigned8       _pad11[0x220-0x20c];
-  rtems_unsigned16      rtcsc;
-  rtems_unsigned16      _pad12;
-  rtems_unsigned32      rtc;
-  rtems_unsigned32      rtsec;
-  rtems_unsigned32      rtcal;
-  rtems_unsigned32      _pad13[4];
-  rtems_unsigned16      piscr;
-  rtems_unsigned16      _pad14;
-  rtems_unsigned16      pitc;
-  rtems_unsigned16      _pad_14_1;
-  rtems_unsigned16      pitr;
-  rtems_unsigned16      _pad_14_2;
-  rtems_unsigned8       _pad15[0x280-0x24c];
-  
-  
-  /*
-   * Clocks and Reset
-   */
-  rtems_unsigned32      sccr;
-  rtems_unsigned32      plprcr;
-  rtems_unsigned32      rsr;
-  rtems_unsigned8       _pad16[0x300-0x28c];
-  
-  
-  /*
-   * System integration timers keys
-   */
-  rtems_unsigned32      tbscrk;
-  rtems_unsigned32      tbreff0k;
-  rtems_unsigned32      tbreff1k;
-  rtems_unsigned32      tbk;
-  rtems_unsigned32      _pad17[4];
-  rtems_unsigned32      rtcsk;
-  rtems_unsigned32      rtck;
-  rtems_unsigned32      rtseck;
-  rtems_unsigned32      rtcalk;
-  rtems_unsigned32      _pad18[4];
-  rtems_unsigned32      piscrk;
-  rtems_unsigned32      pitck;
-  rtems_unsigned8       _pad19[0x380-0x348];
-  
-  /*
-   * Clocks and Reset Keys
-   */
-  rtems_unsigned32      sccrk;
-  rtems_unsigned32      plprck;
-  rtems_unsigned32      rsrk;
-  rtems_unsigned8       _pad20[0x400-0x38c];
-  rtems_unsigned8       _pad21[0x800-0x400];
-  rtems_unsigned8       _pad22[0x860-0x800];
-  
-  
-  /*
-   * I2C
-   */
-  rtems_unsigned8       i2mod;
-  rtems_unsigned8       _pad23[3];
-  rtems_unsigned8       i2add;
-  rtems_unsigned8       _pad24[3];
-  rtems_unsigned8       i2brg;
-  rtems_unsigned8       _pad25[3];
-  rtems_unsigned8       i2com;
-  rtems_unsigned8       _pad26[3];
-  rtems_unsigned8       i2cer;
-  rtems_unsigned8       _pad27[3];
-  rtems_unsigned8       i2cmr;
-  rtems_unsigned8       _pad28[0x900-0x875];
-  
-  /*
-   * DMA Block
-   */
-  rtems_unsigned32      _pad29;
-  rtems_unsigned32      sdar;
-  rtems_unsigned8       sdsr;
-  rtems_unsigned8       _pad30[3];
-  rtems_unsigned8       sdmr;
-  rtems_unsigned8       _pad31[3];
-  rtems_unsigned8       idsr1;
-  rtems_unsigned8       _pad32[3];
-  rtems_unsigned8       idmr1;
-  rtems_unsigned8       _pad33[3];
-  rtems_unsigned8       idsr2;
-  rtems_unsigned8       _pad34[3];
-  rtems_unsigned8       idmr2;
-  rtems_unsigned8       _pad35[0x930-0x91d];
-  
-  
-  
-  /*
-   * CPM Interrupt Control Block
-   */
-  rtems_unsigned16      civr;
-  rtems_unsigned8       _pad36[14];
-  rtems_unsigned32      cicr;
-  rtems_unsigned32      cipr;
-  rtems_unsigned32      cimr;
-  rtems_unsigned32      cisr;
-  
-  /*
-   * I/O Port Block
-   */
-  rtems_unsigned16      padir;
-  rtems_unsigned16      papar;
-  rtems_unsigned16      paodr;
-  rtems_unsigned16      padat;
-  rtems_unsigned8       _pad37[8];
-  rtems_unsigned16      pcdir;
-  rtems_unsigned16      pcpar;
-  rtems_unsigned16      pcso;
-  rtems_unsigned16      pcdat;
-  rtems_unsigned16      pcint;
-  rtems_unsigned8       _pad39[6];
-  rtems_unsigned16      pddir;
-  rtems_unsigned16      pdpar;
-  rtems_unsigned16      _pad40;
-  rtems_unsigned16      pddat;
-  rtems_unsigned8       _pad41[8];
-  
-  /*
-   * CPM Timers Block
-   */
-  rtems_unsigned16      tgcr;
-  rtems_unsigned8       _pad42[14];
-  rtems_unsigned16      tmr1;
-  rtems_unsigned16      tmr2;
-  rtems_unsigned16      trr1;
-  rtems_unsigned16      trr2;
-  rtems_unsigned16      tcr1;
-  rtems_unsigned16      tcr2;
-  rtems_unsigned16      tcn1;
-  rtems_unsigned16      tcn2;
-  rtems_unsigned16      tmr3;
-  rtems_unsigned16      tmr4;
-  rtems_unsigned16      trr3;
-  rtems_unsigned16      trr4;
-  rtems_unsigned16      tcr3;
-  rtems_unsigned16      tcr4;
-  rtems_unsigned16      tcn3;
-  rtems_unsigned16      tcn4;
-  rtems_unsigned16      ter1;
-  rtems_unsigned16      ter2;
-  rtems_unsigned16      ter3;
-  rtems_unsigned16      ter4;
-  rtems_unsigned8       _pad43[8];
-  
-  
-  
-  /*
-   * CPM Block
-   */
-  rtems_unsigned16      cpcr;
-  rtems_unsigned16      _pad44;
-  rtems_unsigned16      rccr;
-  rtems_unsigned8       _pad45;
-  rtems_unsigned8       rmds;
-  rtems_unsigned32      rmdr;
-  rtems_unsigned16      rctr1;
-  rtems_unsigned16      rctr2;
-  rtems_unsigned16      rctr3;
-  rtems_unsigned16      rctr4;
-  rtems_unsigned16      _pad46;
-  rtems_unsigned16      rter;
-  rtems_unsigned16      _pad47;
-  rtems_unsigned16      rtmr;
-  rtems_unsigned8       _pad48[0x9f0-0x9dc];
-  
-  /*
-   * BRG Block
-   */
-  rtems_unsigned32      brgc1;
-  rtems_unsigned32      brgc2;
-  rtems_unsigned32      brgc3;
-  rtems_unsigned32      brgc4;
-  
-  /*
-   * SCC Block
-   */
-  m821SCCRegisters_t    scc1;
-  m821SCCRegisters_t    scc2;
-  rtems_unsigned8	_pad72[0xa80-0xa40];
-  
-  /*
-   * SMC Block
-   */
-  m821SMCRegisters_t    smc1;
-  m821SMCRegisters_t    smc2;
-  
-  /*
-   * SPI Block
-   */
-  rtems_unsigned16      spmode;
-  rtems_unsigned16      _pad49[2];
-  rtems_unsigned8       spie;
-  rtems_unsigned8       _pad50;
-  rtems_unsigned16      _pad51;
-  rtems_unsigned8       spim;
-  rtems_unsigned8       _pad52[2];
-  rtems_unsigned8       spcom;
-  rtems_unsigned16      _pad53[2];
-  
-  /*
-   * PIP Block
-   */
-  rtems_unsigned16      pipc;
-  rtems_unsigned16      _pad54;
-  rtems_unsigned16      ptpr;
-  rtems_unsigned32      pbdir;
-  rtems_unsigned32      pbpar;
-  rtems_unsigned16      _pad55;
-  rtems_unsigned16      pbodr;
-  rtems_unsigned32      pbdat;
-  rtems_unsigned32      _pad56[6];
-  
-  /*
-   * SI Block
-   */
-  rtems_unsigned32      simode;
-  rtems_unsigned8       sigmr;
-  rtems_unsigned8       _pad57;
-  rtems_unsigned8       sistr;
-  rtems_unsigned8       sicmr;
-  rtems_unsigned32      _pad58;
-  rtems_unsigned32      sicr;
-  rtems_unsigned16      sirp[2];
-  rtems_unsigned32      _pad59[3];
-  rtems_unsigned8       _pad60[0xc00-0xb00];
-  rtems_unsigned8       siram[512];
-  rtems_unsigned8       lcdram[512];
-
-  rtems_unsigned8       _pad62[0x2000-0x1000];
-  /*
-   * Dual-port RAM
-   */
-  rtems_unsigned8       dpram0[0x200];  /* BD/DATA/UCODE */
-  rtems_unsigned8       dpram1[0x200];  /* BD/DATA/UCODE */
-  rtems_unsigned8       dpram2[0x400];  /* BD/DATA/UCODE */
-  rtems_unsigned8       dpram3[0x600];  /* BD/DATA*/
-  rtems_unsigned8       dpram4[0x200];  /* BD/DATA/UCODE */
-  rtems_unsigned8       _pad63[0x3c00-0x3000];
-  
-  /* When using SCC1 for ethernet, we lose the use of I2C since
-   *  their parameters would overlap. Motorola has a microcode
-   *  patch to move parameters around so that both can be used
-   *  together. It is available on their web site somewhere 
-   *  under http://www.mot.com/mpc821. If ethernet is used on
-   *  one (or more) of the other SCCs, then other CPM features
-   *  will be unavailable:
-   *    SCC2    -> lose SPI
-   *  However, Ethernet only works on SCC1 on the 821.
-   */
-  m821SCCENparms_t      scc1p;
-  rtems_unsigned8       _rsv1[0xCB0-0xC00-sizeof(m821SCCENparms_t)];
-  m821MiscParms_t       miscp;
-  rtems_unsigned8       _rsv2[0xcc0-0xCB0-sizeof(m821MiscParms_t)];
-  m821IDMAparms_t       idma1p;
-  rtems_unsigned8       _rsv3[0xd00-0xcc0-sizeof(m821IDMAparms_t)];
-  
-  m821SCCparms_t        scc2p;
-  rtems_unsigned8       _rsv4[0xD80-0xD00-sizeof(m821SCCparms_t)];
-  m821SPIparms_t        spip;
-  rtems_unsigned8       _rsv5[0xDB0-0xD80-sizeof(m821SPIparms_t)];
-  m821TimerParms_t      tmp;
-  rtems_unsigned8       _rsv6[0xDC0-0xDB0-sizeof(m821TimerParms_t)];
-  m821IDMAparms_t       idma2p;
-  rtems_unsigned8       _rsv7[0xE00-0xDC0-sizeof(m821IDMAparms_t)];
-  
-  m821SCCparms_t        scc3p; /* Not used */
-  rtems_unsigned8       _rsv8[0xE80-0xE00-sizeof(m821SCCparms_t)];
-  m821SMCparms_t        smc1p;
-  rtems_unsigned8       _rsv9[0xEC0-0xE80-sizeof(m821SMCparms_t)];
-  m821DSPparms_t        dsp1p;
-  rtems_unsigned8       _rsv10[0xF00-0xEC0-sizeof(m821DSPparms_t)];
-  
-  m821SCCparms_t        scc4p; /* Not used */
-  rtems_unsigned8       _rsv11[0xF80-0xF00-sizeof(m821SCCparms_t)];
-  m821SMCparms_t        smc2p;
-  rtems_unsigned8       _rsv12[0xFC0-0xF80-sizeof(m821SMCparms_t)];
-  m821DSPparms_t        dsp2p;
-  rtems_unsigned8       _rsv13[0x1000-0xFC0-sizeof(m821DSPparms_t)];
-} m821_t;
-
-extern volatile m821_t m821;
-#endif /* ASM */
-
-#endif /* __MPC821_h */
diff --git a/c/src/exec/score/cpu/powerpc/mpc860.h b/c/src/exec/score/cpu/powerpc/mpc860.h
deleted file mode 100644
index 7daee45bf0..0000000000
--- a/c/src/exec/score/cpu/powerpc/mpc860.h
+++ /dev/null
@@ -1,1300 +0,0 @@
-/*
-**************************************************************************
-**************************************************************************
-**                                                                      **
-**  MOTOROLA MPC860 POWER QUAD INTEGRATED COMMUNICATIONS CONTROLLER     **
-**                             POWERQUICC                               **
-**                                                                      **
-**                        HARDWARE DECLARATIONS                         **
-**                                                                      **
-**                                                                      **
-**  Submitted By:                                                       **
-**                                                                      **
-**      W. Eric Norum                                                   **
-**      Saskatchewan Accelerator Laboratory                             **
-**      University of Saskatchewan                                      **
-**      107 North Road                                                  **
-**      Saskatoon, Saskatchewan, CANADA                                 **
-**      S7N 5C6                                                         **
-**                                                                      **
-**      eric@skatter.usask.ca                                           **
-**                                                                      **
-**  Modified for use with the MPC860 (original code was for MC68360)    **
-**  by                                                                  **
-**      Jay Monkman                                                     **
-**      Frasca International, Inc.                                      **
-**      906 E. Airport Rd.                                              **
-**      Urbana, IL, 61801                                               **
-**                                                                      **
-**      jmonkman@frasca.com                                             **
-**                                                                      **
-**************************************************************************
-**************************************************************************
-*/
-
-#ifndef __MPC860_h
-#define __MPC860_h
-
-#ifndef ASM
-/*
-  Macros for SPRs
-*/
-
-#define M860_MI_CTR_GPM       (1<<31)
-#define M860_MI_CTR_PPM       (1<<30)
-#define M860_MI_CTR_CIDEF     (1<<29)
-#define M860_MI_CTR_RSV4I     (1<<27)
-#define M860_MI_CTR_PPCS      (1<<25)
-
-#define M860_MD_CTR_GPM       (1<<31)
-#define M860_MD_CTR_PPM       (1<<30)
-#define M860_MD_CTR_CIDEF     (1<<29)
-#define M860_MD_CTR_WTDEF     (1<<28)
-#define M860_MD_CTR_RSV4D     (1<<27)
-#define M860_MD_CTR_TWAM      (1<<26)
-#define M860_MD_CTR_PPCS      (1<<25)
-
-#define M860_MI_EPN_VALID     (1<<9)
-
-#define M860_MD_EPN_VALID     (1<<9)
-
-#define M860_MI_TWC_G         (1<<4)
-#define M860_MI_TWC_PSS       (0<<2)
-#define M860_MI_TWC_PS512     (1<<2)
-#define M860_MI_TWC_PS8       (3<<2)
-#define M860_MI_TWC_VALID     (1)
-
-#define M860_MD_TWC_G         (1<<4)
-#define M860_MD_TWC_PSS       (0<<2)
-#define M860_MD_TWC_PS512     (1<<2)
-#define M860_MD_TWC_PS8       (3<<2)
-#define M860_MD_TWC_WT        (1<<1)
-#define M860_MD_TWC_VALID     (1)
-
-#define M860_MI_RPN_F         (0xf<<4)
-#define M860_MI_RPN_16K       (1<<3)
-#define M860_MI_RPN_SHARED    (1<<2)
-#define M860_MI_RPN_CI        (1<<1)
-#define M860_MI_RPN_VALID     (1)
-
-#define M860_MD_RPN_CHANGE    (1<<8)
-#define M860_MD_RPN_F         (0xf<<4)
-#define M860_MD_RPN_16K       (1<<3)
-#define M860_MD_RPN_SHARED    (1<<2)
-#define M860_MD_RPN_CI        (1<<1)
-#define M860_MD_RPN_VALID     (1)
-
-#define M860_MI_AP_Kp         (1)
-
-#define M860_MD_AP_Kp         (1)
-
-#define M860_CACHE_CMD_SFWT          (0x1<<24)
-#define M860_CACHE_CMD_ENABLE        (0x2<<24)
-#define M860_CACHE_CMD_CFWT          (0x3<<24)
-#define M860_CACHE_CMD_DISABLE       (0x4<<24)
-#define M860_CACHE_CMD_STLES         (0x5<<24)
-#define M860_CACHE_CMD_LLCB          (0x6<<24)
-#define M860_CACHE_CMD_CLES          (0x7<<24)
-#define M860_CACHE_CMD_UNLOCK        (0x8<<24)
-#define M860_CACHE_CMD_UNLOCKALL     (0xa<<24)
-#define M860_CACHE_CMD_INVALIDATE    (0xc<<24)
-#define M860_CACHE_CMD_FLUSH         (0xe<<24)
-
-
-
-/*
-*************************************************************************
-*                         REGISTER SUBBLOCKS                            *
-*************************************************************************
-*/
-
-/*
- * Memory controller registers
- */
-typedef struct m860MEMCRegisters_ {
-  rtems_unsigned32        br;
-  rtems_unsigned32        or;
-} m860MEMCRegisters_t;
-
-/*
- * Serial Communications Controller registers
- */
-typedef struct m860SCCRegisters_ {
-  rtems_unsigned32        gsmr_l;
-  rtems_unsigned32        gsmr_h;
-  rtems_unsigned16        psmr;
-  rtems_unsigned16        _pad0;
-  rtems_unsigned16        todr;
-  rtems_unsigned16        dsr;
-  rtems_unsigned16        scce;
-  rtems_unsigned16        _pad1;
-  rtems_unsigned16        sccm;
-  rtems_unsigned8         _pad2;
-  rtems_unsigned8         sccs;
-  rtems_unsigned32        _pad3[2];
-} m860SCCRegisters_t;
-
-/*
- * Serial Management Controller registers
- */
-typedef struct m860SMCRegisters_ {
-  rtems_unsigned16        _pad0;
-  rtems_unsigned16        smcmr;
-  rtems_unsigned16        _pad1;
-  rtems_unsigned8         smce;
-  rtems_unsigned8         _pad2;
-  rtems_unsigned16        _pad3;
-  rtems_unsigned8         smcm;
-  rtems_unsigned8         _pad4;
-  rtems_unsigned32        _pad5;
-} m860SMCRegisters_t;
-
-/*
- * Fast Ethernet Controller registers (Only on MPC860T)
- */
-typedef struct m860FECRegisters_ {
-  rtems_unsigned32    addr_low;
-  rtems_unsigned32    addr_high;
-  rtems_unsigned32    hash_table_high;
-  rtems_unsigned32    hash_table_low;
-  rtems_unsigned32    r_des_start;
-  rtems_unsigned32    x_des_start;
-  rtems_unsigned32    r_buf_size;
-  rtems_unsigned32    _pad0[9];
-  rtems_unsigned32    ecntrl;
-  rtems_unsigned32    ievent;
-  rtems_unsigned32    imask;
-  rtems_unsigned32    ivec;
-  rtems_unsigned32    r_des_active;
-  rtems_unsigned32    x_des_active;
-  rtems_unsigned32    _pad1[10];
-  rtems_unsigned32    mii_data;
-  rtems_unsigned32    mii_speed;
-  rtems_unsigned32    _pad2[17];
-  rtems_unsigned32    r_bound;
-  rtems_unsigned32    r_fstart;
-  rtems_unsigned32    _pad3[6];
-  rtems_unsigned32    x_fstart;
-  rtems_unsigned32    _pad4[17];
-  rtems_unsigned32    fun_code;
-  rtems_unsigned32    _pad5[3];
-  rtems_unsigned32    r_cntrl;
-  rtems_unsigned32    r_hash;
-  rtems_unsigned32    _pad6[14];
-  rtems_unsigned32    x_cntrl;
-  rtems_unsigned32    _pad7[30];
-
-} m860FECRegisters_t;
-
-#define M860_FEC_IEVENT_HBERR  (1 << 31)
-#define M860_FEC_IEVENT_BABR   (1 << 30)
-#define M860_FEC_IEVENT_BABT   (1 << 29)
-#define M860_FEC_IEVENT_GRA    (1 << 28)
-#define M860_FEC_IEVENT_TFINT  (1 << 27)
-#define M860_FEC_IEVENT_TXB    (1 << 26)
-#define M860_FEC_IEVENT_RFINT  (1 << 25)
-#define M860_FEC_IEVENT_RXB    (1 << 24)
-#define M860_FEC_IEVENT_MII    (1 << 23)
-#define M860_FEC_IEVENT_EBERR  (1 << 22)
-#define M860_FEC_IMASK_HBEEN   (1 << 31)
-#define M860_FEC_IMASK_BREEN   (1 << 30)
-#define M860_FEC_IMASK_BTEN    (1 << 29)
-#define M860_FEC_IMASK_GRAEN   (1 << 28)
-#define M860_FEC_IMASK_TFIEN   (1 << 27)
-#define M860_FEC_IMASK_TBIEN   (1 << 26)
-#define M860_FEC_IMASK_RFIEN   (1 << 25)
-#define M860_FEC_IMASK_RBIEN   (1 << 24)
-#define M860_FEC_IMASK_MIIEN   (1 << 23)
-#define M860_FEC_IMASK_EBERREN (1 << 22)
-
-
-/*
-*************************************************************************
-*                         Miscellaneous Parameters                      *
-*************************************************************************
-*/
-typedef struct m860MiscParms_ {
-  rtems_unsigned16        rev_num;
-  rtems_unsigned16        _res1;
-  rtems_unsigned32        _res2;
-  rtems_unsigned32        _res3;
-} m860MiscParms_t;
-
-/*
-*************************************************************************
-*                              RISC Timers                              *
-*************************************************************************
-*/
-typedef struct m860TimerParms_ {
-  rtems_unsigned16        tm_base;
-  rtems_unsigned16        _tm_ptr;
-  rtems_unsigned16        _r_tmr;
-  rtems_unsigned16        _r_tmv;
-  rtems_unsigned32        tm_cmd;
-  rtems_unsigned32        tm_cnt;
-} m860TimerParms_t;
-
-/*
- * RISC Controller Configuration Register (RCCR)
- * All other bits in this register are reserved.
- */
-#define M860_RCCR_TIME          (1<<15)    /* Enable timer */
-#define M860_RCCR_TIMEP(x)      ((x)<<8)   /* Timer period */
-#define M860_RCCR_DR1M          (1<<7)     /* IDMA Rqst 1 Mode */
-#define M860_RCCR_DR0M          (1<<6)     /* IDMA Rqst 0 Mode */
-#define M860_RCCR_DRQP(x)       ((x)<<4)   /* IDMA Rqst Priority */
-#define M860_RCCR_EIE           (1<<3)     /* External Interrupt Enable */
-#define M860_RCCR_SCD           (1<<2)     /* Scheduler Configuration */
-#define M860_RCCR_ERAM(x)       (x)        /* Enable RAM Microcode */
-
-/*
- * Command register
- * Set up this register before issuing a M860_CR_OP_SET_TIMER command.
- */
-#define M860_TM_CMD_V           (1<<31)         /* Set to enable timer */
-#define M860_TM_CMD_R           (1<<30)         /* Set for automatic restart */
-#define M860_TM_CMD_PWM         (1<<29)         /* Set for PWM operation */
-#define M860_TM_CMD_TIMER(x)    ((x)<<16)       /* Select timer */
-#define M860_TM_CMD_PERIOD(x)   (x)             /* Timer period (16 bits) */
-
-/*
-*************************************************************************
-*                               DMA Controllers                         *
-*************************************************************************
-*/
-typedef struct m860IDMAparms_ {
-  rtems_unsigned16        ibase;
-  rtems_unsigned16        dcmr;
-  rtems_unsigned32        _sapr;
-  rtems_unsigned32        _dapr;
-  rtems_unsigned16        ibptr;
-  rtems_unsigned16        _write_sp;
-  rtems_unsigned32        _s_byte_c;
-  rtems_unsigned32        _d_byte_c;
-  rtems_unsigned32        _s_state;
-  rtems_unsigned32        _itemp[4];
-  rtems_unsigned32        _sr_mem;
-  rtems_unsigned16        _read_sp;
-  rtems_unsigned16        _res0;
-  rtems_unsigned16        _res1;
-  rtems_unsigned16        _res2;
-  rtems_unsigned32        _d_state;
-} m860IDMAparms_t;
-
-
-/*
-*************************************************************************
-*                               DSP                                     *
-*************************************************************************
-*/
-typedef struct m860DSPparms_ {
-  rtems_unsigned32        fdbase;
-  rtems_unsigned32        _fd_ptr;
-  rtems_unsigned32        _dstate;
-  rtems_unsigned32        _pad0;
-  rtems_unsigned16        _dstatus;
-  rtems_unsigned16        _i;
-  rtems_unsigned16        _tap;
-  rtems_unsigned16        _cbase;
-  rtems_unsigned16        _pad1;
-  rtems_unsigned16        _xptr;
-  rtems_unsigned16        _pad2;
-  rtems_unsigned16        _yptr;
-  rtems_unsigned16        _m;
-  rtems_unsigned16        _pad3;
-  rtems_unsigned16        _n;
-  rtems_unsigned16        _pad4;
-  rtems_unsigned16        _k;
-  rtems_unsigned16        _pad5;
-} m860DSPparms_t;
-
-/*
-*************************************************************************
-*                   Serial Communication Controllers                    *
-*************************************************************************
-*/
-typedef struct m860SCCparms_ {
-  rtems_unsigned16        rbase;
-  rtems_unsigned16        tbase;
-  rtems_unsigned8         rfcr;
-  rtems_unsigned8         tfcr;
-  rtems_unsigned16        mrblr;
-  rtems_unsigned32        _rstate;
-  rtems_unsigned32        _pad0;
-  rtems_unsigned16        _rbptr;
-  rtems_unsigned16        _pad1;
-  rtems_unsigned32        _pad2;
-  rtems_unsigned32        _tstate;
-  rtems_unsigned32        _pad3;
-  rtems_unsigned16        _tbptr;
-  rtems_unsigned16        _pad4;
-  rtems_unsigned32        _pad5;
-  rtems_unsigned32        _rcrc;
-  rtems_unsigned32        _tcrc;
-  union {
-    struct {
-      rtems_unsigned32        _res0;
-      rtems_unsigned32        _res1;
-      rtems_unsigned16        max_idl;
-      rtems_unsigned16        _idlc;
-      rtems_unsigned16        brkcr;
-      rtems_unsigned16        parec;
-      rtems_unsigned16        frmec;
-      rtems_unsigned16        nosec;
-      rtems_unsigned16        brkec;
-      rtems_unsigned16        brklen;
-      rtems_unsigned16        uaddr[2];
-      rtems_unsigned16        _rtemp;
-      rtems_unsigned16        toseq;
-      rtems_unsigned16        character[8];
-      rtems_unsigned16        rccm;
-      rtems_unsigned16        rccr;
-      rtems_unsigned16        rlbc;
-    } uart;
-  } un;
-} m860SCCparms_t;
-
-typedef struct m860SCCENparms_ {
-  rtems_unsigned16        rbase;
-  rtems_unsigned16        tbase;
-  rtems_unsigned8         rfcr;
-  rtems_unsigned8         tfcr;
-  rtems_unsigned16        mrblr;
-  rtems_unsigned32        _rstate;
-  rtems_unsigned32        _pad0;
-  rtems_unsigned16        _rbptr;
-  rtems_unsigned16        _pad1;
-  rtems_unsigned32        _pad2;
-  rtems_unsigned32        _tstate;
-  rtems_unsigned32        _pad3;
-  rtems_unsigned16        _tbptr;
-  rtems_unsigned16        _pad4;
-  rtems_unsigned32        _pad5;
-  rtems_unsigned32        _rcrc;
-  rtems_unsigned32        _tcrc;
-  union {
-    struct {
-      rtems_unsigned32        _res0;
-      rtems_unsigned32        _res1;
-      rtems_unsigned16        max_idl;
-      rtems_unsigned16        _idlc;
-      rtems_unsigned16        brkcr;
-      rtems_unsigned16        parec;
-      rtems_unsigned16        frmec;
-      rtems_unsigned16        nosec;
-      rtems_unsigned16        brkec;
-      rtems_unsigned16        brklen;
-      rtems_unsigned16        uaddr[2];
-      rtems_unsigned16        _rtemp;
-      rtems_unsigned16        toseq;
-      rtems_unsigned16        character[8];
-      rtems_unsigned16        rccm;
-      rtems_unsigned16        rccr;
-      rtems_unsigned16        rlbc;
-    } uart;
-    struct {
-      rtems_unsigned32        c_pres;
-      rtems_unsigned32        c_mask;
-      rtems_unsigned32        crcec;
-      rtems_unsigned32        alec;
-      rtems_unsigned32        disfc;
-      rtems_unsigned16        pads;
-      rtems_unsigned16        ret_lim;
-      rtems_unsigned16        _ret_cnt;
-      rtems_unsigned16        mflr;
-      rtems_unsigned16        minflr;
-      rtems_unsigned16        maxd1;
-      rtems_unsigned16        maxd2;
-      rtems_unsigned16        _maxd;
-      rtems_unsigned16        dma_cnt;
-      rtems_unsigned16        _max_b;
-      rtems_unsigned16        gaddr1;
-      rtems_unsigned16        gaddr2;
-      rtems_unsigned16        gaddr3;
-      rtems_unsigned16        gaddr4;
-      rtems_unsigned32        _tbuf0data0;
-      rtems_unsigned32        _tbuf0data1;
-      rtems_unsigned32        _tbuf0rba0;
-      rtems_unsigned32        _tbuf0crc;
-      rtems_unsigned16        _tbuf0bcnt;
-      rtems_unsigned16        paddr_h;
-      rtems_unsigned16        paddr_m;
-      rtems_unsigned16        paddr_l;
-      rtems_unsigned16        p_per;
-      rtems_unsigned16        _rfbd_ptr;
-      rtems_unsigned16        _tfbd_ptr;
-      rtems_unsigned16        _tlbd_ptr;
-      rtems_unsigned32        _tbuf1data0;
-      rtems_unsigned32        _tbuf1data1;
-      rtems_unsigned32        _tbuf1rba0;
-      rtems_unsigned32        _tbuf1crc;
-      rtems_unsigned16        _tbuf1bcnt;
-      rtems_unsigned16        _tx_len;
-      rtems_unsigned16        iaddr1;
-      rtems_unsigned16        iaddr2;
-      rtems_unsigned16        iaddr3;
-      rtems_unsigned16        iaddr4;
-      rtems_unsigned16        _boff_cnt;
-      rtems_unsigned16        taddr_l;
-      rtems_unsigned16        taddr_m;
-      rtems_unsigned16        taddr_h;
-    } ethernet;
-  } un;
-} m860SCCENparms_t;
-
-/*
- * Receive and transmit function code register bits
- * These apply to the function code registers of all devices, not just SCC.
- */
-#define M860_RFCR_BO(x)         ((x)<<3)
-#define M860_RFCR_MOT           (2<<3)
-#define M860_RFCR_DMA_SPACE(x)  (x)
-#define M860_TFCR_BO(x)         ((x)<<3)
-#define M860_TFCR_MOT           (2<<3)
-#define M860_TFCR_DMA_SPACE(x)  (x)
-
-/*
-*************************************************************************
-*                     Serial Management Controllers                     *
-*************************************************************************
-*/
-typedef struct m860SMCparms_ {
-  rtems_unsigned16        rbase;
-  rtems_unsigned16        tbase;
-  rtems_unsigned8         rfcr;
-  rtems_unsigned8         tfcr;
-  rtems_unsigned16        mrblr;
-  rtems_unsigned32        _rstate;
-  rtems_unsigned32        _pad0;
-  rtems_unsigned16        _rbptr;
-  rtems_unsigned16        _pad1;
-  rtems_unsigned32        _pad2;
-  rtems_unsigned32        _tstate;
-  rtems_unsigned32        _pad3;
-  rtems_unsigned16        _tbptr;
-  rtems_unsigned16        _pad4;
-  rtems_unsigned32        _pad5;
-  union {
-    struct {
-      rtems_unsigned16        max_idl;
-      rtems_unsigned16        _idlc;
-      rtems_unsigned16        brklen;
-      rtems_unsigned16        brkec;
-      rtems_unsigned16        brkcr;
-      rtems_unsigned16        _r_mask;
-    } uart;
-    struct {
-      rtems_unsigned16        _pad0[5];
-    } transparent;
-  } un;
-} m860SMCparms_t;
-
-/*
- * Mode register
- */
-#define M860_SMCMR_CLEN(x)              ((x)<<11)    /* Character length */
-#define M860_SMCMR_2STOP                (1<<10)      /* 2 stop bits */
-#define M860_SMCMR_PARITY               (1<<9)       /* Enable parity */
-#define M860_SMCMR_EVEN                 (1<<8)       /* Even parity */
-#define M860_SMCMR_SM_GCI               (0<<4)       /* GCI Mode */
-#define M860_SMCMR_SM_UART              (2<<4)       /* UART Mode */
-#define M860_SMCMR_SM_TRANSPARENT       (3<<4)       /* Transparent Mode */
-#define M860_SMCMR_DM_LOOPBACK          (1<<2)       /* Local loopback mode */
-#define M860_SMCMR_DM_ECHO              (2<<2)       /* Echo mode */
-#define M860_SMCMR_TEN                  (1<<1)       /* Enable transmitter */
-#define M860_SMCMR_REN                  (1<<0)       /* Enable receiver */
-
-/*
- * Event and mask registers (SMCE, SMCM)
- */
-#define M860_SMCE_BRKE  (1<<6)
-#define M860_SMCE_BRK   (1<<4)
-#define M860_SMCE_BSY   (1<<2)
-#define M860_SMCE_TX    (1<<1)
-#define M860_SMCE_RX    (1<<0)
-
-/*
-*************************************************************************
-*                      Serial Peripheral Interface                      *
-*************************************************************************
-*/
-typedef struct m860SPIparms_ {
-  rtems_unsigned16        rbase;
-  rtems_unsigned16        tbase;
-  rtems_unsigned8         rfcr;
-  rtems_unsigned8         tfcr;
-  rtems_unsigned16        mrblr;
-  rtems_unsigned32        _rstate;
-  rtems_unsigned32        _pad0;
-  rtems_unsigned16        _rbptr;
-  rtems_unsigned16        _pad1;
-  rtems_unsigned32        _pad2;
-  rtems_unsigned32        _tstate;
-  rtems_unsigned32        _pad3;
-  rtems_unsigned16        _tbptr;
-  rtems_unsigned16        _pad4;
-  rtems_unsigned32        _pad5;
-} m860SPIparms_t;
-
-/*
- * Mode register (SPMODE)
- */
-#define M860_SPMODE_LOOP                (1<<14) /* Local loopback mode */
-#define M860_SPMODE_CI                  (1<<13) /* Clock invert */
-#define M860_SPMODE_CP                  (1<<12) /* Clock phase */
-#define M860_SPMODE_DIV16               (1<<11) /* Divide BRGCLK by 16 */
-#define M860_SPMODE_REV                 (1<<10) /* Reverse data */
-#define M860_SPMODE_MASTER              (1<<9)  /* SPI is master */
-#define M860_SPMODE_EN                  (1<<8)  /* Enable SPI */
-#define M860_SPMODE_CLEN(x)             ((x)<<4)        /* Character length */
-#define M860_SPMODE_PM(x)               (x)     /* Prescaler modulus */
-
-/*
- * Mode register (SPCOM)
- */
-#define M860_SPCOM_STR                  (1<<7)  /* Start transmit */
-
-/*
- * Event and mask registers (SPIE, SPIM)
- */
-#define M860_SPIE_MME   (1<<5)          /* Multi-master error */
-#define M860_SPIE_TXE   (1<<4)          /* Tx error */
-#define M860_SPIE_BSY   (1<<2)          /* Busy condition*/
-#define M860_SPIE_TXB   (1<<1)          /* Tx buffer */
-#define M860_SPIE_RXB   (1<<0)          /* Rx buffer */
-
-/*
-*************************************************************************
-*                 SDMA (SCC, SMC, SPI) Buffer Descriptors               *
-*************************************************************************
-*/
-typedef struct m860BufferDescriptor_ {
-  rtems_unsigned16        status;
-  rtems_unsigned16        length;
-  volatile void           *buffer;
-} m860BufferDescriptor_t;
-
-/*
- * Bits in receive buffer descriptor status word
- */
-#define M860_BD_EMPTY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
-#define M860_BD_WRAP            (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
-#define M860_BD_INTERRUPT       (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
-#define M860_BD_LAST            (1<<11) /* Ethernet, SPI */
-#define M860_BD_CONTROL_CHAR    (1<<11) /* SCC UART */
-#define M860_BD_FIRST_IN_FRAME  (1<<10) /* Ethernet */
-#define M860_BD_ADDRESS         (1<<10) /* SCC UART */
-#define M860_BD_CONTINUOUS      (1<<9)  /* SCC UART, SMC UART, SPI */
-#define M860_BD_MISS            (1<<8)  /* Ethernet */
-#define M860_BD_IDLE            (1<<8)  /* SCC UART, SMC UART */
-#define M860_BD_ADDRSS_MATCH    (1<<7)  /* SCC UART */
-#define M860_BD_LONG            (1<<5)  /* Ethernet */
-#define M860_BD_BREAK           (1<<5)  /* SCC UART, SMC UART */
-#define M860_BD_NONALIGNED      (1<<4)  /* Ethernet */
-#define M860_BD_FRAMING_ERROR   (1<<4)  /* SCC UART, SMC UART */
-#define M860_BD_SHORT           (1<<3)  /* Ethernet */
-#define M860_BD_PARITY_ERROR    (1<<3)  /* SCC UART, SMC UART */
-#define M860_BD_CRC_ERROR       (1<<2)  /* Ethernet */
-#define M860_BD_OVERRUN         (1<<1)  /* Ethernet, SCC UART, SMC UART, SPI */
-#define M860_BD_COLLISION       (1<<0)  /* Ethernet */
-#define M860_BD_CARRIER_LOST    (1<<0)  /* SCC UART, SMC UART */
-#define M860_BD_MASTER_ERROR    (1<<0)  /* SPI */
-
-/*
- * Bits in transmit buffer descriptor status word
- * Many bits have the same meaning as those in receiver buffer descriptors.
- */
-#define M860_BD_READY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
-#define M860_BD_PAD             (1<<14) /* Ethernet */
-#define M860_BD_CTS_REPORT      (1<<11) /* SCC UART */
-#define M860_BD_TX_CRC          (1<<10) /* Ethernet */
-#define M860_BD_DEFER           (1<<9)  /* Ethernet */
-#define M860_BD_HEARTBEAT       (1<<8)  /* Ethernet */
-#define M860_BD_PREAMBLE        (1<<8)  /* SCC UART, SMC UART */
-#define M860_BD_LATE_COLLISION  (1<<7)  /* Ethernet */
-#define M860_BD_NO_STOP_BIT     (1<<7)  /* SCC UART */
-#define M860_BD_RETRY_LIMIT     (1<<6)  /* Ethernet */
-#define M860_BD_RETRY_COUNT(x)  (((x)&0x3C)>>2) /* Ethernet */
-#define M860_BD_UNDERRUN        (1<<1)  /* Ethernet, SPI */
-#define M860_BD_CARRIER_LOST    (1<<0)  /* Ethernet */
-#define M860_BD_CTS_LOST        (1<<0)  /* SCC UART */
-
-/*
-*************************************************************************
-*                           IDMA Buffer Descriptors                     *
-*************************************************************************
-*/
-typedef struct m860IDMABufferDescriptor_ {
-  rtems_unsigned16        status;
-  rtems_unsigned8         dfcr;       
-  rtems_unsigned8         sfcr;       
-  rtems_unsigned32        length;
-  void                    *source;
-  void                    *destination;
-} m860IDMABufferDescriptor_t;
-
-/*
-*************************************************************************
-*       RISC Communication Processor Module Command Register (CR)       *
-*************************************************************************
-*/
-#define M860_CR_RST             (1<<15) /* Reset communication processor */
-#define M860_CR_OP_INIT_RX_TX   (0<<8)  /* SCC, SMC UART, SMC GCI, SPI */
-#define M860_CR_OP_INIT_RX      (1<<8)  /* SCC, SMC UART, SPI */
-#define M860_CR_OP_INIT_TX      (2<<8)  /* SCC, SMC UART, SPI */
-#define M860_CR_OP_INIT_HUNT    (3<<8)  /* SCC, SMC UART */
-#define M860_CR_OP_STOP_TX      (4<<8)  /* SCC, SMC UART */
-#define M860_CR_OP_GR_STOP_TX   (5<<8)  /* SCC */
-#define M860_CR_OP_INIT_IDMA    (5<<8)  /* IDMA */
-#define M860_CR_OP_RESTART_TX   (6<<8)  /* SCC, SMC UART */
-#define M860_CR_OP_CLOSE_RX_BD  (7<<8)  /* SCC, SMC UART, SPI */
-#define M860_CR_OP_SET_GRP_ADDR (8<<8)  /* SCC */
-#define M860_CR_OP_SET_TIMER    (8<<8)  /* Timer */
-#define M860_CR_OP_GCI_TIMEOUT  (9<<8)  /* SMC GCI */
-#define M860_CR_OP_RESERT_BCS   (10<<8) /* SCC */
-#define M860_CR_OP_GCI_ABORT    (10<<8) /* SMC GCI */
-#define M860_CR_OP_STOP_IDMA    (11<<8) /* IDMA */
-#define M860_CR_OP_START_DSP    (12<<8) /* DSP */
-#define M860_CR_OP_INIT_DSP     (13<<8) /* DSP */
-
-#define M860_CR_CHAN_SCC1       (0<<4)  /* Channel selection */
-#define M860_CR_CHAN_I2C        (1<<4)
-#define M860_CR_CHAN_IDMA1      (1<<4)
-#define M860_CR_CHAN_SCC2       (4<<4)
-#define M860_CR_CHAN_SPI        (5<<4)
-#define M860_CR_CHAN_IDMA2      (5<<4)
-#define M860_CR_CHAN_TIMER      (5<<4)
-#define M860_CR_CHAN_SCC3       (8<<4)
-#define M860_CR_CHAN_SMC1       (9<<4)
-#define M860_CR_CHAN_DSP1       (9<<4)
-#define M860_CR_CHAN_SCC4       (12<<4)
-#define M860_CR_CHAN_SMC2       (13<<4)
-#define M860_CR_CHAN_DSP2       (13<<4)
-#define M860_CR_FLG             (1<<0)  /* Command flag */
-
-/*
-*************************************************************************
-*                 System Protection Control Register (SYPCR)            *
-*************************************************************************
-*/
-#define M860_SYPCR_SWTC(x)      ((x)<<16)   /* Software watchdog timer count */
-#define M860_SYPCR_BMT(x)       ((x)<<8)    /* Bus monitor timing */
-#define M860_SYPCR_BME          (1<<7)      /* Bus monitor enable */
-#define M860_SYPCR_SWF          (1<<3)      /* Software watchdog freeze */
-#define M860_SYPCR_SWE          (1<<2)      /* Software watchdog enable */
-#define M860_SYPCR_SWRI         (1<<1)      /* Watchdog reset/interrupt sel. */
-#define M860_SYPCR_SWP          (1<<0)      /* Software watchdog prescale */
-
-/*
-*************************************************************************
-*                        Memory Control Registers                       *
-*************************************************************************
-*/
-#define M860_UPM_AMX_8col       (0<<20) /* 8 column DRAM */
-#define M860_UPM_AMX_9col       (1<<20) /* 9 column DRAM */
-#define M860_UPM_AMX_10col      (2<<20) /* 10 column DRAM */
-#define M860_UPM_AMX_11col      (3<<20) /* 11 column DRAM */
-#define M860_UPM_AMX_12col      (4<<20) /* 12 column DRAM */
-#define M860_UPM_AMX_13col      (5<<20) /* 13 column DRAM */
-#define M860_MSR_PER(x)         (0x100<<(7-x)) /* Perity error bank (x) */
-#define M860_MSR_WPER           (1<<7)  /* Write protection error */
-#define M860_MPTPR_PTP(x)       ((x)<<8) /* Periodic timer prescaler */
-#define M860_BR_BA(x)           ((x)&0xffff8000) /* Base address */
-#define M860_BR_AT(x)           ((x)<<12) /* Address type */
-#define M860_BR_PS8             (1<<10)  /* 8 bit port */
-#define M860_BR_PS16            (2<<10)  /* 16 bit port */
-#define M860_BR_PS32            (0<<10)  /* 32 bit port */
-#define M860_BR_PARE            (1<<9)   /* Parity checking enable */
-#define M860_BR_WP              (1<<8)   /* Write protect */
-#define M860_BR_MS_GPCM         (0<<6)   /* GPCM */
-#define M860_BR_MS_UPMA         (2<<6)   /* UPM A */
-#define M860_BR_MS_UPMB         (3<<6)   /* UPM B */
-#define M860_MEMC_BR_V          (1<<0)  /* Base/Option register are valid */
-
-#define M860_MEMC_OR_32K        0xffff8000      /* Address range */
-#define M860_MEMC_OR_64K        0xffff0000
-#define M860_MEMC_OR_128K       0xfffe0000
-#define M860_MEMC_OR_256K       0xfffc0000
-#define M860_MEMC_OR_512K       0xfff80000
-#define M860_MEMC_OR_1M         0xfff00000
-#define M860_MEMC_OR_2M         0xffe00000
-#define M860_MEMC_OR_4M         0xffc00000
-#define M860_MEMC_OR_8M         0xff800000
-#define M860_MEMC_OR_16M        0xff000000
-#define M860_MEMC_OR_32M        0xfe000000
-#define M860_MEMC_OR_64M        0xfc000000
-#define M860_MEMC_OR_128        0xf8000000
-#define M860_MEMC_OR_256M       0xf0000000
-#define M860_MEMC_OR_512M       0xe0000000
-#define M860_MEMC_OR_1G         0xc0000000
-#define M860_MEMC_OR_2G         0x80000000
-#define M860_MEMC_OR_4G         0x00000000
-#define M860_MEMC_OR_ATM(x)     ((x)<<12)   /* Address type mask */
-#define M860_MEMC_OR_CSNT       (1<<11)     /* Chip select is negated early */
-#define M860_MEMC_OR_SAM        (1<<11)     /* Address lines are multiplexed */
-#define M860_MEMC_OR_ACS_NORM   (0<<9)      /* *CS asserted with addr lines */
-#define M860_MEMC_OR_ACS_QRTR   (2<<9)      /* *CS asserted 1/4 after addr */
-#define M860_MEMC_OR_ACS_HALF   (3<<9)      /* *CS asserted 1/2 after addr */
-#define M860_MEMC_OR_BI         (1<8)       /* Burst inhibit */
-#define M860_MEMC_OR_SCY(x)     ((x)<<4)    /* Cycle length in clocks */
-#define M860_MEMC_OR_SETA       (1<<3)      /* *TA generated externally */
-#define M860_MEMC_OR_TRLX       (1<<2)      /* Relaxed timing in GPCM */
-#define M860_MEMC_OR_EHTR       (1<<1)      /* Extended hold time on reads */
-
-/*
-*************************************************************************
-*                         UPM Registers (MxMR)                          *
-*************************************************************************
-*/
-#define M860_MEMC_MMR_PTP(x)   ((x)<<24)    /* Periodic timer period */
-#define M860_MEMC_MMR_PTE      (1<<23)      /* Periodic timer enable */
-#define M860_MEMC_MMR_DSP(x)   ((x)<<17)    /* Disable timer period */
-#define M860_MEMC_MMR_G0CL(x)  ((x)<<13)    /* General line 0 control */
-#define M860_MEMC_MMR_UPWAIT   (1<<12)      /* GPL_x4 is UPWAITx */
-#define M860_MEMC_MMR_RLF(x)   ((x)<<8)     /* Read loop field */
-#define M860_MEMC_MMR_WLF(x)   ((x)<<4)     /* Write loop field */
-#define M860_MEMC_MMR_TLF(x)   ((x)<<0)     /* Timer loop field */
-/*
-*************************************************************************
-*                         Memory Command Register (MCR)                 *
-*************************************************************************
-*/
-#define M860_MEMC_MCR_WRITE     (0<<30)     /* WRITE command */
-#define M860_MEMC_MCR_READ      (1<<30)     /* READ command */
-#define M860_MEMC_MCR_RUN       (2<<30)     /* RUN command */
-#define M860_MEMC_MCR_UPMA      (0<<23)     /* Cmd is for UPMA */
-#define M860_MEMC_MCR_UPMB      (1<<23)     /* Cmd is for UPMB */
-#define M860_MEMC_MCR_MB(x)     ((x)<<13)   /* Memory bank when RUN cmd */
-#define M860_MEMC_MCR_MCLF(x)   ((x)<<8)    /* Memory command loop field */
-#define M860_MEMC_MCR_MAD(x)    (x)         /* Machine address */
-
-
-
-/*
-*************************************************************************
-*                         SI Mode Register (SIMODE)                     *
-*************************************************************************
-*/
-#define M860_SI_SMC2_BITS       0xFFFF0000      /* All SMC2 bits */
-#define M860_SI_SMC2_TDM        (1<<31) /* Multiplexed SMC2 */
-#define M860_SI_SMC2_BRG1       (0<<28) /* SMC2 clock souce */
-#define M860_SI_SMC2_BRG2       (1<<28)
-#define M860_SI_SMC2_BRG3       (2<<28)
-#define M860_SI_SMC2_BRG4       (3<<28)
-#define M860_SI_SMC2_CLK5       (0<<28)
-#define M860_SI_SMC2_CLK6       (1<<28)
-#define M860_SI_SMC2_CLK7       (2<<28)
-#define M860_SI_SMC2_CLK8       (3<<28)
-#define M860_SI_SMC1_BITS       0x0000FFFF      /* All SMC1 bits */
-#define M860_SI_SMC1_TDM        (1<<15) /* Multiplexed SMC1 */
-#define M860_SI_SMC1_BRG1       (0<<12) /* SMC1 clock souce */
-#define M860_SI_SMC1_BRG2       (1<<12)
-#define M860_SI_SMC1_BRG3       (2<<12)
-#define M860_SI_SMC1_BRG4       (3<<12)
-#define M860_SI_SMC1_CLK1       (0<<12)
-#define M860_SI_SMC1_CLK2       (1<<12)
-#define M860_SI_SMC1_CLK3       (2<<12)
-#define M860_SI_SMC1_CLK4       (3<<12)
-
-/*
-*************************************************************************
-*                  SDMA Configuration Register (SDCR)                   *
-*************************************************************************
-*/
-#define M860_SDCR_FREEZE        (2<<13) /* Freeze on next bus cycle */
-#define M860_SDCR_RAID_5        (1<<0)  /* Normal arbitration ID */
-
-/*
-*************************************************************************
-*                  SDMA Status Register (SDSR)                          *
-*************************************************************************
-*/
-#define M860_SDSR_SBER          (1<<7)  /* SDMA Channel bus error */
-#define M860_SDSR_DSP2          (1<<1)  /* DSP Chain 2 interrupt */
-#define M860_SDSR_DSP1          (1<<0)  /* DSP Chain 1 interrupt */
-
-/*
-*************************************************************************
-*                      Baud (sic) Rate Generators                       *
-*************************************************************************
-*/
-#define M860_BRG_RST            (1<<17)         /* Reset generator */
-#define M860_BRG_EN             (1<<16)         /* Enable generator */
-#define M860_BRG_EXTC_BRGCLK    (0<<14)         /* Source is BRGCLK */
-#define M860_BRG_EXTC_CLK2      (1<<14)         /* Source is CLK2 pin */
-#define M860_BRG_EXTC_CLK6      (2<<14)         /* Source is CLK6 pin */
-#define M860_BRG_ATB            (1<<13)         /* Autobaud */
-#define M860_BRG_115200         (21<<1)         /* Assume 40 MHz clock */
-#define M860_BRG_57600          (32<<1)
-#define M860_BRG_38400          (64<<1)
-#define M860_BRG_19200          (129<<1)
-#define M860_BRG_9600           (259<<1)
-#define M860_BRG_4800           (520<<1)
-#define M860_BRG_2400           (1040<<1)
-#define M860_BRG_1200           (2082<<1)
-#define M860_BRG_600            ((259<<1) | 1)
-#define M860_BRG_300            ((520<<1) | 1)
-#define M860_BRG_150            ((1040<<1) | 1)
-#define M860_BRG_75             ((2080<<1) | 1)
-
-#define M860_TGCR_CAS4          (1<<15)   /* Cascade timers 3 and 4 */
-#define M860_TGCR_CAS2          (1<<7)    /* Cascade timers 1 and 2 */
-#define M860_TGCR_FRZ1          (1<<2)    /* Halt timer if FREEZE asserted */
-#define M860_TGCR_FRZ2          (1<<6)    /* Halt timer if FREEZE asserted */
-#define M860_TGCR_FRZ3          (1<<10)   /* Halt timer if FREEZE asserted */
-#define M860_TGCR_FRZ4          (1<<14)   /* Halt timer if FREEZE asserted */
-#define M860_TGCR_STP1          (1<<1)    /* Stop timer */
-#define M860_TGCR_STP2          (1<<5)    /* Stop timer */
-#define M860_TGCR_STP3          (1<<9)    /* Stop timer */
-#define M860_TGCR_STP4          (1<<13)   /* Stop timer */
-#define M860_TGCR_RST1          (1<<0)    /* Enable timer */
-#define M860_TGCR_RST2          (1<<4)    /* Enable timer */
-#define M860_TGCR_RST3          (1<<8)    /* Enable timer */
-#define M860_TGCR_RST4          (1<<12)   /* Enable timer */
-#define M860_TGCR_GM1           (1<<3)    /* Gate Mode 1 for TMR1 or TMR2 */
-#define M860_TGCR_GM2           (1<<11)   /* Gate Mode 2 for TMR3 or TMR4 */
-
-#define M860_TMR_PS(x)          ((x)<<8)  /* Timer prescaler */
-#define M860_TMR_CE_RISE        (1<<6)    /* Capture on rising edge */
-#define M860_TMR_CE_FALL        (2<<6)    /* Capture on falling edge */
-#define M860_TMR_CE_ANY         (3<<6)    /* Capture on any edge */
-#define M860_TMR_OM_TOGGLE      (1<<5)    /* Toggle TOUTx pin */
-#define M860_TMR_ORI            (1<<4)    /* Interrupt on reaching reference */
-#define M860_TMR_RESTART        (1<<3)    /* Restart timer after reference */
-#define M860_TMR_ICLK_INT       (1<<1)    /* Internal clock is timer source */
-#define M860_TMR_ICLK_INT16     (2<<1)    /* Internal clock/16 is tmr src */
-#define M860_TMR_ICLK_TIN       (3<<1)    /* TIN pin is timer source */
-#define M860_TMR_TGATE          (1<<0)    /* TGATE controls timer */
-
-#define M860_PISCR_PIRQ(x)      (1<<(15-x))  /* PIT interrupt level */
-#define M860_PISCR_PS           (1<<7)    /* PIT Interrupt state */
-#define M860_PISCR_PIE          (1<<2)    /* PIT interrupt enable */
-#define M860_PISCR_PITF         (1<<1)    /* Stop timer when freeze asserted */
-#define M860_PISCR_PTE          (1<<0)    /* PIT enable */
-
-#define M860_TBSCR_TBIRQ(x)     (1<<(15-x))  /* TB interrupt level */
-#define M860_TBSCR_REFA         (1<<7)    /* TB matches TBREFF0 */
-#define M860_TBSCR_REFB         (1<<6)    /* TB matches TBREFF1 */
-#define M860_TBSCR_REFAE        (1<<3)    /* Enable ints for REFA */
-#define M860_TBSCR_REFBE        (1<<2)    /* Enable ints for REFB */
-#define M860_TBSCR_TBF          (1<<1)    /* TB stops on FREEZE */
-#define M860_TBSCR_TBE          (1<<0)    /* enable TB and decrementer */
-
-#define M860_SIMASK_IRM0        (1<<31)
-#define M860_SIMASK_LVM0        (1<<30)
-#define M860_SIMASK_IRM1        (1<<29)
-#define M860_SIMASK_LVM1        (1<<28)
-#define M860_SIMASK_IRM2        (1<<27)
-#define M860_SIMASK_LVM2        (1<<26)
-#define M860_SIMASK_IRM3        (1<<25)
-#define M860_SIMASK_LVM3        (1<<24)
-#define M860_SIMASK_IRM4        (1<<23)
-#define M860_SIMASK_LVM4        (1<<22)
-#define M860_SIMASK_IRM5        (1<<21)
-#define M860_SIMASK_LVM5        (1<<20)
-#define M860_SIMASK_IRM6        (1<<19)
-#define M860_SIMASK_LVM6        (1<<18)
-#define M860_SIMASK_IRM7        (1<<17)
-#define M860_SIMASK_LVM7        (1<<16)
-
-#define M860_SIUMCR_EARB        (1<<31)
-#define M860_SIUMCR_EARP0       (0<<28)
-#define M860_SIUMCR_EARP1       (1<<28)
-#define M860_SIUMCR_EARP2       (2<<28)
-#define M860_SIUMCR_EARP3       (3<<28)
-#define M860_SIUMCR_EARP4       (4<<28)
-#define M860_SIUMCR_EARP5       (5<<28)
-#define M860_SIUMCR_EARP6       (6<<28)
-#define M860_SIUMCR_EARP7       (7<<28)
-#define M860_SIUMCR_DSHW        (1<<23)
-#define M860_SIUMCR_DBGC0       (0<<21)
-#define M860_SIUMCR_DBGC1       (1<<21)
-#define M860_SIUMCR_DBGC2       (2<<21)
-#define M860_SIUMCR_DBGC3       (3<<21)
-#define M860_SIUMCR_DBPC0       (0<<19)
-#define M860_SIUMCR_DBPC1       (1<<19)
-#define M860_SIUMCR_DBPC2       (2<<19)
-#define M860_SIUMCR_DBPC3       (3<<19)
-#define M860_SIUMCR_FRC         (1<<17)
-#define M860_SIUMCR_DLK         (1<<16)
-#define M860_SIUMCR_PNCS        (1<<15)
-#define M860_SIUMCR_OPAR        (1<<14)
-#define M860_SIUMCR_DPC         (1<<13)
-#define M860_SIUMCR_MPRE        (1<<12)
-#define M860_SIUMCR_MLRC0       (0<<10)
-#define M860_SIUMCR_MLRC1       (1<<10)
-#define M860_SIUMCR_MLRC2       (2<<10)
-#define M860_SIUMCR_MLRC3       (3<<10)
-#define M860_SIUMCR_AEME        (1<<9)
-#define M860_SIUMCR_SEME        (1<<8)
-#define M860_SIUMCR_BSC         (1<<7)
-#define M860_SIUMCR_GB5E        (1<<6)
-#define M860_SIUMCR_B2DD        (1<<5)
-#define M860_SIUMCR_B3DD        (1<<4)
-/*
-*************************************************************************
-*                 MPC860 DUAL-PORT RAM AND REGISTERS                    *
-*************************************************************************
-*/
-typedef struct m860_ {
-        
-  /*
-   * SIU Block
-   */
-  rtems_unsigned32      siumcr;
-  rtems_unsigned32      sypcr;
-  rtems_unsigned32      swt;
-  rtems_unsigned16      _pad0;
-  rtems_unsigned16      swsr;
-  rtems_unsigned32      sipend;
-  rtems_unsigned32      simask;
-  rtems_unsigned32      siel;
-  rtems_unsigned32      sivec;
-  rtems_unsigned32      tesr;
-  rtems_unsigned32      _pad1[3];
-  rtems_unsigned32      sdcr;
-  rtems_unsigned8       _pad2[0x80-0x34];
-  
-  /*
-   * PCMCIA Block
-   */
-  rtems_unsigned32      pbr0;
-  rtems_unsigned32      por0;
-  rtems_unsigned32      pbr1;
-  rtems_unsigned32      por1;
-  rtems_unsigned32      pbr2;
-  rtems_unsigned32      por2;
-  rtems_unsigned32      pbr3;
-  rtems_unsigned32      por3;
-  rtems_unsigned32      pbr4;
-  rtems_unsigned32      por4;
-  rtems_unsigned32      pbr5;
-  rtems_unsigned32      por5;
-  rtems_unsigned32      pbr6;
-  rtems_unsigned32      por6;
-  rtems_unsigned32      pbr7;
-  rtems_unsigned32      por7;
-  rtems_unsigned8       _pad3[0xe0-0xc0];
-  rtems_unsigned32      pgcra;
-  rtems_unsigned32      pgcrb;
-  rtems_unsigned32      pscr;
-  rtems_unsigned32      _pad4;
-  rtems_unsigned32      pipr;
-  rtems_unsigned32      _pad5;
-  rtems_unsigned32      per;
-  rtems_unsigned32      _pad6;
-  
-  /*
-   * MEMC Block
-   */
-  m860MEMCRegisters_t   memc[8];
-  rtems_unsigned8       _pad7[0x164-0x140];
-  rtems_unsigned32      mar;
-  rtems_unsigned32      mcr;
-  rtems_unsigned32      _pad8;
-  rtems_unsigned32      mamr;
-  rtems_unsigned32      mbmr;
-  rtems_unsigned16      mstat;
-  rtems_unsigned16      mptpr;
-  rtems_unsigned32      mdr;
-  rtems_unsigned8       _pad9[0x200-0x180];
-  
-  /*
-   * System integration timers
-   */
-  rtems_unsigned16      tbscr;
-  rtems_unsigned16      _pad10;
-  rtems_unsigned32      tbreff0;
-  rtems_unsigned32      tbreff1;
-  rtems_unsigned8       _pad11[0x220-0x20c];
-  rtems_unsigned16      rtcsc;
-  rtems_unsigned16      _pad12;
-  rtems_unsigned32      rtc;
-  rtems_unsigned32      rtsec;
-  rtems_unsigned32      rtcal;
-  rtems_unsigned32      _pad13[4];
-  rtems_unsigned16      piscr;
-  rtems_unsigned16      _pad14;
-  rtems_unsigned16      pitc;
-  rtems_unsigned16      _pad_14_1;
-  rtems_unsigned16      pitr;
-  rtems_unsigned16      _pad_14_2;
-  rtems_unsigned8       _pad15[0x280-0x24c];
-  
-  
-  /*
-   * Clocks and Reset
-   */
-  rtems_unsigned32      sccr;
-  rtems_unsigned32      plprcr;
-  rtems_unsigned32      rsr;
-  rtems_unsigned8       _pad16[0x300-0x28c];
-  
-  
-  /*
-   * System integration timers keys
-   */
-  rtems_unsigned32      tbscrk;
-  rtems_unsigned32      tbreff0k;
-  rtems_unsigned32      tbreff1k;
-  rtems_unsigned32      tbk;
-  rtems_unsigned32      _pad17[4];
-  rtems_unsigned32      rtcsk;
-  rtems_unsigned32      rtck;
-  rtems_unsigned32      rtseck;
-  rtems_unsigned32      rtcalk;
-  rtems_unsigned32      _pad18[4];
-  rtems_unsigned32      piscrk;
-  rtems_unsigned32      pitck;
-  rtems_unsigned8       _pad19[0x380-0x348];
-  
-  /*
-   * Clocks and Reset Keys
-   */
-  rtems_unsigned32      sccrk;
-  rtems_unsigned32      plprck;
-  rtems_unsigned32      rsrk;
-  rtems_unsigned8       _pad20[0x400-0x38c];
-  rtems_unsigned8       _pad21[0x800-0x400];
-  rtems_unsigned8       _pad22[0x860-0x800];
-  
-  
-  /*
-   * I2C
-   */
-  rtems_unsigned8       i2mod;
-  rtems_unsigned8       _pad23[3];
-  rtems_unsigned8       i2add;
-  rtems_unsigned8       _pad24[3];
-  rtems_unsigned8       i2brg;
-  rtems_unsigned8       _pad25[3];
-  rtems_unsigned8       i2com;
-  rtems_unsigned8       _pad26[3];
-  rtems_unsigned8       i2cer;
-  rtems_unsigned8       _pad27[3];
-  rtems_unsigned8       i2cmr;
-  rtems_unsigned8       _pad28[0x900-0x875];
-  
-  /*
-   * DMA Block
-   */
-  rtems_unsigned32      _pad29;
-  rtems_unsigned32      sdar;
-  rtems_unsigned8       sdsr;
-  rtems_unsigned8       _pad30[3];
-  rtems_unsigned8       sdmr;
-  rtems_unsigned8       _pad31[3];
-  rtems_unsigned8       idsr1;
-  rtems_unsigned8       _pad32[3];
-  rtems_unsigned8       idmr1;
-  rtems_unsigned8       _pad33[3];
-  rtems_unsigned8       idsr2;
-  rtems_unsigned8       _pad34[3];
-  rtems_unsigned8       idmr2;
-  rtems_unsigned8       _pad35[0x930-0x91d];
-  
-  
-  
-  /*
-   * CPM Interrupt Control Block
-   */
-  rtems_unsigned16      civr;
-  rtems_unsigned8       _pad36[14];
-  rtems_unsigned32      cicr;
-  rtems_unsigned32      cipr;
-  rtems_unsigned32      cimr;
-  rtems_unsigned32      cisr;
-  
-  /*
-   * I/O Port Block
-   */
-  rtems_unsigned16      padir;
-  rtems_unsigned16      papar;
-  rtems_unsigned16      paodr;
-  rtems_unsigned16      padat;
-  rtems_unsigned8       _pad37[8];
-  rtems_unsigned16      pcdir;
-  rtems_unsigned16      pcpar;
-  rtems_unsigned16      pcso;
-  rtems_unsigned16      pcdat;
-  rtems_unsigned16      pcint;
-  rtems_unsigned8       _pad39[6];
-  rtems_unsigned16      pddir;
-  rtems_unsigned16      pdpar;
-  rtems_unsigned16      _pad40;
-  rtems_unsigned16      pddat;
-  rtems_unsigned8       _pad41[8];
-  
-  /*
-   * CPM Timers Block
-   */
-  rtems_unsigned16      tgcr;
-  rtems_unsigned8       _pad42[14];
-  rtems_unsigned16      tmr1;
-  rtems_unsigned16      tmr2;
-  rtems_unsigned16      trr1;
-  rtems_unsigned16      trr2;
-  rtems_unsigned16      tcr1;
-  rtems_unsigned16      tcr2;
-  rtems_unsigned16      tcn1;
-  rtems_unsigned16      tcn2;
-  rtems_unsigned16      tmr3;
-  rtems_unsigned16      tmr4;
-  rtems_unsigned16      trr3;
-  rtems_unsigned16      trr4;
-  rtems_unsigned16      tcr3;
-  rtems_unsigned16      tcr4;
-  rtems_unsigned16      tcn3;
-  rtems_unsigned16      tcn4;
-  rtems_unsigned16      ter1;
-  rtems_unsigned16      ter2;
-  rtems_unsigned16      ter3;
-  rtems_unsigned16      ter4;
-  rtems_unsigned8       _pad43[8];
-  
-  
-  
-  /*
-   * CPM Block
-   */
-  rtems_unsigned16      cpcr;
-  rtems_unsigned16      _pad44;
-  rtems_unsigned16      rccr;
-  rtems_unsigned8       _pad45;
-  rtems_unsigned8       rmds;
-  rtems_unsigned32      rmdr;
-  rtems_unsigned16      rctr1;
-  rtems_unsigned16      rctr2;
-  rtems_unsigned16      rctr3;
-  rtems_unsigned16      rctr4;
-  rtems_unsigned16      _pad46;
-  rtems_unsigned16      rter;
-  rtems_unsigned16      _pad47;
-  rtems_unsigned16      rtmr;
-  rtems_unsigned8       _pad48[0x9f0-0x9dc];
-  
-  /*
-   * BRG Block
-   */
-  rtems_unsigned32      brgc1;
-  rtems_unsigned32      brgc2;
-  rtems_unsigned32      brgc3;
-  rtems_unsigned32      brgc4;
-  
-  /*
-   * SCC Block
-   */
-  m860SCCRegisters_t    scc1;
-  m860SCCRegisters_t    scc2;
-  m860SCCRegisters_t    scc3;
-  m860SCCRegisters_t    scc4;
-  
-  /*
-   * SMC Block
-   */
-  m860SMCRegisters_t    smc1;
-  m860SMCRegisters_t    smc2;
-  
-  /*
-   * SPI Block
-   */
-  rtems_unsigned16      spmode;
-  rtems_unsigned16      _pad49[2];
-  rtems_unsigned8       spie;
-  rtems_unsigned8       _pad50;
-  rtems_unsigned16      _pad51;
-  rtems_unsigned8       spim;
-  rtems_unsigned8       _pad52[2];
-  rtems_unsigned8       spcom;
-  rtems_unsigned16      _pad53[2];
-  
-  /*
-   * PIP Block
-   */
-  rtems_unsigned16      pipc;
-  rtems_unsigned16      _pad54;
-  rtems_unsigned16      ptpr;
-  rtems_unsigned32      pbdir;
-  rtems_unsigned32      pbpar;
-  rtems_unsigned16      _pad55;
-  rtems_unsigned16      pbodr;
-  rtems_unsigned32      pbdat;
-  rtems_unsigned32      _pad56[6];
-  
-  /*
-   * SI Block
-   */
-  rtems_unsigned32      simode;
-  rtems_unsigned8       sigmr;
-  rtems_unsigned8       _pad57;
-  rtems_unsigned8       sistr;
-  rtems_unsigned8       sicmr;
-  rtems_unsigned32      _pad58;
-  rtems_unsigned32      sicr;
-  rtems_unsigned16      sirp[2];
-  rtems_unsigned32      _pad59[3];
-  rtems_unsigned8       _pad60[0xc00-0xb00];
-  rtems_unsigned8       siram[512];
-
-  /*
-   * This is only used on the MPC860T - for the Fast Ethernet Controller (FEC)
-   */
-  m860FECRegisters_t         fec;
-
-  rtems_unsigned8       _pad62[0x2000-0x1000];
-  /*
-   * Dual-port RAM
-   */
-  rtems_unsigned8       dpram0[0x200];  /* BD/DATA/UCODE */
-  rtems_unsigned8       dpram1[0x200];  /* BD/DATA/UCODE */
-  rtems_unsigned8       dpram2[0x400];  /* BD/DATA/UCODE */
-  rtems_unsigned8       dpram3[0x600];  /* BD/DATA*/
-  rtems_unsigned8       dpram4[0x200];  /* BD/DATA/UCODE */
-  rtems_unsigned8       _pad63[0x3c00-0x3000];
-  
-  /* When using SCC1 for ethernet, we lose the use of I2C since
-   *  their parameters would overlap. Motorola has a microcode
-   *  patch to move parameters around so that both can be used
-   *  together. It is available on their web site somewhere 
-   *  under http://www.mot.com/mpc860. If ethernet is used on
-   *  one (or more) of the other SCCs, then other CPM features
-   *  will be unavailable:
-   *    SCC2    -> lose SPI
-   *    SCC3    -> lose SMC1
-   *    SCC4    -> lose SMC2
-   */
-  m860SCCENparms_t      scc1p;
-  rtems_unsigned8       _rsv1[0xCB0-0xC00-sizeof(m860SCCENparms_t)];
-  m860MiscParms_t       miscp;
-  rtems_unsigned8       _rsv2[0xcc0-0xCB0-sizeof(m860MiscParms_t)];
-  m860IDMAparms_t       idma1p;
-  rtems_unsigned8       _rsv3[0xd00-0xcc0-sizeof(m860IDMAparms_t)];
-  
-  m860SCCparms_t        scc2p;
-  rtems_unsigned8       _rsv4[0xD80-0xD00-sizeof(m860SCCparms_t)];
-  m860SPIparms_t        spip;
-  rtems_unsigned8       _rsv5[0xDB0-0xD80-sizeof(m860SPIparms_t)];
-  m860TimerParms_t      tmp;
-  rtems_unsigned8       _rsv6[0xDC0-0xDB0-sizeof(m860TimerParms_t)];
-  m860IDMAparms_t       idma2p;
-  rtems_unsigned8       _rsv7[0xE00-0xDC0-sizeof(m860IDMAparms_t)];
-  
-  m860SCCparms_t        scc3p;
-  rtems_unsigned8       _rsv8[0xE80-0xE00-sizeof(m860SCCparms_t)];
-  m860SMCparms_t        smc1p;
-  rtems_unsigned8       _rsv9[0xEC0-0xE80-sizeof(m860SMCparms_t)];
-  m860DSPparms_t        dsp1p;
-  rtems_unsigned8       _rsv10[0xF00-0xEC0-sizeof(m860DSPparms_t)];
-  
-  m860SCCparms_t        scc4p;
-  rtems_unsigned8       _rsv11[0xF80-0xF00-sizeof(m860SCCparms_t)];
-  m860SMCparms_t        smc2p;
-  rtems_unsigned8       _rsv12[0xFC0-0xF80-sizeof(m860SMCparms_t)];
-  m860DSPparms_t        dsp2p;
-  rtems_unsigned8       _rsv13[0x1000-0xFC0-sizeof(m860DSPparms_t)];
-} m860_t;
-
-extern volatile m860_t m860;
-#endif /* ASM */
-
-#endif /* __MPC860_h */
diff --git a/c/src/exec/score/cpu/powerpc/other_cpu/Makefile.in b/c/src/exec/score/cpu/powerpc/other_cpu/Makefile.in
new file mode 100644
index 0000000000..dd38dc7bf2
--- /dev/null
+++ b/c/src/exec/score/cpu/powerpc/other_cpu/Makefile.in
@@ -0,0 +1,83 @@
+#
+# $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+top_srcdir = @top_srcdir@
+top_builddir = ../../../../../../..
+subdir = c/src/exec/score/cpu/powerpc/wrap
+
+INSTALL = @INSTALL@
+
+RTEMS_ROOT = $(top_srcdir)/@RTEMS_TOPdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+VPATH = @srcdir@
+
+RELS=../$(ARCH)/rtems-cpu.rel
+
+# C source names, if any, go here -- minus the .c
+C_PIECES = cpu ppccache
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+ROOT_H_PIECES =
+ROOT_H_FILES=$(ROOT_H_PIECES:%=$(srcdir)/%)
+RTEMS_SCORE_H_PIECES=cpu.h
+RTEMS_SCORE_H_FILES=$(RTEMS_SCORE_H_PIECES:%=$(srcdir)/%)
+H_PIECES=$(ROOT_H_PIECES) $(RTEMS_SCORE_H_PIECES)
+H_FILES=$(H_PIECES%=$(srcdir)/%)
+I_PIECES= c_isr
+I_FILES=$(I_PIECES:%=$(srcdir)/%.inl)
+
+# Assembly source names, if any, go here -- minus the .S
+S_PIECES = cpu_asm rtems # irq_stub
+S_FILES=$(S_PIECES:%=%.S)
+S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
+
+SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES) $(I_FILES)
+OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/${RTEMS_BSP}.cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS += 
+CFLAGS   += $(CFLAGS_OS_V)
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS += 
+CLOBBER_ADDITIONS +=
+
+../$(ARCH)/rtems-cpu.rel: $(OBJS)
+	test -d ../$(ARCH) || mkdir ../$(ARCH)
+	$(make-rel)
+
+all:    ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
+
+# Install the program(s), appending _g or _p as appropriate.
+# for include files, just use $(INSTALL_CHANGE)
+install:  all
+
+preinstall: ${ARCH}
+	$(INSTALL_CHANGE) -m 444 ${RTEMS_SCORE_H_FILES} ${I_FILES} $(PROJECT_INCLUDE)/rtems/score
+	$(INSTALL_CHANGE) -m 444 ${ROOT_H_FILES} $(PROJECT_INCLUDE)
+
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+	cd $(top_builddir) \
+	 && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status
diff --git a/c/src/exec/score/cpu/powerpc/README b/c/src/exec/score/cpu/powerpc/other_cpu/README
index 0b87ac1ea7..0b87ac1ea7 100644
--- a/c/src/exec/score/cpu/powerpc/README
+++ b/c/src/exec/score/cpu/powerpc/other_cpu/README
diff --git a/c/src/exec/score/cpu/powerpc/TODO b/c/src/exec/score/cpu/powerpc/other_cpu/TODO
index 64c96cb14c..64c96cb14c 100644
--- a/c/src/exec/score/cpu/powerpc/TODO
+++ b/c/src/exec/score/cpu/powerpc/other_cpu/TODO
diff --git a/c/src/exec/score/cpu/powerpc/other_cpu/c_isr.inl b/c/src/exec/score/cpu/powerpc/other_cpu/c_isr.inl
new file mode 100644
index 0000000000..706d4f7e4f
--- /dev/null
+++ b/c/src/exec/score/cpu/powerpc/other_cpu/c_isr.inl
@@ -0,0 +1,4 @@
+RTEMS_INLINE_ROUTINE boolean _ISR_Is_in_progress( void )
+{
+	return (_ISR_Nest_level != 0);
+}
diff --git a/c/src/exec/score/cpu/powerpc/cpu.c b/c/src/exec/score/cpu/powerpc/other_cpu/cpu.c
index 1e1a7379f0..1e1a7379f0 100644
--- a/c/src/exec/score/cpu/powerpc/cpu.c
+++ b/c/src/exec/score/cpu/powerpc/other_cpu/cpu.c
diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/cpu.h b/c/src/exec/score/cpu/powerpc/other_cpu/cpu.h
index 0bb28110d4..325f6bd7af 100644
--- a/c/src/exec/score/cpu/powerpc/rtems/score/cpu.h
+++ b/c/src/exec/score/cpu/powerpc/other_cpu/cpu.h
@@ -41,6 +41,7 @@ extern "C" {
 #include <rtems/score/ppc.h>               /* pick up machine definitions */
 #ifndef ASM
 struct CPU_Interrupt_frame;
+typedef void ( *ppc_isr_entry )( int, struct CPU_Interrupt_frame * );
 
 #include <rtems/score/ppctypes.h>
 #endif
diff --git a/c/src/exec/score/cpu/powerpc/cpu_asm.S b/c/src/exec/score/cpu/powerpc/other_cpu/cpu_asm.S
index a377fa5d2a..a377fa5d2a 100644
--- a/c/src/exec/score/cpu/powerpc/cpu_asm.S
+++ b/c/src/exec/score/cpu/powerpc/other_cpu/cpu_asm.S
diff --git a/c/src/exec/score/cpu/powerpc/irq_stub.S b/c/src/exec/score/cpu/powerpc/other_cpu/irq_stub.S
index 76c8927305..76c8927305 100644
--- a/c/src/exec/score/cpu/powerpc/irq_stub.S
+++ b/c/src/exec/score/cpu/powerpc/other_cpu/irq_stub.S
diff --git a/c/src/exec/score/cpu/powerpc/ppccache.c b/c/src/exec/score/cpu/powerpc/other_cpu/ppccache.c
index ecfb4b96ca..ecfb4b96ca 100644
--- a/c/src/exec/score/cpu/powerpc/ppccache.c
+++ b/c/src/exec/score/cpu/powerpc/other_cpu/ppccache.c
diff --git a/c/src/exec/score/cpu/powerpc/rtems.S b/c/src/exec/score/cpu/powerpc/other_cpu/rtems.S
index b653152411..b653152411 100644
--- a/c/src/exec/score/cpu/powerpc/rtems.S
+++ b/c/src/exec/score/cpu/powerpc/other_cpu/rtems.S
diff --git a/c/src/exec/score/cpu/powerpc/rtems/Makefile.in b/c/src/exec/score/cpu/powerpc/rtems/Makefile.in
deleted file mode 100644
index 3b0dff2d4d..0000000000
--- a/c/src/exec/score/cpu/powerpc/rtems/Makefile.in
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-#  $Id$
-#
-
-@SET_MAKE@
-srcdir = @srcdir@
-top_srcdir = @top_srcdir@
-top_builddir = ../../../../../../..
-subdir = c/src/exec/score/cpu/powerpc/rtems
-
-INSTALL = @INSTALL@
-
-RTEMS_ROOT = $(top_srcdir)/@RTEMS_TOPdir@
-PROJECT_ROOT = @PROJECT_ROOT@
-
-VPATH = @srcdir@
-
-include $(RTEMS_ROOT)/make/custom/${RTEMS_BSP}.cfg
-include $(RTEMS_ROOT)/make/directory.cfg
-
-SUB_DIRS = score
-
-Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
-	cd $(top_builddir) \
-	 && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status
diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h b/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h
new file mode 100644
index 0000000000..27f8a4cfc1
--- /dev/null
+++ b/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h
@@ -0,0 +1,615 @@
+/*  ppc.h
+ *
+ *  This file contains definitions for the IBM/Motorola PowerPC
+ *  family members.
+ *
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *
+ * Note:
+ *      This file is included by both C and assembler code ( -DASM )
+ *
+ *  $Id$
+ */
+
+
+#ifndef _INCLUDE_PPC_h
+#define _INCLUDE_PPC_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  Define the name of the CPU family.
+ */
+
+#define CPU_NAME "PowerPC"
+
+/*
+ *  This file contains the information required to build
+ *  RTEMS for a particular member of the PowerPC family.  It does
+ *  this by setting variables to indicate which implementation
+ *  dependent features are present in a particular member
+ *  of the family.
+ *
+ *  The following architectural feature definitions are defaulted
+ *  unless specifically set by the model definition:
+ *
+ *    + PPC_DEBUG_MODEL          - PPC_DEBUG_MODEL_STANDARD
+ *    + PPC_INTERRUPT_MAX        - 16
+ *    + PPC_CACHE_ALIGNMENT      - 32
+ *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
+ *    + PPC_HAS_EXCEPTION_PREFIX - 1
+ *    + PPC_HAS_FPU              - 1
+ *    + PPC_HAS_DOUBLE           - 1 if PPC_HAS_FPU, 
+ *                               - 0 otherwise
+ *    + PPC_USE_MULTIPLE         - 0
+ */
+ 
+/*
+ *  Define the debugging assistance models found in the PPC family.
+ *
+ *  Standard:         single step and branch trace
+ *  Single Step Only: single step only
+ *  IBM 4xx:          debug exception
+ */
+
+#define PPC_DEBUG_MODEL_STANDARD         1
+#define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2
+#define PPC_DEBUG_MODEL_IBM4xx           3
+
+/*
+ *  Define the low power mode models
+ *
+ *  Standard:   as defined for 603e
+ *  Nap Mode:   nap mode only (604)
+ *  XXX 403GB, 603, 603e, 604, 821
+ */
+
+#define PPC_LOW_POWER_MODE_NONE      0
+#define PPC_LOW_POWER_MODE_STANDARD  1
+
+#if defined(ppc403)
+/*
+ *  IBM 403
+ *
+ *  Developed for 403GA.  Book checked for 403GB.
+ *
+ *  Does not have user mode.
+ */
+ 
+#define CPU_MODEL_NAME "PowerPC 403"
+#define PPC_ALIGNMENT		4  
+#define PPC_CACHE_ALIGNMENT	16
+#define PPC_HAS_RFCI    	1
+#define PPC_HAS_FPU     	0
+#define PPC_USE_MULTIPLE	1
+#define PPC_I_CACHE		2048
+#define PPC_D_CACHE		1024
+
+#define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_IBM4xx
+#define PPC_HAS_EXCEPTION_PREFIX 0
+#define PPC_HAS_EVPR             1
+
+#elif defined(ppc601)
+/*
+ *  Submitted with original port -- book checked only.
+ */
+ 
+#define CPU_MODEL_NAME  "PowerPC 601"
+
+#define PPC_ALIGNMENT		8
+#define PPC_USE_MULTIPLE	1
+#define PPC_I_CACHE		0
+#define PPC_D_CACHE		32768
+
+#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY
+
+#elif defined(ppc602)
+/*
+ *  Submitted with original port -- book checked only.
+ */
+ 
+#define CPU_MODEL_NAME  "PowerPC 602"
+
+#define PPC_ALIGNMENT		4
+#define PPC_HAS_DOUBLE		0
+#define PPC_I_CACHE		4096
+#define PPC_D_CACHE		4096
+
+#elif defined(ppc603)
+/*
+ *  Submitted with original port -- book checked only.
+ */
+ 
+#define CPU_MODEL_NAME  "PowerPC 603"
+
+#define PPC_ALIGNMENT		8
+#define PPC_I_CACHE		8192
+#define PPC_D_CACHE		8192
+
+#elif defined(ppc603e)
+ 
+#define CPU_MODEL_NAME  "PowerPC 603e"
+/*
+ *  Submitted with original port.
+ *
+ *  Known to work on real hardware.
+ */
+
+#define PPC_ALIGNMENT		8
+#define PPC_I_CACHE		16384
+#define PPC_D_CACHE		16384
+
+#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
+
+#elif defined(ppc604)
+/*
+ *  Submitted with original port -- book checked only.
+ */
+ 
+#define CPU_MODEL_NAME  "PowerPC 604"
+
+#define PPC_ALIGNMENT		8
+#define PPC_I_CACHE		16384
+#define PPC_D_CACHE		16384
+ 
+#elif defined(mpc860)
+/* 
+ *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98 
+ */ 
+#define CPU_MODEL_NAME  "PowerPC MPC860"
+
+#define PPC_ALIGNMENT		4
+#define PPC_I_CACHE             4096
+#define PPC_D_CACHE             4096
+#define PPC_CACHE_ALIGNMENT	16
+#define PPC_INTERRUPT_MAX       71
+#define PPC_HAS_FPU     	0
+#define PPC_HAS_DOUBLE		0
+#define PPC_USE_MULTIPLE	1
+#define PPC_USE_SPRG            1
+
+#define PPC_MSR_0		0x00009000
+#define PPC_MSR_1		0x00001000
+#define PPC_MSR_2		0x00001000
+#define PPC_MSR_3		0x00000000
+
+#elif defined(mpc821)
+/* 
+ *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
+ */ 
+#define CPU_MODEL_NAME  "PowerPC MPC821"
+
+#define PPC_ALIGNMENT		4
+#define PPC_I_CACHE             4096
+#define PPC_D_CACHE             4096
+#define PPC_CACHE_ALIGNMENT	16
+#define PPC_INTERRUPT_MAX       71
+#define PPC_HAS_FPU     	0
+#define PPC_HAS_DOUBLE		0
+
+#define PPC_MSR_0		0x00009000
+#define PPC_MSR_1		0x00001000
+#define PPC_MSR_2		0x00001000
+#define PPC_MSR_3		0x00000000
+
+#elif defined(mpc750)
+
+#define CPU_MODEL_NAME  "PowerPC 750"
+
+#define PPC_ALIGNMENT		8
+#define PPC_I_CACHE		16384
+#define PPC_D_CACHE		16384
+  
+#else
+ 
+#error "Unsupported CPU Model"
+ 
+#endif
+
+/*
+ *  Application binary interfaces.
+ *
+ *  PPC_ABI MUST be defined as one of these.
+ *  Only PPC_ABI_POWEROPEN is currently fully supported.
+ *  Only EABI will be supported in the end when
+ *  the tools are there.
+ *  Only big endian is currently supported.
+ */
+/*
+ *  PowerOpen ABI.  This is Andy's hack of the
+ *  PowerOpen ABI to ELF.  ELF rather than a
+ *  XCOFF assembler is used.  This may work
+ *  if PPC_ASM == PPC_ASM_XCOFF is defined.
+ */
+#define PPC_ABI_POWEROPEN	0
+/*
+ *  GCC 2.7.0 munched version of EABI, with
+ *  PowerOpen calling convention and stack frames,
+ *  but EABI style indirect function calls.
+ */
+#define PPC_ABI_GCC27		1
+/*
+ *  SVR4 ABI
+ */
+#define PPC_ABI_SVR4		2
+/*
+ *  Embedded ABI
+ */
+#define PPC_ABI_EABI		3
+
+#if (PPC_ABI == PPC_ABI_POWEROPEN)
+#define PPC_STACK_ALIGNMENT	8
+#elif (PPC_ABI == PPC_ABI_GCC27)
+#define PPC_STACK_ALIGNMENT	8
+#elif (PPC_ABI == PPC_ABI_SVR4)
+#define PPC_STACK_ALIGNMENT	16
+#elif (PPC_ABI == PPC_ABI_EABI)
+#define PPC_STACK_ALIGNMENT	8
+#else
+#error  "PPC_ABI is not properly defined"
+#endif
+#ifndef PPC_ABI
+#error  "PPC_ABI is not properly defined"
+#endif
+
+/*
+ *  Assemblers.
+ *  PPC_ASM MUST be defined as one of these.
+ *
+ *  PPC_ASM_ELF:   ELF assembler. Currently used for all ABIs.
+ *  PPC_ASM_XCOFF: XCOFF assembler. May be needed for PowerOpen ABI.
+ *
+ *  NOTE: Only PPC_ABI_ELF is currently fully supported.
+ */
+
+#define PPC_ASM_ELF   0
+#define PPC_ASM_XCOFF 1
+
+/*
+ *  Use the default debug scheme defined in the architectural specification
+ *  if another model has not been specified.
+ */
+
+#ifndef PPC_DEBUG_MODEL
+#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD
+#endif
+
+/*
+ *  If the maximum number of exception sources has not been defined,
+ *  then default it to 16.
+ */
+
+#ifndef PPC_INTERRUPT_MAX
+#define PPC_INTERRUPT_MAX	16
+#endif
+
+/*
+ *  Unless specified otherwise, the cache line size is defaulted to 32.
+ *
+ *  The derive the power of 2 the cache line is.
+ */
+
+#ifndef PPC_CACHE_ALIGNMENT
+#define PPC_CACHE_ALIGNMENT 32
+#endif
+
+#if (PPC_CACHE_ALIGNMENT == 16)
+#define PPC_CACHE_ALIGN_POWER 4
+#elif (PPC_CACHE_ALIGNMENT == 32)
+#define PPC_CACHE_ALIGN_POWER 5
+#else
+#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
+#endif
+
+/*
+ *  Unless otherwise specified, assume the model has an IP/EP bit to
+ *  set the exception address prefix.
+ */
+
+#ifndef PPC_HAS_EXCEPTION_PREFIX
+#define PPC_HAS_EXCEPTION_PREFIX 1
+#endif
+
+/*
+ *  Unless otherwise specified, assume the model does NOT have
+ *  403 style EVPR register to set the exception address prefix.
+ */
+
+#ifndef PPC_HAS_EVPR
+#define PPC_HAS_EVPR 0
+#endif
+
+/*
+ *  If no low power mode model was specified, then assume there is none.
+ */
+
+#ifndef PPC_LOW_POWER_MODE
+#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
+#endif
+
+/*
+ *  Unless specified above, then assume the model has FP support.
+ */
+
+#ifndef PPC_HAS_FPU
+#define PPC_HAS_FPU 1
+#endif
+
+/*
+ *  Unless specified above, If the model has FP support, it is assumed to
+ *  support doubles (8-byte floating point numbers).
+ *
+ *  If the model does NOT have FP support, then the model does
+ *  NOT have double length FP registers. 
+ */
+
+#ifndef PPC_HAS_DOUBLE
+#if (PPC_HAS_FPU)
+#define PPC_HAS_DOUBLE 1
+#else
+#define PPC_HAS_DOUBLE 0
+#endif
+#endif
+
+/*
+ *  Unless specified above, then assume the model does NOT have critical
+ *  interrupt support.
+ */
+
+#ifndef PPC_HAS_RFCI
+#define PPC_HAS_RFCI 0
+#endif
+
+/*
+ *  Unless specified above, do not use the load/store multiple instructions
+ *  in a context switch.
+ */
+
+#ifndef PPC_USE_MULTIPLE
+#define PPC_USE_MULTIPLE 0
+#endif
+
+/*
+ *  The following exceptions are not maskable, and are not
+ *  necessarily predictable, so cannot be offered to RTEMS:
+ *    Alignment exception - handled by the CPU module
+ *    Data exceptions.
+ *    Instruction exceptions.
+ */
+
+/*
+ *  Base Interrupt vectors supported on all models.
+ */
+#define PPC_IRQ_SYSTEM_RESET	 0 /* 0x00100 - System reset.              */
+#define PPC_IRQ_MCHECK		 1 /* 0x00200 - Machine check              */
+#define PPC_IRQ_PROTECT		 2 /* 0x00300 - Protection violation       */
+#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
+#define PPC_IRQ_EXTERNAL	 4 /* 0x00500 - External interrupt         */
+#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
+#define PPC_IRQ_PROGRAM		 6 /* 0x00700 - Program exception          */
+#define PPC_IRQ_NOFP		 7 /* 0x00800 - Floating point unavailable */
+#define PPC_IRQ_DECREMENTER	 8 /* 0x00900 - Decrementer interrupt      */
+#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
+#define PPC_IRQ_RESERVED_B      10 /* 0x00a00 - Implementation Reserved    */
+#define PPC_IRQ_SCALL		11 /* 0x00c00 - System call                */
+#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
+#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
+#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
+
+#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
+
+#if defined(ppc403)
+                                  
+#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
+#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
+#define PPC_IRQ_FIT	 (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
+#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
+#define PPC_IRQ_DEBUG	 (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
+#define PPC_IRQ_LAST     PPC_IRQ_DEBUG    
+
+#elif defined(ppc601)
+#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
+#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
+
+#elif defined(ppc602)
+#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST) 
+
+#elif defined(ppc603)
+#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
+#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
+#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
+#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
+#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
+#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT    
+
+#elif defined(ppc603e)
+#define PPC_TLB_INST_MISS  (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/
+#define PPC_TLB_LOAD_MISS  (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load  */
+#define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */
+#define PPC_IRQ_ADDRBRK    (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */
+#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
+#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT    
+
+
+#elif defined(ppc604)
+#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
+#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
+#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT  
+
+#elif defined(mpc860) || defined(mpc821)
+#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
+#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
+#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
+#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
+#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
+#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
+#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
+#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
+#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
+#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
+#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
+#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
+#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
+#define PPC_IRQ_IRQ2		(PPC_STD_IRQ_LAST + 14)
+#define PPC_IRQ_LVL2		(PPC_STD_IRQ_LAST + 15)
+#define PPC_IRQ_IRQ3		(PPC_STD_IRQ_LAST + 16)
+#define PPC_IRQ_LVL3		(PPC_STD_IRQ_LAST + 17)
+#define PPC_IRQ_IRQ4		(PPC_STD_IRQ_LAST + 18)
+#define PPC_IRQ_LVL4		(PPC_STD_IRQ_LAST + 19)
+#define PPC_IRQ_IRQ5		(PPC_STD_IRQ_LAST + 20)
+#define PPC_IRQ_LVL5		(PPC_STD_IRQ_LAST + 21)
+#define PPC_IRQ_IRQ6		(PPC_STD_IRQ_LAST + 22)
+#define PPC_IRQ_LVL6		(PPC_STD_IRQ_LAST + 23)
+#define PPC_IRQ_IRQ7		(PPC_STD_IRQ_LAST + 24)
+#define PPC_IRQ_LVL7		(PPC_STD_IRQ_LAST + 25)
+#define PPC_IRQ_CPM_RESERVED_0	(PPC_STD_IRQ_LAST + 26)
+#define PPC_IRQ_CPM_PC4		(PPC_STD_IRQ_LAST + 27)
+#define PPC_IRQ_CPM_PC5		(PPC_STD_IRQ_LAST + 28)
+#define PPC_IRQ_CPM_SMC2	(PPC_STD_IRQ_LAST + 29)
+#define PPC_IRQ_CPM_SMC1	(PPC_STD_IRQ_LAST + 30)
+#define PPC_IRQ_CPM_SPI		(PPC_STD_IRQ_LAST + 31)
+#define PPC_IRQ_CPM_PC6		(PPC_STD_IRQ_LAST + 32)
+#define PPC_IRQ_CPM_TIMER4	(PPC_STD_IRQ_LAST + 33)
+#define PPC_IRQ_CPM_RESERVED_8	(PPC_STD_IRQ_LAST + 34)
+#define PPC_IRQ_CPM_PC7		(PPC_STD_IRQ_LAST + 35)
+#define PPC_IRQ_CPM_PC8		(PPC_STD_IRQ_LAST + 36)
+#define PPC_IRQ_CPM_PC9		(PPC_STD_IRQ_LAST + 37)
+#define PPC_IRQ_CPM_TIMER3	(PPC_STD_IRQ_LAST + 38)
+#define PPC_IRQ_CPM_RESERVED_D	(PPC_STD_IRQ_LAST + 39)
+#define PPC_IRQ_CPM_PC10	(PPC_STD_IRQ_LAST + 40)
+#define PPC_IRQ_CPM_PC11	(PPC_STD_IRQ_LAST + 41)
+#define PPC_IRQ_CPM_I2C		(PPC_STD_IRQ_LAST + 42)
+#define PPC_IRQ_CPM_RISC_TIMER	(PPC_STD_IRQ_LAST + 43)
+#define PPC_IRQ_CPM_TIMER2	(PPC_STD_IRQ_LAST + 44)
+#define PPC_IRQ_CPM_RESERVED_13	(PPC_STD_IRQ_LAST + 45)
+#define PPC_IRQ_CPM_IDMA2	(PPC_STD_IRQ_LAST + 46)
+#define PPC_IRQ_CPM_IDMA1	(PPC_STD_IRQ_LAST + 47)
+#define PPC_IRQ_CPM_SDMA_ERROR	(PPC_STD_IRQ_LAST + 48)
+#define PPC_IRQ_CPM_PC12	(PPC_STD_IRQ_LAST + 49)
+#define PPC_IRQ_CPM_PC13	(PPC_STD_IRQ_LAST + 50)
+#define PPC_IRQ_CPM_TIMER1	(PPC_STD_IRQ_LAST + 51)
+#define PPC_IRQ_CPM_PC14	(PPC_STD_IRQ_LAST + 52)
+#define PPC_IRQ_CPM_SCC4	(PPC_STD_IRQ_LAST + 53)
+#define PPC_IRQ_CPM_SCC3	(PPC_STD_IRQ_LAST + 54)
+#define PPC_IRQ_CPM_SCC2	(PPC_STD_IRQ_LAST + 55)
+#define PPC_IRQ_CPM_SCC1	(PPC_STD_IRQ_LAST + 56)
+#define PPC_IRQ_CPM_PC15	(PPC_STD_IRQ_LAST + 57)
+
+#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
+
+#endif
+
+/*
+ *  If the maximum number of exception sources is too low,
+ *  then fix it
+ */
+
+#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
+#undef PPC_INTERRUPT_MAX
+#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
+#endif
+
+/*
+ *  Machine Status Register (MSR) Constants Used by RTEMS
+ */
+
+/*
+ *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
+ *  IP for no apparent reason.
+ */
+
+#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
+#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
+#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
+
+#if (PPC_HAS_EXCEPTION_PREFIX)
+#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
+#else
+#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
+#endif
+
+#if (PPC_HAS_FPU)
+#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
+#else
+#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
+#endif
+
+#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
+#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
+#else
+#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
+#endif
+
+/*
+ *  Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming
+ *  Environments" and the manuals for various PPC models.
+ */
+
+#if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD)
+#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
+#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
+#define PPC_MSR_SE       0x000000400 /* bit 21 - single step trace enable */
+#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY)
+#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
+#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
+#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
+#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx)
+#define PPC_MSR_DE       0x000000200 /* bit 22 - debug exception enable */
+#define PPC_MSR_BE       0x000000000 /* bit 22 - branch trace enable */
+#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
+#else
+#error "MSR constants -- unknown PPC_DEBUG_MODEL!!"
+#endif
+
+#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
+#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
+
+#if (PPC_HAS_RFCI)
+#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
+#else
+#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
+#endif
+
+#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
+
+/*
+ *  Initial value for the FPSCR register
+ */
+
+#define PPC_INIT_FPSCR		0x000000f8
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! _INCLUDE_PPC_h */
+/* end of include file */
+
+
diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/ppctypes.h b/c/src/exec/score/cpu/powerpc/rtems/score/ppctypes.h
new file mode 100644
index 0000000000..62bdb35d10
--- /dev/null
+++ b/c/src/exec/score/cpu/powerpc/rtems/score/ppctypes.h
@@ -0,0 +1,73 @@
+/*  ppctypes.h
+ *
+ *  This include file contains type definitions pertaining to the PowerPC
+ *  processor family.
+ *
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/cpu/no_cpu/no_cputypes.h:
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __PPC_TYPES_h
+#define __PPC_TYPES_h
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This section defines the basic types for this processor.
+ */
+
+typedef unsigned char  unsigned8;      /* unsigned 8-bit  integer */
+typedef unsigned short unsigned16;     /* unsigned 16-bit integer */
+typedef unsigned int   unsigned32;     /* unsigned 32-bit integer */
+typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
+
+typedef unsigned32     Priority_Bit_map_control;
+
+typedef signed char      signed8;      /* 8-bit  signed integer */
+typedef signed short     signed16;     /* 16-bit signed integer */
+typedef signed int       signed32;     /* 32-bit signed integer */
+typedef signed long long signed64;     /* 64 bit signed integer */
+
+typedef unsigned32 boolean;     /* Boolean value   */
+
+typedef float          single_precision;     /* single precision float */
+typedef double         double_precision;     /* double precision float */
+
+typedef void ppc_isr;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* !ASM */
+
+#endif
+/* end of include file */
diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/types.h b/c/src/exec/score/cpu/powerpc/rtems/score/types.h
new file mode 100644
index 0000000000..62bdb35d10
--- /dev/null
+++ b/c/src/exec/score/cpu/powerpc/rtems/score/types.h
@@ -0,0 +1,73 @@
+/*  ppctypes.h
+ *
+ *  This include file contains type definitions pertaining to the PowerPC
+ *  processor family.
+ *
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/cpu/no_cpu/no_cputypes.h:
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __PPC_TYPES_h
+#define __PPC_TYPES_h
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This section defines the basic types for this processor.
+ */
+
+typedef unsigned char  unsigned8;      /* unsigned 8-bit  integer */
+typedef unsigned short unsigned16;     /* unsigned 16-bit integer */
+typedef unsigned int   unsigned32;     /* unsigned 32-bit integer */
+typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
+
+typedef unsigned32     Priority_Bit_map_control;
+
+typedef signed char      signed8;      /* 8-bit  signed integer */
+typedef signed short     signed16;     /* 16-bit signed integer */
+typedef signed int       signed32;     /* 32-bit signed integer */
+typedef signed long long signed64;     /* 64 bit signed integer */
+
+typedef unsigned32 boolean;     /* Boolean value   */
+
+typedef float          single_precision;     /* single precision float */
+typedef double         double_precision;     /* double precision float */
+
+typedef void ppc_isr;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* !ASM */
+
+#endif
+/* end of include file */
diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/Makefile.in b/c/src/exec/score/cpu/powerpc/shared/Makefile.in
index d2278f291a..1b6dd81aa4 100644
--- a/c/src/exec/score/cpu/powerpc/rtems/score/Makefile.in
+++ b/c/src/exec/score/cpu/powerpc/shared/Makefile.in
@@ -1,12 +1,12 @@
 #
-#  $Id$
+# $Id$
 #
 
 @SET_MAKE@
 srcdir = @srcdir@
 top_srcdir = @top_srcdir@
-top_builddir = ../../../../../../../..
-subdir = c/src/exec/score/cpu/powerpc/rtems/score
+top_builddir = ../../../../../../..
+subdir = c/src/exec/score/cpu/powerpc/shared
 
 INSTALL = @INSTALL@
 
@@ -15,20 +15,26 @@ PROJECT_ROOT = @PROJECT_ROOT@
 
 VPATH = @srcdir@
 
+RELS=
+
 # C source names, if any, go here -- minus the .c
-C_PIECES=
+C_PIECES =
 C_FILES=$(C_PIECES:%=%.c)
 C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
 
-H_PIECES=cpu.h ppc.h ppctypes.h
-H_FILES=$(H_PIECES:%=$(srcdir)/%)
+ROOT_H_PIECES = asm.h
+ROOT_H_FILES=$(ROOT_H_PIECES:%=$(srcdir)/%)
+RTEMS_SCORE_H_PIECES=ppc.h ppctypes.h
+RTEMS_SCORE_H_FILES=$(RTEMS_SCORE_H_PIECES:%=$(srcdir)/%)
+H_PIECES=$(ROOT_H_PIECES) $(RTEMS_SCORE_H_PIECES)
+H_FILES=$(H_PIECES%=$(srcdir)/%)
 
 # Assembly source names, if any, go here -- minus the .S
-S_PIECES=
+S_PIECES =
 S_FILES=$(S_PIECES:%=%.S)
 S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
 
-SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
+SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES)
 OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
 
 include $(RTEMS_ROOT)/make/custom/${RTEMS_BSP}.cfg
@@ -39,8 +45,8 @@ include $(RTEMS_ROOT)/make/leaf.cfg
 #
 
 DEFINES  +=
-CPPFLAGS +=
-CFLAGS   += 
+CPPFLAGS += 
+CFLAGS   += $(CFLAGS_OS_V)
 
 LD_PATHS  +=
 LD_LIBS   +=
@@ -53,17 +59,18 @@ LDFLAGS   +=
 #  'make clobber' already includes 'make clean'
 #
 
-CLEAN_ADDITIONS +=
-CLOBBER_ADDITIONS += $(BUILT_SOURCES)
+CLEAN_ADDITIONS += 
+CLOBBER_ADDITIONS +=
+
+all:$(SRCS) preinstall
 
 # Install the program(s), appending _g or _p as appropriate.
 # for include files, just use $(INSTALL_CHANGE)
-all: install-headers
-
-install-headers: ${H_FILES}
-	$(INSTALL_CHANGE) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
+install:  all
 
-preinstall: install-headers
+preinstall: ${ARCH}
+	$(INSTALL_CHANGE) -m 444 ${RTEMS_SCORE_H_FILES} $(PROJECT_INCLUDE)/rtems/score
+	$(INSTALL_CHANGE) -m 444 ${ROOT_H_FILES} $(PROJECT_INCLUDE)
 
 Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
 	cd $(top_builddir) \
diff --git a/c/src/exec/score/cpu/powerpc/shared/asm.h b/c/src/exec/score/cpu/powerpc/shared/asm.h
new file mode 100644
index 0000000000..af14c95665
--- /dev/null
+++ b/c/src/exec/score/cpu/powerpc/shared/asm.h
@@ -0,0 +1,275 @@
+/*  asm.h
+ *
+ *  This include file attempts to address the problems
+ *  caused by incompatible flavors of assemblers and
+ *  toolsets.  It primarily addresses variations in the
+ *  use of leading underscores on symbols and the requirement
+ *  that register names be preceded by a %.
+ *
+ *
+ *  NOTE: The spacing in the use of these macros
+ *        is critical to them working as advertised.
+ *
+ *  COPYRIGHT:
+ *
+ *  This file is based on similar code found in newlib available
+ *  from ftp.cygnus.com.  The file which was used had no copyright
+ *  notice.  This file is freely distributable as long as the source
+ *  of the file is noted.  This file is:
+ *
+ *  COPYRIGHT (c) 1995.
+ *  i-cubed ltd.
+ *
+ *  COPYRIGHT (c) 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  $Id$
+ */
+
+#ifndef __PPC_ASM_h
+#define __PPC_ASM_h
+
+/*
+ *  Indicate we are in an assembly file and get the basic CPU definitions.
+ */
+
+#ifndef ASM
+#define ASM
+#endif
+#include <rtems/score/targopts.h>
+#include <rtems/score/ppc.h>
+
+/*
+ *  Recent versions of GNU cpp define variables which indicate the
+ *  need for underscores and percents.  If not using GNU cpp or
+ *  the version does not support this, then you will obviously
+ *  have to define these as appropriate.
+ */
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__ 
+#endif
+
+#ifndef __REGISTER_PREFIX__
+#define __REGISTER_PREFIX__
+#endif
+
+#ifndef __FLOAT_REGISTER_PREFIX__
+#define __FLOAT_REGISTER_PREFIX__  __REGISTER_PREFIX__
+#endif
+
+#if (PPC_ABI == PPC_ABI_POWEROPEN)
+#ifndef __PROC_LABEL_PREFIX__
+#define __PROC_LABEL_PREFIX__ .
+#endif
+#endif
+
+#ifndef __PROC_LABEL_PREFIX__
+#define __PROC_LABEL_PREFIX__  __USER_LABEL_PREFIX__
+#endif
+
+/* ANSI concatenation macros.  */
+
+#define CONCAT1(a, b) CONCAT2(a, b)
+#define CONCAT2(a, b) a ## b
+
+/* Use the right prefix for global labels.  */
+
+#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
+
+/* Use the right prefix for procedure labels.  */
+
+#define PROC(x) CONCAT1 (__PROC_LABEL_PREFIX__, x)
+
+/* Use the right prefix for registers.  */
+
+#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
+
+/* Use the right prefix for floating point registers.  */
+
+#define FREG(x) CONCAT1 (__FLOAT_REGISTER_PREFIX__, x)
+
+/*
+ *  define macros for all of the registers on this CPU
+ *
+ *  EXAMPLE:     #define d0 REG (d0)
+ */
+#define r0 REG(0)
+#define r1 REG(1)
+#define r2 REG(2)
+#define r3 REG(3)
+#define r4 REG(4)
+#define r5 REG(5)
+#define r6 REG(6)
+#define r7 REG(7)
+#define r8 REG(8)
+#define r9 REG(9)
+#define r10 REG(10)
+#define r11 REG(11)
+#define r12 REG(12)
+#define r13 REG(13)
+#define r14 REG(14)
+#define r15 REG(15)
+#define r16 REG(16)
+#define r17 REG(17)
+#define r18 REG(18)
+#define r19 REG(19)
+#define r20 REG(20)
+#define r21 REG(21)
+#define r22 REG(22)
+#define r23 REG(23)
+#define r24 REG(24)
+#define r25 REG(25)
+#define r26 REG(26)
+#define r27 REG(27)
+#define r28 REG(28)
+#define r29 REG(29)
+#define r30 REG(30)
+#define r31 REG(31)
+#define f0 FREG(0)
+#define f1 FREG(1)
+#define f2 FREG(2)
+#define f3 FREG(3)
+#define f4 FREG(4)
+#define f5 FREG(5)
+#define f6 FREG(6)
+#define f7 FREG(7)
+#define f8 FREG(8)
+#define f9 FREG(9)
+#define f10 FREG(10)
+#define f11 FREG(11)
+#define f12 FREG(12)
+#define f13 FREG(13)
+#define f14 FREG(14)
+#define f15 FREG(15)
+#define f16 FREG(16)
+#define f17 FREG(17)
+#define f18 FREG(18)
+#define f19 FREG(19)
+#define f20 FREG(20)
+#define f21 FREG(21)
+#define f22 FREG(22)
+#define f23 FREG(23)
+#define f24 FREG(24)
+#define f25 FREG(25)
+#define f26 FREG(26)
+#define f27 FREG(27)
+#define f28 FREG(28)
+#define f29 FREG(29)
+#define f30 FREG(30)
+#define f31 FREG(31)
+
+/*
+ * Some special purpose registers (SPRs).
+ */
+#define srr0	0x01a
+#define srr1	0x01b
+#define srr2	0x3de	/* IBM 400 series only */
+#define srr3	0x3df	/* IBM 400 series only */
+#define sprg0	0x110
+#define sprg1	0x111
+#define sprg2	0x112
+#define sprg3	0x113
+
+
+/* the following SPR/DCR registers exist only in IBM 400 series */
+#define dear	0x3d5	
+#define evpr    0x3d6   /* SPR: exception vector prefix register   */
+#define iccr    0x3fb   /* SPR: instruction cache control reg.     */
+#define dccr    0x3fa   /* SPR: data cache control reg.            */
+
+#define exisr   0x040   /* DCR: external interrupt status register */
+#define exier   0x042   /* DCR: external interrupt enable register */
+#define br0     0x080   /* DCR: memory bank register 0             */
+#define br1     0x081   /* DCR: memory bank register 1             */
+#define br2     0x082   /* DCR: memory bank register 2             */
+#define br3     0x083   /* DCR: memory bank register 3             */
+#define br4     0x084   /* DCR: memory bank register 4             */
+#define br5     0x085   /* DCR: memory bank register 5             */
+#define br6     0x086   /* DCR: memory bank register 6             */
+#define br7     0x087   /* DCR: memory bank register 7             */
+/* end of IBM400 series register definitions */
+
+/* The following registers are for the MPC8x0 */
+#define der     0x095   /* Debug Enable Register */
+/* end of MPC8x0 registers */
+
+/*
+ *  Following must be tailor for a particular flavor of the C compiler.
+ *  They may need to put underscores in front of the symbols.
+ */
+
+#define PUBLIC_VAR(sym) .globl SYM (sym)
+#define EXTERN_VAR(sym) .extern SYM (sym)
+#define PUBLIC_PROC(sym) .globl PROC (sym)
+#define EXTERN_PROC(sym) .extern PROC (sym)
+
+/* Other potentially assembler specific operations */
+#if PPC_ASM == PPC_ASM_ELF
+#define ALIGN(n,p)	.align	p
+#define DESCRIPTOR(x)	\
+	.section .descriptors,"aw";	\
+	PUBLIC_VAR (x);			\
+SYM (x):;				\
+	.long	PROC (x);		\
+	.long	s.got;			\
+	.long	0
+
+#define EXT_SYM_REF(x)	.long x
+#define EXT_PROC_REF(x)	.long x
+
+/*
+ *  Define macros to handle section beginning and ends.
+ */
+
+#define BEGIN_CODE_DCL .text
+#define END_CODE_DCL
+#define BEGIN_DATA_DCL .data
+#define END_DATA_DCL
+#define BEGIN_CODE .text
+#define END_CODE
+#define BEGIN_DATA .data
+#define END_DATA
+#define BEGIN_BSS  .bss
+#define END_BSS
+#define END
+
+#elif PPC_ASM == PPC_ASM_XCOFF
+#define ALIGN(n,p)	.align	p
+#define DESCRIPTOR(x)	\
+	.csect	x[DS];		\
+	.globl	x[DS];		\
+	.long	PROC (x)[PR];	\
+	.long	TOC[tc0]
+
+#define EXT_SYM_REF(x)	.long x[RW]
+#define EXT_PROC_REF(x)	.long x[DS]
+
+/*
+ *  Define macros to handle section beginning and ends.
+ */
+
+#define BEGIN_CODE_DCL .csect .text[PR]
+#define END_CODE_DCL
+#define BEGIN_DATA_DCL .csect .data[RW]
+#define END_DATA_DCL
+#define BEGIN_CODE .csect .text[PR]
+#define END_CODE
+#define BEGIN_DATA .csect .data[RW]
+#define END_DATA
+#define BEGIN_BSS  .bss
+#define END_BSS
+#define END
+
+#else
+#error "PPC_ASM_TYPE is not properly defined"
+#endif
+#ifndef PPC_ASM
+#error "PPC_ASM_TYPE is not properly defined"
+#endif
+
+
+#endif
+/* end of include file */
+
+
diff --git a/c/src/exec/score/cpu/powerpc/shared/ppc.h b/c/src/exec/score/cpu/powerpc/shared/ppc.h
new file mode 100644
index 0000000000..27f8a4cfc1
--- /dev/null
+++ b/c/src/exec/score/cpu/powerpc/shared/ppc.h
@@ -0,0 +1,615 @@
+/*  ppc.h
+ *
+ *  This file contains definitions for the IBM/Motorola PowerPC
+ *  family members.
+ *
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *
+ * Note:
+ *      This file is included by both C and assembler code ( -DASM )
+ *
+ *  $Id$
+ */
+
+
+#ifndef _INCLUDE_PPC_h
+#define _INCLUDE_PPC_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  Define the name of the CPU family.
+ */
+
+#define CPU_NAME "PowerPC"
+
+/*
+ *  This file contains the information required to build
+ *  RTEMS for a particular member of the PowerPC family.  It does
+ *  this by setting variables to indicate which implementation
+ *  dependent features are present in a particular member
+ *  of the family.
+ *
+ *  The following architectural feature definitions are defaulted
+ *  unless specifically set by the model definition:
+ *
+ *    + PPC_DEBUG_MODEL          - PPC_DEBUG_MODEL_STANDARD
+ *    + PPC_INTERRUPT_MAX        - 16
+ *    + PPC_CACHE_ALIGNMENT      - 32
+ *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
+ *    + PPC_HAS_EXCEPTION_PREFIX - 1
+ *    + PPC_HAS_FPU              - 1
+ *    + PPC_HAS_DOUBLE           - 1 if PPC_HAS_FPU, 
+ *                               - 0 otherwise
+ *    + PPC_USE_MULTIPLE         - 0
+ */
+ 
+/*
+ *  Define the debugging assistance models found in the PPC family.
+ *
+ *  Standard:         single step and branch trace
+ *  Single Step Only: single step only
+ *  IBM 4xx:          debug exception
+ */
+
+#define PPC_DEBUG_MODEL_STANDARD         1
+#define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2
+#define PPC_DEBUG_MODEL_IBM4xx           3
+
+/*
+ *  Define the low power mode models
+ *
+ *  Standard:   as defined for 603e
+ *  Nap Mode:   nap mode only (604)
+ *  XXX 403GB, 603, 603e, 604, 821
+ */
+
+#define PPC_LOW_POWER_MODE_NONE      0
+#define PPC_LOW_POWER_MODE_STANDARD  1
+
+#if defined(ppc403)
+/*
+ *  IBM 403
+ *
+ *  Developed for 403GA.  Book checked for 403GB.
+ *
+ *  Does not have user mode.
+ */
+ 
+#define CPU_MODEL_NAME "PowerPC 403"
+#define PPC_ALIGNMENT		4  
+#define PPC_CACHE_ALIGNMENT	16
+#define PPC_HAS_RFCI    	1
+#define PPC_HAS_FPU     	0
+#define PPC_USE_MULTIPLE	1
+#define PPC_I_CACHE		2048
+#define PPC_D_CACHE		1024
+
+#define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_IBM4xx
+#define PPC_HAS_EXCEPTION_PREFIX 0
+#define PPC_HAS_EVPR             1
+
+#elif defined(ppc601)
+/*
+ *  Submitted with original port -- book checked only.
+ */
+ 
+#define CPU_MODEL_NAME  "PowerPC 601"
+
+#define PPC_ALIGNMENT		8
+#define PPC_USE_MULTIPLE	1
+#define PPC_I_CACHE		0
+#define PPC_D_CACHE		32768
+
+#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY
+
+#elif defined(ppc602)
+/*
+ *  Submitted with original port -- book checked only.
+ */
+ 
+#define CPU_MODEL_NAME  "PowerPC 602"
+
+#define PPC_ALIGNMENT		4
+#define PPC_HAS_DOUBLE		0
+#define PPC_I_CACHE		4096
+#define PPC_D_CACHE		4096
+
+#elif defined(ppc603)
+/*
+ *  Submitted with original port -- book checked only.
+ */
+ 
+#define CPU_MODEL_NAME  "PowerPC 603"
+
+#define PPC_ALIGNMENT		8
+#define PPC_I_CACHE		8192
+#define PPC_D_CACHE		8192
+
+#elif defined(ppc603e)
+ 
+#define CPU_MODEL_NAME  "PowerPC 603e"
+/*
+ *  Submitted with original port.
+ *
+ *  Known to work on real hardware.
+ */
+
+#define PPC_ALIGNMENT		8
+#define PPC_I_CACHE		16384
+#define PPC_D_CACHE		16384
+
+#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
+
+#elif defined(ppc604)
+/*
+ *  Submitted with original port -- book checked only.
+ */
+ 
+#define CPU_MODEL_NAME  "PowerPC 604"
+
+#define PPC_ALIGNMENT		8
+#define PPC_I_CACHE		16384
+#define PPC_D_CACHE		16384
+ 
+#elif defined(mpc860)
+/* 
+ *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98 
+ */ 
+#define CPU_MODEL_NAME  "PowerPC MPC860"
+
+#define PPC_ALIGNMENT		4
+#define PPC_I_CACHE             4096
+#define PPC_D_CACHE             4096
+#define PPC_CACHE_ALIGNMENT	16
+#define PPC_INTERRUPT_MAX       71
+#define PPC_HAS_FPU     	0
+#define PPC_HAS_DOUBLE		0
+#define PPC_USE_MULTIPLE	1
+#define PPC_USE_SPRG            1
+
+#define PPC_MSR_0		0x00009000
+#define PPC_MSR_1		0x00001000
+#define PPC_MSR_2		0x00001000
+#define PPC_MSR_3		0x00000000
+
+#elif defined(mpc821)
+/* 
+ *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
+ */ 
+#define CPU_MODEL_NAME  "PowerPC MPC821"
+
+#define PPC_ALIGNMENT		4
+#define PPC_I_CACHE             4096
+#define PPC_D_CACHE             4096
+#define PPC_CACHE_ALIGNMENT	16
+#define PPC_INTERRUPT_MAX       71
+#define PPC_HAS_FPU     	0
+#define PPC_HAS_DOUBLE		0
+
+#define PPC_MSR_0		0x00009000
+#define PPC_MSR_1		0x00001000
+#define PPC_MSR_2		0x00001000
+#define PPC_MSR_3		0x00000000
+
+#elif defined(mpc750)
+
+#define CPU_MODEL_NAME  "PowerPC 750"
+
+#define PPC_ALIGNMENT		8
+#define PPC_I_CACHE		16384
+#define PPC_D_CACHE		16384
+  
+#else
+ 
+#error "Unsupported CPU Model"
+ 
+#endif
+
+/*
+ *  Application binary interfaces.
+ *
+ *  PPC_ABI MUST be defined as one of these.
+ *  Only PPC_ABI_POWEROPEN is currently fully supported.
+ *  Only EABI will be supported in the end when
+ *  the tools are there.
+ *  Only big endian is currently supported.
+ */
+/*
+ *  PowerOpen ABI.  This is Andy's hack of the
+ *  PowerOpen ABI to ELF.  ELF rather than a
+ *  XCOFF assembler is used.  This may work
+ *  if PPC_ASM == PPC_ASM_XCOFF is defined.
+ */
+#define PPC_ABI_POWEROPEN	0
+/*
+ *  GCC 2.7.0 munched version of EABI, with
+ *  PowerOpen calling convention and stack frames,
+ *  but EABI style indirect function calls.
+ */
+#define PPC_ABI_GCC27		1
+/*
+ *  SVR4 ABI
+ */
+#define PPC_ABI_SVR4		2
+/*
+ *  Embedded ABI
+ */
+#define PPC_ABI_EABI		3
+
+#if (PPC_ABI == PPC_ABI_POWEROPEN)
+#define PPC_STACK_ALIGNMENT	8
+#elif (PPC_ABI == PPC_ABI_GCC27)
+#define PPC_STACK_ALIGNMENT	8
+#elif (PPC_ABI == PPC_ABI_SVR4)
+#define PPC_STACK_ALIGNMENT	16
+#elif (PPC_ABI == PPC_ABI_EABI)
+#define PPC_STACK_ALIGNMENT	8
+#else
+#error  "PPC_ABI is not properly defined"
+#endif
+#ifndef PPC_ABI
+#error  "PPC_ABI is not properly defined"
+#endif
+
+/*
+ *  Assemblers.
+ *  PPC_ASM MUST be defined as one of these.
+ *
+ *  PPC_ASM_ELF:   ELF assembler. Currently used for all ABIs.
+ *  PPC_ASM_XCOFF: XCOFF assembler. May be needed for PowerOpen ABI.
+ *
+ *  NOTE: Only PPC_ABI_ELF is currently fully supported.
+ */
+
+#define PPC_ASM_ELF   0
+#define PPC_ASM_XCOFF 1
+
+/*
+ *  Use the default debug scheme defined in the architectural specification
+ *  if another model has not been specified.
+ */
+
+#ifndef PPC_DEBUG_MODEL
+#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD
+#endif
+
+/*
+ *  If the maximum number of exception sources has not been defined,
+ *  then default it to 16.
+ */
+
+#ifndef PPC_INTERRUPT_MAX
+#define PPC_INTERRUPT_MAX	16
+#endif
+
+/*
+ *  Unless specified otherwise, the cache line size is defaulted to 32.
+ *
+ *  The derive the power of 2 the cache line is.
+ */
+
+#ifndef PPC_CACHE_ALIGNMENT
+#define PPC_CACHE_ALIGNMENT 32
+#endif
+
+#if (PPC_CACHE_ALIGNMENT == 16)
+#define PPC_CACHE_ALIGN_POWER 4
+#elif (PPC_CACHE_ALIGNMENT == 32)
+#define PPC_CACHE_ALIGN_POWER 5
+#else
+#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
+#endif
+
+/*
+ *  Unless otherwise specified, assume the model has an IP/EP bit to
+ *  set the exception address prefix.
+ */
+
+#ifndef PPC_HAS_EXCEPTION_PREFIX
+#define PPC_HAS_EXCEPTION_PREFIX 1
+#endif
+
+/*
+ *  Unless otherwise specified, assume the model does NOT have
+ *  403 style EVPR register to set the exception address prefix.
+ */
+
+#ifndef PPC_HAS_EVPR
+#define PPC_HAS_EVPR 0
+#endif
+
+/*
+ *  If no low power mode model was specified, then assume there is none.
+ */
+
+#ifndef PPC_LOW_POWER_MODE
+#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
+#endif
+
+/*
+ *  Unless specified above, then assume the model has FP support.
+ */
+
+#ifndef PPC_HAS_FPU
+#define PPC_HAS_FPU 1
+#endif
+
+/*
+ *  Unless specified above, If the model has FP support, it is assumed to
+ *  support doubles (8-byte floating point numbers).
+ *
+ *  If the model does NOT have FP support, then the model does
+ *  NOT have double length FP registers. 
+ */
+
+#ifndef PPC_HAS_DOUBLE
+#if (PPC_HAS_FPU)
+#define PPC_HAS_DOUBLE 1
+#else
+#define PPC_HAS_DOUBLE 0
+#endif
+#endif
+
+/*
+ *  Unless specified above, then assume the model does NOT have critical
+ *  interrupt support.
+ */
+
+#ifndef PPC_HAS_RFCI
+#define PPC_HAS_RFCI 0
+#endif
+
+/*
+ *  Unless specified above, do not use the load/store multiple instructions
+ *  in a context switch.
+ */
+
+#ifndef PPC_USE_MULTIPLE
+#define PPC_USE_MULTIPLE 0
+#endif
+
+/*
+ *  The following exceptions are not maskable, and are not
+ *  necessarily predictable, so cannot be offered to RTEMS:
+ *    Alignment exception - handled by the CPU module
+ *    Data exceptions.
+ *    Instruction exceptions.
+ */
+
+/*
+ *  Base Interrupt vectors supported on all models.
+ */
+#define PPC_IRQ_SYSTEM_RESET	 0 /* 0x00100 - System reset.              */
+#define PPC_IRQ_MCHECK		 1 /* 0x00200 - Machine check              */
+#define PPC_IRQ_PROTECT		 2 /* 0x00300 - Protection violation       */
+#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
+#define PPC_IRQ_EXTERNAL	 4 /* 0x00500 - External interrupt         */
+#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
+#define PPC_IRQ_PROGRAM		 6 /* 0x00700 - Program exception          */
+#define PPC_IRQ_NOFP		 7 /* 0x00800 - Floating point unavailable */
+#define PPC_IRQ_DECREMENTER	 8 /* 0x00900 - Decrementer interrupt      */
+#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
+#define PPC_IRQ_RESERVED_B      10 /* 0x00a00 - Implementation Reserved    */
+#define PPC_IRQ_SCALL		11 /* 0x00c00 - System call                */
+#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
+#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
+#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
+
+#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
+
+#if defined(ppc403)
+                                  
+#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
+#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
+#define PPC_IRQ_FIT	 (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
+#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
+#define PPC_IRQ_DEBUG	 (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
+#define PPC_IRQ_LAST     PPC_IRQ_DEBUG    
+
+#elif defined(ppc601)
+#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
+#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
+
+#elif defined(ppc602)
+#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST) 
+
+#elif defined(ppc603)
+#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
+#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
+#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
+#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
+#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
+#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT    
+
+#elif defined(ppc603e)
+#define PPC_TLB_INST_MISS  (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/
+#define PPC_TLB_LOAD_MISS  (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load  */
+#define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */
+#define PPC_IRQ_ADDRBRK    (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */
+#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
+#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT    
+
+
+#elif defined(ppc604)
+#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
+#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
+#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT  
+
+#elif defined(mpc860) || defined(mpc821)
+#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
+#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
+#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
+#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
+#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
+#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
+#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
+#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
+#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
+#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
+#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
+#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
+#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
+#define PPC_IRQ_IRQ2		(PPC_STD_IRQ_LAST + 14)
+#define PPC_IRQ_LVL2		(PPC_STD_IRQ_LAST + 15)
+#define PPC_IRQ_IRQ3		(PPC_STD_IRQ_LAST + 16)
+#define PPC_IRQ_LVL3		(PPC_STD_IRQ_LAST + 17)
+#define PPC_IRQ_IRQ4		(PPC_STD_IRQ_LAST + 18)
+#define PPC_IRQ_LVL4		(PPC_STD_IRQ_LAST + 19)
+#define PPC_IRQ_IRQ5		(PPC_STD_IRQ_LAST + 20)
+#define PPC_IRQ_LVL5		(PPC_STD_IRQ_LAST + 21)
+#define PPC_IRQ_IRQ6		(PPC_STD_IRQ_LAST + 22)
+#define PPC_IRQ_LVL6		(PPC_STD_IRQ_LAST + 23)
+#define PPC_IRQ_IRQ7		(PPC_STD_IRQ_LAST + 24)
+#define PPC_IRQ_LVL7		(PPC_STD_IRQ_LAST + 25)
+#define PPC_IRQ_CPM_RESERVED_0	(PPC_STD_IRQ_LAST + 26)
+#define PPC_IRQ_CPM_PC4		(PPC_STD_IRQ_LAST + 27)
+#define PPC_IRQ_CPM_PC5		(PPC_STD_IRQ_LAST + 28)
+#define PPC_IRQ_CPM_SMC2	(PPC_STD_IRQ_LAST + 29)
+#define PPC_IRQ_CPM_SMC1	(PPC_STD_IRQ_LAST + 30)
+#define PPC_IRQ_CPM_SPI		(PPC_STD_IRQ_LAST + 31)
+#define PPC_IRQ_CPM_PC6		(PPC_STD_IRQ_LAST + 32)
+#define PPC_IRQ_CPM_TIMER4	(PPC_STD_IRQ_LAST + 33)
+#define PPC_IRQ_CPM_RESERVED_8	(PPC_STD_IRQ_LAST + 34)
+#define PPC_IRQ_CPM_PC7		(PPC_STD_IRQ_LAST + 35)
+#define PPC_IRQ_CPM_PC8		(PPC_STD_IRQ_LAST + 36)
+#define PPC_IRQ_CPM_PC9		(PPC_STD_IRQ_LAST + 37)
+#define PPC_IRQ_CPM_TIMER3	(PPC_STD_IRQ_LAST + 38)
+#define PPC_IRQ_CPM_RESERVED_D	(PPC_STD_IRQ_LAST + 39)
+#define PPC_IRQ_CPM_PC10	(PPC_STD_IRQ_LAST + 40)
+#define PPC_IRQ_CPM_PC11	(PPC_STD_IRQ_LAST + 41)
+#define PPC_IRQ_CPM_I2C		(PPC_STD_IRQ_LAST + 42)
+#define PPC_IRQ_CPM_RISC_TIMER	(PPC_STD_IRQ_LAST + 43)
+#define PPC_IRQ_CPM_TIMER2	(PPC_STD_IRQ_LAST + 44)
+#define PPC_IRQ_CPM_RESERVED_13	(PPC_STD_IRQ_LAST + 45)
+#define PPC_IRQ_CPM_IDMA2	(PPC_STD_IRQ_LAST + 46)
+#define PPC_IRQ_CPM_IDMA1	(PPC_STD_IRQ_LAST + 47)
+#define PPC_IRQ_CPM_SDMA_ERROR	(PPC_STD_IRQ_LAST + 48)
+#define PPC_IRQ_CPM_PC12	(PPC_STD_IRQ_LAST + 49)
+#define PPC_IRQ_CPM_PC13	(PPC_STD_IRQ_LAST + 50)
+#define PPC_IRQ_CPM_TIMER1	(PPC_STD_IRQ_LAST + 51)
+#define PPC_IRQ_CPM_PC14	(PPC_STD_IRQ_LAST + 52)
+#define PPC_IRQ_CPM_SCC4	(PPC_STD_IRQ_LAST + 53)
+#define PPC_IRQ_CPM_SCC3	(PPC_STD_IRQ_LAST + 54)
+#define PPC_IRQ_CPM_SCC2	(PPC_STD_IRQ_LAST + 55)
+#define PPC_IRQ_CPM_SCC1	(PPC_STD_IRQ_LAST + 56)
+#define PPC_IRQ_CPM_PC15	(PPC_STD_IRQ_LAST + 57)
+
+#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
+
+#endif
+
+/*
+ *  If the maximum number of exception sources is too low,
+ *  then fix it
+ */
+
+#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
+#undef PPC_INTERRUPT_MAX
+#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
+#endif
+
+/*
+ *  Machine Status Register (MSR) Constants Used by RTEMS
+ */
+
+/*
+ *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
+ *  IP for no apparent reason.
+ */
+
+#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
+#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
+#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
+
+#if (PPC_HAS_EXCEPTION_PREFIX)
+#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
+#else
+#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
+#endif
+
+#if (PPC_HAS_FPU)
+#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
+#else
+#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
+#endif
+
+#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
+#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
+#else
+#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
+#endif
+
+/*
+ *  Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming
+ *  Environments" and the manuals for various PPC models.
+ */
+
+#if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD)
+#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
+#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
+#define PPC_MSR_SE       0x000000400 /* bit 21 - single step trace enable */
+#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY)
+#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
+#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
+#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
+#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx)
+#define PPC_MSR_DE       0x000000200 /* bit 22 - debug exception enable */
+#define PPC_MSR_BE       0x000000000 /* bit 22 - branch trace enable */
+#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
+#else
+#error "MSR constants -- unknown PPC_DEBUG_MODEL!!"
+#endif
+
+#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
+#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
+
+#if (PPC_HAS_RFCI)
+#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
+#else
+#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
+#endif
+
+#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
+
+/*
+ *  Initial value for the FPSCR register
+ */
+
+#define PPC_INIT_FPSCR		0x000000f8
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! _INCLUDE_PPC_h */
+/* end of include file */
+
+
diff --git a/c/src/exec/score/cpu/powerpc/shared/ppctypes.h b/c/src/exec/score/cpu/powerpc/shared/ppctypes.h
new file mode 100644
index 0000000000..62bdb35d10
--- /dev/null
+++ b/c/src/exec/score/cpu/powerpc/shared/ppctypes.h
@@ -0,0 +1,73 @@
+/*  ppctypes.h
+ *
+ *  This include file contains type definitions pertaining to the PowerPC
+ *  processor family.
+ *
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/cpu/no_cpu/no_cputypes.h:
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __PPC_TYPES_h
+#define __PPC_TYPES_h
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This section defines the basic types for this processor.
+ */
+
+typedef unsigned char  unsigned8;      /* unsigned 8-bit  integer */
+typedef unsigned short unsigned16;     /* unsigned 16-bit integer */
+typedef unsigned int   unsigned32;     /* unsigned 32-bit integer */
+typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
+
+typedef unsigned32     Priority_Bit_map_control;
+
+typedef signed char      signed8;      /* 8-bit  signed integer */
+typedef signed short     signed16;     /* 16-bit signed integer */
+typedef signed int       signed32;     /* 32-bit signed integer */
+typedef signed long long signed64;     /* 64 bit signed integer */
+
+typedef unsigned32 boolean;     /* Boolean value   */
+
+typedef float          single_precision;     /* single precision float */
+typedef double         double_precision;     /* double precision float */
+
+typedef void ppc_isr;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* !ASM */
+
+#endif
+/* end of include file */