Yet another part of automake VI from Ralf Corsepius <corsepiu@faw.uni-ulm.de>:

> 4) rtems-rc-19990202-0.diff /reorg-score-cpu.sh
>
> reorg-score-cpu.sh reorganizes the cpu/<cpu>/* subdirectories in a
> similar manner than previous reorg scripts did. rtems-rc-19990202-0.diff
> contains the diffs after reorg-score-cpu.sh has been run on a
> rtems-19981215 snapshot + my patches up to rtems-rc-19990131-2.diff.
>
> This patch is rather nasty and may break something. However, I've tested
> it for about 10 different target/bsp pairs and believe to have shaken
> out most bugs.

I wonder about the following .h files that were not moved:

a29k/asm.h
a29k/cpu_asm.h
i386/asm.h
i960/asm.h
m68k/asm.h
m68k/m68302.h
m68k/m68360.h
m68k/qsm.h
m68k/sim.h
mips64orion/asm.h
mips64orion/cpu_asm.h
mips64orion/mips64orion.h
no_cpu/asm.h
no_cpu/cpu_asm.h
powerpc/asm.h
powerpc/mpc860.h
sh/asm.h
sparc/asm.h
sparc/erc32.h

6 files changed, 2 insertions, 2038 deletions

diff --git a/c/src/exec/score/cpu/mips64orion/Makefile.in b/c/src/exec/score/cpu/mips64orion/Makefile.in
index 16d0ba4f82..94424f094e 100644
--- a/c/src/exec/score/cpu/mips64orion/Makefile.in
+++ b/c/src/exec/score/cpu/mips64orion/Makefile.in
@@ -8,65 +8,7 @@ VPATH = @srcdir@
 RTEMS_ROOT = @top_srcdir@
 PROJECT_ROOT = @PROJECT_ROOT@
 
-RELS=$(ARCH)/rtems-cpu.rel
-
-# C source names, if any, go here -- minus the .c
-#  Normally cpu_asm and rtems are assembly files
-C_PIECES=cpu rtems
-C_FILES=$(C_PIECES:%=%.c)
-C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
-
-H_FILES=$(srcdir)/cpu.h $(srcdir)/mips64orion.h $(srcdir)/mipstypes.h \
-	$(srcdir)/idtcpu.h $(srcdir)/iregdef.h $(srcdir)/idtmon.h
-
-# H_FILES that get installed externally
-EXTERNAL_H_FILES = $(srcdir)/asm.h
-
-# Assembly source names, if any, go here -- minus the .s
-#  Normally cpu_asm and rtems are assembly files
-S_PIECES=cpu_asm
-S_FILES=$(S_PIECES:%=%.S)
-S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
-
-SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES) 
-OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
-
 include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
-include $(RTEMS_ROOT)/make/leaf.cfg
-
-#
-# (OPTIONAL) Add local stuff here using +=
-#
-
-DEFINES  +=
-CPPFLAGS +=
-CFLAGS   += $(CFLAGS_OS_V)
-
-LD_PATHS  +=
-LD_LIBS   +=
-LDFLAGS   +=
-
-#
-# Add your list of files to delete here.  The config files
-#  already know how to delete some stuff, so you may want
-#  to just run 'make clean' first to see what gets missed.
-#  'make clobber' already includes 'make clean'
-#
-
-CLEAN_ADDITIONS +=
-CLOBBER_ADDITIONS +=
-
-all:	${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
-	$(INSTALL_VARIANT) -m 444 $(RELS) ${PROJECT_RELEASE}/lib
-
-$(ARCH)/rtems-cpu.rel: $(OBJS)
-	$(make-rel)
-
-# Install the program(s), appending _g or _p as appropriate.
-# for include files, just use $(INSTALL)
-
-preinstall: $(ARCH)
-	$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
-# we will share the basic cpu file
-	$(INSTALL) -m 444 ${EXTERNAL_H_FILES} $(PROJECT_INCLUDE)
+include $(RTEMS_ROOT)/make/directory.cfg
 
+SUB_DIRS = rtems wrap
diff --git a/c/src/exec/score/cpu/mips64orion/cpu.h b/c/src/exec/score/cpu/mips64orion/cpu.h
deleted file mode 100644
index 0dfa3b0e98..0000000000
--- a/c/src/exec/score/cpu/mips64orion/cpu.h
+++ /dev/null
@@ -1,969 +0,0 @@
-/*  cpu.h
- *
- *  This include file contains information pertaining to the IDT 4650
- *  processor.
- *
- *  Author:     Craig Lebakken <craigl@transition.com>
- *
- *  COPYRIGHT (c) 1996 by Transition Networks Inc.
- *
- *  To anyone who acknowledges that this file is provided "AS IS"
- *  without any express or implied warranty:
- *      permission to use, copy, modify, and distribute this file
- *      for any purpose is hereby granted without fee, provided that
- *      the above copyright notice and this notice appears in all
- *      copies, and that the name of Transition Networks not be used in
- *      advertising or publicity pertaining to distribution of the
- *      software without specific, written prior permission.
- *      Transition Networks makes no representations about the suitability
- *      of this software for any purpose.
- *
- *  Derived from c/src/exec/score/cpu/no_cpu/cpu.h:
- *
- *  COPYRIGHT (c) 1989-1998.
- *  On-Line Applications Research Corporation (OAR).
- *  Copyright assigned to U.S. Government, 1994.
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.OARcorp.com/rtems/license.html.
- *
- *  $Id$
- */
-/* @(#)cpu.h       08/29/96     1.7 */
-
-#ifndef __CPU_h
-#define __CPU_h
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtems/score/mips64orion.h>       /* pick up machine definitions */
-#ifndef ASM
-#include <rtems/score/mipstypes.h>
-#endif
-
-extern int mips_disable_interrupts( void );
-extern void mips_enable_interrupts( int _level );
-extern int mips_disable_global_interrupts( void );
-extern void mips_enable_global_interrupts( void );
-extern void mips_fatal_error ( int error );
-
-/* conditional compilation parameters */
-
-/*
- *  Should the calls to _Thread_Enable_dispatch be inlined?
- *
- *  If TRUE, then they are inlined.
- *  If FALSE, then a subroutine call is made.
- *
- *  Basically this is an example of the classic trade-off of size
- *  versus speed.  Inlining the call (TRUE) typically increases the
- *  size of RTEMS while speeding up the enabling of dispatching.
- *  [NOTE: In general, the _Thread_Dispatch_disable_level will
- *  only be 0 or 1 unless you are in an interrupt handler and that
- *  interrupt handler invokes the executive.]  When not inlined
- *  something calls _Thread_Enable_dispatch which in turns calls
- *  _Thread_Dispatch.  If the enable dispatch is inlined, then
- *  one subroutine call is avoided entirely.]
- */
-
-#define CPU_INLINE_ENABLE_DISPATCH       TRUE
-
-/*
- *  Should the body of the search loops in _Thread_queue_Enqueue_priority
- *  be unrolled one time?  In unrolled each iteration of the loop examines
- *  two "nodes" on the chain being searched.  Otherwise, only one node
- *  is examined per iteration.
- *
- *  If TRUE, then the loops are unrolled.
- *  If FALSE, then the loops are not unrolled.
- *
- *  The primary factor in making this decision is the cost of disabling
- *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
- *  body of the loop.  On some CPUs, the flash is more expensive than
- *  one iteration of the loop body.  In this case, it might be desirable
- *  to unroll the loop.  It is important to note that on some CPUs, this
- *  code is the longest interrupt disable period in RTEMS.  So it is
- *  necessary to strike a balance when setting this parameter.
- */
-
-#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
-
-/*
- *  Does RTEMS manage a dedicated interrupt stack in software?
- *
- *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
- *  If FALSE, nothing is done.
- *
- *  If the CPU supports a dedicated interrupt stack in hardware,
- *  then it is generally the responsibility of the BSP to allocate it
- *  and set it up.
- *
- *  If the CPU does not support a dedicated interrupt stack, then
- *  the porter has two options: (1) execute interrupts on the
- *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
- *  interrupt stack.
- *
- *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
- *
- *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
- */
-
-#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
-
-/*
- *  Does this CPU have hardware support for a dedicated interrupt stack?
- *
- *  If TRUE, then it must be installed during initialization.
- *  If FALSE, then no installation is performed.
- *
- *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
- *
- *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
- */
-
-#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
-
-/*
- *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
- *
- *  If TRUE, then the memory is allocated during initialization.
- *  If FALSE, then the memory is allocated during initialization.
- *
- *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
- *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
- */
-
-#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
-
-/*
- *  Does the RTEMS invoke the user's ISR with the vector number and
- *  a pointer to the saved interrupt frame (1) or just the vector 
- *  number (0)?
- */
-
-#define CPU_ISR_PASSES_FRAME_POINTER 0
-
-/*
- *  Does the CPU have hardware floating point?
- *
- *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
- *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
- *
- *  If there is a FP coprocessor such as the i387 or mc68881, then
- *  the answer is TRUE.
- *
- *  The macro name "MIPS64ORION_HAS_FPU" should be made CPU specific.
- *  It indicates whether or not this CPU model has FP support.  For
- *  example, it would be possible to have an i386_nofp CPU model
- *  which set this to false to indicate that you have an i386 without
- *  an i387 and wish to leave floating point support out of RTEMS.
- */
-
-#if ( MIPS64ORION_HAS_FPU == 1 )
-#define CPU_HARDWARE_FP     TRUE
-#else
-#define CPU_HARDWARE_FP     FALSE
-#endif
-
-/*
- *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
- *
- *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
- *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
- *
- *  So far, the only CPU in which this option has been used is the
- *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
- *  floating point registers to perform integer multiplies.  If
- *  a function which you would not think utilize the FP unit DOES,
- *  then one can not easily predict which tasks will use the FP hardware.
- *  In this case, this option should be TRUE.
- *
- *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
- */
-
-#define CPU_ALL_TASKS_ARE_FP    FALSE
-
-/*
- *  Should the IDLE task have a floating point context?
- *
- *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
- *  and it has a floating point context which is switched in and out.
- *  If FALSE, then the IDLE task does not have a floating point context.
- *
- *  Setting this to TRUE negatively impacts the time required to preempt
- *  the IDLE task from an interrupt because the floating point context
- *  must be saved as part of the preemption.
- */
-
-#define CPU_IDLE_TASK_IS_FP      FALSE
-
-/*
- *  Should the saving of the floating point registers be deferred
- *  until a context switch is made to another different floating point
- *  task?
- *
- *  If TRUE, then the floating point context will not be stored until
- *  necessary.  It will remain in the floating point registers and not
- *  disturned until another floating point task is switched to.
- *
- *  If FALSE, then the floating point context is saved when a floating
- *  point task is switched out and restored when the next floating point
- *  task is restored.  The state of the floating point registers between
- *  those two operations is not specified.
- *
- *  If the floating point context does NOT have to be saved as part of
- *  interrupt dispatching, then it should be safe to set this to TRUE.
- *
- *  Setting this flag to TRUE results in using a different algorithm
- *  for deciding when to save and restore the floating point context.
- *  The deferred FP switch algorithm minimizes the number of times
- *  the FP context is saved and restored.  The FP context is not saved
- *  until a context switch is made to another, different FP task.
- *  Thus in a system with only one FP task, the FP context will never
- *  be saved or restored.
- */
-
-#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
-
-/*
- *  Does this port provide a CPU dependent IDLE task implementation?
- *
- *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
- *  must be provided and is the default IDLE thread body instead of
- *  _Internal_threads_Idle_thread_body.
- *
- *  If FALSE, then use the generic IDLE thread body if the BSP does
- *  not provide one.
- *
- *  This is intended to allow for supporting processors which have
- *  a low power or idle mode.  When the IDLE thread is executed, then
- *  the CPU can be powered down.
- *
- *  The order of precedence for selecting the IDLE thread body is:
- *
- *    1.  BSP provided
- *    2.  CPU dependent (if provided)
- *    3.  generic (if no BSP and no CPU dependent)
- */
-
-/* we can use the low power wait instruction for the IDLE thread */
-#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE 
-
-/*
- *  Does the stack grow up (toward higher addresses) or down
- *  (toward lower addresses)?
- *
- *  If TRUE, then the grows upward.
- *  If FALSE, then the grows toward smaller addresses.
- */
-
-/* our stack grows down */
-#define CPU_STACK_GROWS_UP               FALSE
-
-/*
- *  The following is the variable attribute used to force alignment
- *  of critical RTEMS structures.  On some processors it may make
- *  sense to have these aligned on tighter boundaries than
- *  the minimum requirements of the compiler in order to have as
- *  much of the critical data area as possible in a cache line.
- *
- *  The placement of this macro in the declaration of the variables
- *  is based on the syntactically requirements of the GNU C
- *  "__attribute__" extension.  For example with GNU C, use
- *  the following to force a structures to a 32 byte boundary.
- *
- *      __attribute__ ((aligned (32)))
- *
- *  NOTE:  Currently only the Priority Bit Map table uses this feature.
- *         To benefit from using this, the data must be heavily
- *         used so it will stay in the cache and used frequently enough
- *         in the executive to justify turning this on.
- */
-
-/* our cache line size is 16 bytes */
-#if __GNUC__
-#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
-#else
-#define CPU_STRUCTURE_ALIGNMENT 
-#endif
-
-/*
- *  Define what is required to specify how the network to host conversion
- *  routines are handled.
- */
-
-#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
-#define CPU_BIG_ENDIAN                           TRUE
-#define CPU_LITTLE_ENDIAN                        FALSE
-
-/*
- *  The following defines the number of bits actually used in the
- *  interrupt field of the task mode.  How those bits map to the
- *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
- */
-
-#define CPU_MODES_INTERRUPT_MASK   0x00000001
-
-/*
- *  Processor defined structures
- *
- *  Examples structures include the descriptor tables from the i386
- *  and the processor control structure on the i960ca.
- */
-
-/* may need to put some structures here.  */
-
-/*
- * Contexts
- *
- *  Generally there are 2 types of context to save.
- *     1. Interrupt registers to save
- *     2. Task level registers to save
- *
- *  This means we have the following 3 context items:
- *     1. task level context stuff::  Context_Control
- *     2. floating point task stuff:: Context_Control_fp
- *     3. special interrupt level context :: Context_Control_interrupt
- *
- *  On some processors, it is cost-effective to save only the callee
- *  preserved registers during a task context switch.  This means
- *  that the ISR code needs to save those registers which do not
- *  persist across function calls.  It is not mandatory to make this
- *  distinctions between the caller/callee saves registers for the
- *  purpose of minimizing context saved during task switch and on interrupts.
- *  If the cost of saving extra registers is minimal, simplicity is the
- *  choice.  Save the same context on interrupt entry as for tasks in
- *  this case.
- *
- *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
- *  care should be used in designing the context area.
- *
- *  On some CPUs with hardware floating point support, the Context_Control_fp
- *  structure will not be used or it simply consist of an array of a
- *  fixed number of bytes.   This is done when the floating point context
- *  is dumped by a "FP save context" type instruction and the format
- *  is not really defined by the CPU.  In this case, there is no need
- *  to figure out the exact format -- only the size.  Of course, although
- *  this is enough information for RTEMS, it is probably not enough for
- *  a debugger such as gdb.  But that is another problem.
- */
-
-/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
-typedef struct {
-    unsigned64 s0;
-    unsigned64 s1;
-    unsigned64 s2;
-    unsigned64 s3;
-    unsigned64 s4;
-    unsigned64 s5;
-    unsigned64 s6;
-    unsigned64 s7;
-    unsigned64 sp;
-    unsigned64 fp;
-    unsigned64 ra;
-    unsigned64 c0_sr;
-    unsigned64 c0_epc;
-} Context_Control;
-
-/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
-typedef struct {
-    unsigned32      fp0;
-    unsigned32      fp1;
-    unsigned32      fp2;
-    unsigned32      fp3;
-    unsigned32      fp4;
-    unsigned32      fp5;
-    unsigned32      fp6;
-    unsigned32      fp7;
-    unsigned32      fp8;
-    unsigned32      fp9;
-    unsigned32      fp10;
-    unsigned32      fp11;
-    unsigned32      fp12;
-    unsigned32      fp13;
-    unsigned32      fp14;
-    unsigned32      fp15;
-    unsigned32      fp16;
-    unsigned32      fp17;
-    unsigned32      fp18;
-    unsigned32      fp19;
-    unsigned32      fp20;
-    unsigned32      fp21;
-    unsigned32      fp22;
-    unsigned32      fp23;
-    unsigned32      fp24;
-    unsigned32      fp25;
-    unsigned32      fp26;
-    unsigned32      fp27;
-    unsigned32      fp28;
-    unsigned32      fp29;
-    unsigned32      fp30;
-    unsigned32      fp31;
-} Context_Control_fp;
-
-typedef struct {
-    unsigned32 special_interrupt_register;
-} CPU_Interrupt_frame;
-
-
-/*
- *  The following table contains the information required to configure
- *  the mips processor specific parameters.
- */
-
-typedef struct {
-  void       (*pretasking_hook)( void );
-  void       (*predriver_hook)( void );
-  void       (*postdriver_hook)( void );
-  void       (*idle_task)( void );
-  boolean      do_zero_of_workspace;
-  unsigned32   idle_task_stack_size;
-  unsigned32   interrupt_stack_size;
-  unsigned32   extra_mpci_receive_server_stack;
-  void *     (*stack_allocate_hook)( unsigned32 );
-  void       (*stack_free_hook)( void* );
-  /* end of fields required on all CPUs */
-
-  unsigned32   some_other_cpu_dependent_info;
-}   rtems_cpu_table;
-
-/*
- *  This variable is optional.  It is used on CPUs on which it is difficult
- *  to generate an "uninitialized" FP context.  It is filled in by
- *  _CPU_Initialize and copied into the task's FP context area during
- *  _CPU_Context_Initialize.
- */
-
-SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
-
-/*
- *  On some CPUs, RTEMS supports a software managed interrupt stack.
- *  This stack is allocated by the Interrupt Manager and the switch
- *  is performed in _ISR_Handler.  These variables contain pointers
- *  to the lowest and highest addresses in the chunk of memory allocated
- *  for the interrupt stack.  Since it is unknown whether the stack
- *  grows up or down (in general), this give the CPU dependent
- *  code the option of picking the version it wants to use.
- *
- *  NOTE: These two variables are required if the macro
- *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
- */
-
-SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
-SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
-
-/*
- *  With some compilation systems, it is difficult if not impossible to
- *  call a high-level language routine from assembly language.  This
- *  is especially true of commercial Ada compilers and name mangling
- *  C++ ones.  This variable can be optionally defined by the CPU porter
- *  and contains the address of the routine _Thread_Dispatch.  This
- *  can make it easier to invoke that routine at the end of the interrupt
- *  sequence (if a dispatch is necessary).
- */
-
-SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
-
-/*
- *  Nothing prevents the porter from declaring more CPU specific variables.
- */
-
-/* XXX: if needed, put more variables here */
-
-/*
- *  The size of the floating point context area.  On some CPUs this
- *  will not be a "sizeof" because the format of the floating point
- *  area is not defined -- only the size is.  This is usually on
- *  CPUs with a "floating point save context" instruction.
- */
-
-#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
-
-/*
- *  Amount of extra stack (above minimum stack size) required by
- *  system initialization thread.  Remember that in a multiprocessor
- *  system the system intialization thread becomes the MP server thread.
- */
-
-#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
-
-/*
- *  This defines the number of entries in the ISR_Vector_table managed
- *  by RTEMS.
- */
-
-#define CPU_INTERRUPT_NUMBER_OF_VECTORS      8
-#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
-
-/*
- *  Should be large enough to run all RTEMS tests.  This insures
- *  that a "reasonable" small application should not have any problems.
- */
-
-#define CPU_STACK_MINIMUM_SIZE          (2048*sizeof(unsigned32))
-
-/*
- *  CPU's worst alignment requirement for data types on a byte boundary.  This
- *  alignment does not take into account the requirements for the stack.
- */
-
-#define CPU_ALIGNMENT              8
-
-/*
- *  This number corresponds to the byte alignment requirement for the
- *  heap handler.  This alignment requirement may be stricter than that
- *  for the data types alignment specified by CPU_ALIGNMENT.  It is
- *  common for the heap to follow the same alignment requirement as
- *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
- *  then this should be set to CPU_ALIGNMENT.
- *
- *  NOTE:  This does not have to be a power of 2.  It does have to
- *         be greater or equal to than CPU_ALIGNMENT.
- */
-
-#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
-
-/*
- *  This number corresponds to the byte alignment requirement for memory
- *  buffers allocated by the partition manager.  This alignment requirement
- *  may be stricter than that for the data types alignment specified by
- *  CPU_ALIGNMENT.  It is common for the partition to follow the same
- *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
- *  enough for the partition, then this should be set to CPU_ALIGNMENT.
- *
- *  NOTE:  This does not have to be a power of 2.  It does have to
- *         be greater or equal to than CPU_ALIGNMENT.
- */
-
-#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
-
-/*
- *  This number corresponds to the byte alignment requirement for the
- *  stack.  This alignment requirement may be stricter than that for the
- *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
- *  is strict enough for the stack, then this should be set to 0.
- *
- *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
- */
-
-#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
-
-/* ISR handler macros */
-
-/*
- *  Disable all interrupts for an RTEMS critical section.  The previous
- *  level is returned in _level.
- */
-
-#define _CPU_ISR_Disable( _int_level ) \
-  do{ \
-	_int_level = mips_disable_interrupts(); \
-  }while(0)
-
-/*
- *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- *  This indicates the end of an RTEMS critical section.  The parameter
- *  _level is not modified.
- */
-
-#define _CPU_ISR_Enable( _level )  \
-  do{ \
-	mips_enable_interrupts(_level); \
-  }while(0)
-
-/*
- *  This temporarily restores the interrupt to _level before immediately
- *  disabling them again.  This is used to divide long RTEMS critical
- *  sections into two or more parts.  The parameter _level is not
- * modified.
- */
-
-#define _CPU_ISR_Flash( _xlevel ) \
-  do{ \
-	int _scratch; \
-	_CPU_ISR_Enable( _xlevel ); \
-	_CPU_ISR_Disable( _scratch ); \
-  }while(0)
-
-/*
- *  Map interrupt level in task mode onto the hardware that the CPU
- *  actually provides.  Currently, interrupt levels which do not
- *  map onto the CPU in a generic fashion are undefined.  Someday,
- *  it would be nice if these were "mapped" by the application
- *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
- *  8 - 255 would be available for bsp/application specific meaning.
- *  This could be used to manage a programmable interrupt controller
- *  via the rtems_task_mode directive.
- */
-extern void _CPU_ISR_Set_level( unsigned32 _new_level );
-
-unsigned32 _CPU_ISR_Get_level( void );
-
-/* end of ISR handler macros */
-
-/* Context handler macros */
-
-/*
- *  Initialize the context to a state suitable for starting a
- *  task after a context restore operation.  Generally, this
- *  involves:
- *
- *     - setting a starting address
- *     - preparing the stack
- *     - preparing the stack and frame pointers
- *     - setting the proper interrupt level in the context
- *     - initializing the floating point context
- *
- *  This routine generally does not set any unnecessary register
- *  in the context.  The state of the "general data" registers is
- *  undefined at task start time.
- *
- *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
- *        point thread.  This is typically only used on CPUs where the
- *        FPU may be easily disabled by software such as on the SPARC
- *        where the PSR contains an enable FPU bit.
- */
-
-#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
-                                 _isr, _entry_point, _is_fp ) \
-  { \
- 	unsigned32 _stack_tmp = (unsigned32)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \
-  	_stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
-  	(_the_context)->sp = _stack_tmp; \
-  	(_the_context)->fp = _stack_tmp; \
-	(_the_context)->ra = (unsigned64)_entry_point; \
-	(_the_context)->c0_sr = 0; \
-  }
-
-/*
- *  This routine is responsible for somehow restarting the currently
- *  executing task.  If you are lucky, then all that is necessary
- *  is restoring the context.  Otherwise, there will need to be
- *  a special assembly routine which does something special in this
- *  case.  Context_Restore should work most of the time.  It will
- *  not work if restarting self conflicts with the stack frame
- *  assumptions of restoring a context.
- */
-
-#define _CPU_Context_Restart_self( _the_context ) \
-   _CPU_Context_restore( (_the_context) );
-
-/*
- *  The purpose of this macro is to allow the initial pointer into
- *  A floating point context area (used to save the floating point
- *  context) to be at an arbitrary place in the floating point
- *  context area.
- *
- *  This is necessary because some FP units are designed to have
- *  their context saved as a stack which grows into lower addresses.
- *  Other FP units can be saved by simply moving registers into offsets
- *  from the base of the context area.  Finally some FP units provide
- *  a "dump context" instruction which could fill in from high to low
- *  or low to high based on the whim of the CPU designers.
- */
-
-#define _CPU_Context_Fp_start( _base, _offset ) \
-   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
-
-/*
- *  This routine initializes the FP context area passed to it to.
- *  There are a few standard ways in which to initialize the
- *  floating point context.  The code included for this macro assumes
- *  that this is a CPU in which a "initial" FP context was saved into
- *  _CPU_Null_fp_context and it simply copies it to the destination
- *  context passed to it.
- *
- *  Other models include (1) not doing anything, and (2) putting
- *  a "null FP status word" in the correct place in the FP context.
- */
-
-#define _CPU_Context_Initialize_fp( _destination ) \
-  { \
-   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
-  }
-
-/* end of Context handler macros */
-
-/* Fatal Error manager macros */
-
-/*
- *  This routine copies _error into a known place -- typically a stack
- *  location or a register, optionally disables interrupts, and
- *  halts/stops the CPU.
- */
-
-#define _CPU_Fatal_halt( _error ) \
-  { \
-    mips_disable_global_interrupts(); \
-    mips_fatal_error(_error); \
-  }
-
-/* end of Fatal Error manager macros */
-
-/* Bitfield handler macros */
-
-/*
- *  This routine sets _output to the bit number of the first bit
- *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
- *  This type may be either 16 or 32 bits wide although only the 16
- *  least significant bits will be used.
- *
- *  There are a number of variables in using a "find first bit" type
- *  instruction.
- *
- *    (1) What happens when run on a value of zero?
- *    (2) Bits may be numbered from MSB to LSB or vice-versa.
- *    (3) The numbering may be zero or one based.
- *    (4) The "find first bit" instruction may search from MSB or LSB.
- *
- *  RTEMS guarantees that (1) will never happen so it is not a concern.
- *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
- *  _CPU_Priority_bits_index().  These three form a set of routines
- *  which must logically operate together.  Bits in the _value are
- *  set and cleared based on masks built by _CPU_Priority_mask().
- *  The basic major and minor values calculated by _Priority_Major()
- *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
- *  to properly range between the values returned by the "find first bit"
- *  instruction.  This makes it possible for _Priority_Get_highest() to
- *  calculate the major and directly index into the minor table.
- *  This mapping is necessary to ensure that 0 (a high priority major/minor)
- *  is the first bit found.
- *
- *  This entire "find first bit" and mapping process depends heavily
- *  on the manner in which a priority is broken into a major and minor
- *  components with the major being the 4 MSB of a priority and minor
- *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
- *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
- *  to the lowest priority.
- *
- *  If your CPU does not have a "find first bit" instruction, then
- *  there are ways to make do without it.  Here are a handful of ways
- *  to implement this in software:
- *
- *    - a series of 16 bit test instructions
- *    - a "binary search using if's"
- *    - _number = 0
- *      if _value > 0x00ff
- *        _value >>=8
- *        _number = 8;
- *
- *      if _value > 0x0000f
- *        _value >=8
- *        _number += 4
- *
- *      _number += bit_set_table[ _value ]
- *
- *    where bit_set_table[ 16 ] has values which indicate the first
- *      bit set
- */
-
-#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
-#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
-
-#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
-
-#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
-  { \
-    (_output) = 0;   /* do something to prevent warnings */ \
-  }
-
-#endif
-
-/* end of Bitfield handler macros */
-
-/*
- *  This routine builds the mask which corresponds to the bit fields
- *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
- *  for that routine.
- */
-
-#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
-
-#define _CPU_Priority_Mask( _bit_number ) \
-  ( 1 << (_bit_number) )
-
-#endif
-
-/*
- *  This routine translates the bit numbers returned by
- *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
- *  a major or minor component of a priority.  See the discussion
- *  for that routine.
- */
-
-#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
-
-#define _CPU_Priority_bits_index( _priority ) \
-  (_priority)
-
-#endif
-
-/* end of Priority handler macros */
-
-/* functions */
-
-/*
- *  _CPU_Initialize
- *
- *  This routine performs CPU dependent initialization.
- */
-
-void _CPU_Initialize(
-  rtems_cpu_table  *cpu_table,
-  void      (*thread_dispatch)
-);
-
-/*
- *  _CPU_ISR_install_raw_handler
- *
- *  This routine installs a "raw" interrupt handler directly into the 
- *  processor's vector table.
- */
- 
-void _CPU_ISR_install_raw_handler(
-  unsigned32  vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-);
-
-/*
- *  _CPU_ISR_install_vector
- *
- *  This routine installs an interrupt vector.
- */
-
-void _CPU_ISR_install_vector(
-  unsigned32  vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-);
-
-/*
- *  _CPU_Install_interrupt_stack
- *
- *  This routine installs the hardware interrupt stack pointer.
- *
- *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
- *         is TRUE.
- */
-
-void _CPU_Install_interrupt_stack( void );
-
-/*
- *  _CPU_Internal_threads_Idle_thread_body
- *
- *  This routine is the CPU dependent IDLE thread body.
- *
- *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
- *         is TRUE.
- */
-
-void _CPU_Thread_Idle_body( void );
-
-/*
- *  _CPU_Context_switch
- *
- *  This routine switches from the run context to the heir context.
- */
-
-void _CPU_Context_switch(
-  Context_Control  *run,
-  Context_Control  *heir
-);
-
-/*
- *  _CPU_Context_restore
- *
- *  This routine is generally used only to restart self in an
- *  efficient manner.  It may simply be a label in _CPU_Context_switch.
- *
- *  NOTE: May be unnecessary to reload some registers.
- */
-
-void _CPU_Context_restore(
-  Context_Control *new_context
-);
-
-/*
- *  _CPU_Context_save_fp
- *
- *  This routine saves the floating point context passed to it.
- */
-
-void _CPU_Context_save_fp(
-  void **fp_context_ptr
-);
-
-/*
- *  _CPU_Context_restore_fp
- *
- *  This routine restores the floating point context passed to it.
- */
-
-void _CPU_Context_restore_fp(
-  void **fp_context_ptr
-);
-
-/*  The following routine swaps the endian format of an unsigned int.
- *  It must be static because it is referenced indirectly.
- *
- *  This version will work on any processor, but if there is a better
- *  way for your CPU PLEASE use it.  The most common way to do this is to:
- *
- *     swap least significant two bytes with 16-bit rotate
- *     swap upper and lower 16-bits
- *     swap most significant two bytes with 16-bit rotate
- *
- *  Some CPUs have special instructions which swap a 32-bit quantity in
- *  a single instruction (e.g. i486).  It is probably best to avoid
- *  an "endian swapping control bit" in the CPU.  One good reason is
- *  that interrupts would probably have to be disabled to insure that
- *  an interrupt does not try to access the same "chunk" with the wrong
- *  endian.  Another good reason is that on some CPUs, the endian bit
- *  endianness for ALL fetches -- both code and data -- so the code
- *  will be fetched incorrectly.
- */
- 
-static inline unsigned int CPU_swap_u32(
-  unsigned int value
-)
-{
-  unsigned32 byte1, byte2, byte3, byte4, swapped;
- 
-  byte4 = (value >> 24) & 0xff;
-  byte3 = (value >> 16) & 0xff;
-  byte2 = (value >> 8)  & 0xff;
-  byte1 =  value        & 0xff;
- 
-  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
-  return( swapped );
-}
-
-#define CPU_swap_u16( value ) \
-  (((value&0xff) << 8) | ((value >> 8)&0xff))
-
-/*
- *  Miscellaneous prototypes 
- *
- *  NOTE:  The names should have mips64orion in them.
- */
-
-void disable_int( unsigned32 mask );
-void enable_int( unsigned32 mask );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/c/src/exec/score/cpu/mips64orion/idtcpu.h b/c/src/exec/score/cpu/mips64orion/idtcpu.h
deleted file mode 100644
index f921e85ef6..0000000000
--- a/c/src/exec/score/cpu/mips64orion/idtcpu.h
+++ /dev/null
@@ -1,440 +0,0 @@
-/*
-
-Based upon IDT provided code with the following release:
-
-This source code has been made available to you by IDT on an AS-IS
-basis. Anyone receiving this source is licensed under IDT copyrights
-to use it in any way he or she deems fit, including copying it,
-modifying it, compiling it, and redistributing it either with or
-without modifications.  No license under IDT patents or patent
-applications is to be implied by the copyright license.
-
-Any user of this software should understand that IDT cannot provide
-technical support for this software and will not be responsible for
-any consequences resulting from the use of this software.
-
-Any person who transfers this source code or any derivative work must
-include the IDT copyright notice, this paragraph, and the preceeding
-two paragraphs in the transferred software.
-
-COPYRIGHT IDT CORPORATION 1996
-LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
-
-  $Id$
-*/ 
-
-/*
-** idtcpu.h -- cpu related defines
-*/
-
-#ifndef _IDTCPU_H__
-#define _IDTCPU_H__
-
-/*
- * 950313: Ketan added Register definition for XContext reg.
- *               added define for WAIT instruction.
- * 950421: Ketan added Register definition for Config reg (R3081)
- */
-
-/*
-** memory configuration and mapping
-*/
-#define K0BASE	0x80000000
-#define K0SIZE	0x20000000
-#define K1BASE	0xa0000000
-#define K1SIZE	0x20000000
-#define K2BASE	0xc0000000
-#define K2SIZE	0x20000000
-#if defined(CPU_R4000)
-#define KSBASE	0xe0000000
-#define KSSIZE	0x20000000
-#endif
-
-#define KUBASE	0
-#define KUSIZE	0x80000000
-
-/*
-** Exception Vectors
-*/
-#if defined(CPU_R3000)
-#define	UT_VEC	K0BASE			/* utlbmiss vector */
-#define E_VEC	(K0BASE+0x80)		/* exception vevtor */
-#endif
-#if defined(CPU_R4000)
-#define	T_VEC	(K0BASE+0x000)		/* tlbmiss vector */
-#define X_VEC	(K0BASE+0x080)		/* xtlbmiss vector */
-#define C_VEC	(K0BASE+0x100)		/* cache error vector */
-#define E_VEC	(K0BASE+0x180)		/* exception vector */
-#endif
-#define	R_VEC	(K1BASE+0x1fc00000)	/* reset vector */
-
-/*
-** Address conversion macros
-*/
-#ifdef CLANGUAGE
-#define CAST(as) (as)
-#else
-#define CAST(as)
-#endif
-#define	K0_TO_K1(x)	(CAST(unsigned)(x)|0xA0000000)	/* kseg0 to kseg1 */
-#define	K1_TO_K0(x)	(CAST(unsigned)(x)&0x9FFFFFFF)	/* kseg1 to kseg0 */
-#define	K0_TO_PHYS(x)	(CAST(unsigned)(x)&0x1FFFFFFF)	/* kseg0 to physical */
-#define	K1_TO_PHYS(x)	(CAST(unsigned)(x)&0x1FFFFFFF)	/* kseg1 to physical */
-#define	PHYS_TO_K0(x)	(CAST(unsigned)(x)|0x80000000)	/* physical to kseg0 */
-#define	PHYS_TO_K1(x)	(CAST(unsigned)(x)|0xA0000000)	/* physical to kseg1 */
-
-/*
-**	Cache size constants
-*/
-#define	MINCACHE	0x200		/* 512       For 3041. */
-#define	MAXCACHE	0x40000		/* 256*1024   256k */	
-
-#if defined(CPU_R4000)
-/* R4000 configuration register definitions */
-#define CFG_CM		0x80000000	/* Master-Checker mode */
-#define CFG_ECMASK	0x70000000	/* System Clock Ratio */
-#define CFG_ECBY2	0x00000000 	/* divide by 2 */
-#define CFG_ECBY3	0x10000000 	/* divide by 3 */
-#define CFG_ECBY4	0x20000000 	/* divide by 4 */
-#define CFG_EPMASK	0x0f000000	/* Transmit data pattern */
-#define CFG_EPD		0x00000000	/* D */
-#define CFG_EPDDX	0x01000000	/* DDX */
-#define CFG_EPDDXX	0x02000000	/* DDXX */
-#define CFG_EPDXDX	0x03000000	/* DXDX */
-#define CFG_EPDDXXX	0x04000000	/* DDXXX */
-#define CFG_EPDDXXXX	0x05000000	/* DDXXXX */
-#define CFG_EPDXXDXX	0x06000000	/* DXXDXX */
-#define CFG_EPDDXXXXX	0x07000000	/* DDXXXXX */
-#define CFG_EPDXXXDXXX	0x08000000	/* DXXXDXXX */
-#define CFG_SBMASK	0x00c00000	/* Secondary cache block size */
-#define CFG_SBSHIFT	22
-#define CFG_SB4		0x00000000	/* 4 words */
-#define CFG_SB8		0x00400000	/* 8 words */
-#define CFG_SB16	0x00800000	/* 16 words */
-#define CFG_SB32	0x00c00000	/* 32 words */
-#define CFG_SS		0x00200000	/* Split secondary cache */
-#define CFG_SW		0x00100000	/* Secondary cache port width */
-#define CFG_EWMASK	0x000c0000	/* System port width */
-#define CFG_EWSHIFT	18
-#define CFG_EW64	0x00000000	/* 64 bit */
-#define CFG_EW32	0x00010000	/* 32 bit */
-#define CFG_SC		0x00020000	/* Secondary cache absent */
-#define CFG_SM		0x00010000	/* Dirty Shared mode disabled */
-#define CFG_BE		0x00008000	/* Big Endian */
-#define CFG_EM		0x00004000	/* ECC mode enable */
-#define CFG_EB		0x00002000	/* Block ordering */
-#define CFG_ICMASK	0x00000e00	/* Instruction cache size */
-#define CFG_ICSHIFT	9
-#define CFG_DCMASK	0x000001c0	/* Data cache size */
-#define CFG_DCSHIFT	6
-#define CFG_IB		0x00000020	/* Instruction cache block size */
-#define CFG_DB		0x00000010	/* Data cache block size */
-#define CFG_CU		0x00000008	/* Update on Store Conditional */
-#define CFG_K0MASK	0x00000007	/* KSEG0 coherency algorithm */
-
-/*
- * R4000 primary cache mode
- */
-#define CFG_C_UNCACHED		2
-#define CFG_C_NONCOHERENT	3
-#define CFG_C_COHERENTXCL	4
-#define CFG_C_COHERENTXCLW	5
-#define CFG_C_COHERENTUPD	6
-
-/*
- * R4000 cache operations (should be in assembler...?)
- */
-#define Index_Invalidate_I               0x0         /* 0       0 */
-#define Index_Writeback_Inv_D            0x1         /* 0       1 */
-#define Index_Invalidate_SI              0x2         /* 0       2 */
-#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
-#define Index_Load_Tag_I                 0x4         /* 1       0 */
-#define Index_Load_Tag_D                 0x5         /* 1       1 */
-#define Index_Load_Tag_SI                0x6         /* 1       2 */
-#define Index_Load_Tag_SD                0x7         /* 1       3 */
-#define Index_Store_Tag_I                0x8         /* 2       0 */
-#define Index_Store_Tag_D                0x9         /* 2       1 */
-#define Index_Store_Tag_SI               0xA         /* 2       2 */
-#define Index_Store_Tag_SD               0xB         /* 2       3 */
-#define Create_Dirty_Exc_D               0xD         /* 3       1 */
-#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
-#define Hit_Invalidate_I                 0x10        /* 4       0 */
-#define Hit_Invalidate_D                 0x11        /* 4       1 */
-#define Hit_Invalidate_SI                0x12        /* 4       2 */
-#define Hit_Invalidate_SD                0x13        /* 4       3 */
-#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
-#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
-#define Fill_I                           0x14        /* 5       0 */
-#define Hit_Writeback_D                  0x19        /* 6       1 */
-#define Hit_Writeback_SD                 0x1B        /* 6       3 */
-#define Hit_Writeback_I                  0x18        /* 6       0 */
-#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
-#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
-
-#ifndef WAIT
-#define WAIT .word 0x42000020
-#endif WAIT
-
-#ifndef wait 
-#define wait .word 0x42000020
-#endif wait
-
-#endif
-
-/*
-** TLB resource defines
-*/
-#if defined(CPU_R3000)
-#define	N_TLB_ENTRIES	64
-#define TLB_PGSIZE	0x1000
-#define RANDBASE	8
-#define	TLBLO_PFNMASK	0xfffff000
-#define	TLBLO_PFNSHIFT	12
-#define	TLBLO_N		0x800	/* non-cacheable */
-#define	TLBLO_D		0x400	/* writeable */
-#define	TLBLO_V		0x200	/* valid bit */
-#define	TLBLO_G		0x100	/* global access bit */
-
-#define	TLBHI_VPNMASK	0xfffff000
-#define	TLBHI_VPNSHIFT	12
-#define	TLBHI_PIDMASK	0xfc0
-#define	TLBHI_PIDSHIFT	6
-#define	TLBHI_NPID	64
-
-#define	TLBINX_PROBE	0x80000000
-#define	TLBINX_INXMASK	0x00003f00
-#define	TLBINX_INXSHIFT	8
-
-#define	TLBRAND_RANDMASK	0x00003f00
-#define	TLBRAND_RANDSHIFT	8
-
-#define	TLBCTXT_BASEMASK	0xffe00000
-#define	TLBCTXT_BASESHIFT	21
-
-#define	TLBCTXT_VPNMASK		0x001ffffc
-#define	TLBCTXT_VPNSHIFT	2
-#endif
-#if defined(CPU_R4000)
-#define	N_TLB_ENTRIES	48
-
-#define	TLBHI_VPN2MASK	0xffffe000
-#define	TLBHI_PIDMASK	0x000000ff
-#define	TLBHI_NPID	256
-
-#define	TLBLO_PFNMASK	0x3fffffc0
-#define TLBLO_PFNSHIFT	6
-#define	TLBLO_D		0x00000004	/* writeable */
-#define	TLBLO_V		0x00000002	/* valid bit */
-#define	TLBLO_G		0x00000001	/* global access bit */
-#define TLBLO_CMASK	0x00000038	/* cache algorithm mask */
-#define TLBLO_CSHIFT	3
-
-#define TLBLO_UNCACHED		(CFG_C_UNCACHED<<TLBLO_CSHIFT)
-#define TLBLO_NONCOHERENT	(CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
-#define TLBLO_COHERENTXCL	(CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
-#define TLBLO_COHERENTXCLW	(CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
-#define TLBLO_COHERENTUPD	(CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
-
-#define	TLBINX_PROBE	0x80000000
-#define	TLBINX_INXMASK	0x0000003f
-
-#define	TLBRAND_RANDMASK	0x0000003f
-
-#define	TLBCTXT_BASEMASK	0xff800000
-#define	TLBCTXT_BASESHIFT	23
-
-#define	TLBCTXT_VPN2MASK	0x007ffff0
-#define	TLBCTXT_VPN2SHIFT	4
-
-#define TLBPGMASK_MASK		0x01ffe000
-#endif
-
-#if defined(CPU_R3000)
-#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
-#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
-#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
-#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
-#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
-
-#define	SR_BEV		0x00400000	/* use boot exception vectors */
-
-/* Cache control bits */
-#define	SR_TS		0x00200000	/* TLB shutdown */
-#define	SR_PE		0x00100000	/* cache parity error */
-#define	SR_CM		0x00080000	/* cache miss */
-#define	SR_PZ		0x00040000	/* cache parity zero */
-#define	SR_SWC		0x00020000	/* swap cache */
-#define	SR_ISC		0x00010000	/* Isolate data cache */
-
-/*
-**	status register interrupt masks and bits
-*/
-
-#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
-#define	SR_IMASK8	0x00000000	/* mask level 8 */
-#define	SR_IMASK7	0x00008000	/* mask level 7 */
-#define	SR_IMASK6	0x0000c000	/* mask level 6 */
-#define	SR_IMASK5	0x0000e000	/* mask level 5 */
-#define	SR_IMASK4	0x0000f000	/* mask level 4 */
-#define	SR_IMASK3	0x0000f800	/* mask level 3 */
-#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
-#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
-#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
-
-#define	SR_IMASKSHIFT	8
-
-#define	SR_IBIT8	0x00008000	/* bit level 8 */
-#define	SR_IBIT7	0x00004000	/* bit level 7 */
-#define	SR_IBIT6	0x00002000	/* bit level 6 */
-#define	SR_IBIT5	0x00001000	/* bit level 5 */
-#define	SR_IBIT4	0x00000800	/* bit level 4 */
-#define	SR_IBIT3	0x00000400	/* bit level 3 */
-#define	SR_IBIT2	0x00000200	/* bit level 2 */
-#define	SR_IBIT1	0x00000100	/* bit level 1 */
-
-#define	SR_KUO		0x00000020	/* old kernel/user, 0 => k, 1 => u */
-#define	SR_IEO		0x00000010	/* old interrupt enable, 1 => enable */
-#define	SR_KUP		0x00000008	/* prev kernel/user, 0 => k, 1 => u */
-#define	SR_IEP		0x00000004	/* prev interrupt enable, 1 => enable */
-#define	SR_KUC		0x00000002	/* cur kernel/user, 0 => k, 1 => u */
-#define	SR_IEC		0x00000001	/* cur interrupt enable, 1 => enable */
-#endif
-
-#if defined(CPU_R4000)
-#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
-#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
-#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
-#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
-#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
-
-#define SR_RP		0x08000000      /* Reduced power operation */
-#define SR_FR		0x04000000	/* Additional floating point registers */
-#define SR_RE		0x02000000	/* Reverse endian in user mode */
-
-#define SR_BEV		0x00400000	/* Use boot exception vectors */
-#define SR_TS		0x00200000	/* TLB shutdown */
-#define SR_SR		0x00100000	/* Soft reset */
-#define SR_CH		0x00040000	/* Cache hit */
-#define SR_CE		0x00020000	/* Use cache ECC  */
-#define SR_DE		0x00010000	/* Disable cache exceptions */
-
-/*
-**	status register interrupt masks and bits
-*/
-
-#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
-#define	SR_IMASK8	0x00000000	/* mask level 8 */
-#define	SR_IMASK7	0x00008000	/* mask level 7 */
-#define	SR_IMASK6	0x0000c000	/* mask level 6 */
-#define	SR_IMASK5	0x0000e000	/* mask level 5 */
-#define	SR_IMASK4	0x0000f000	/* mask level 4 */
-#define	SR_IMASK3	0x0000f800	/* mask level 3 */
-#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
-#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
-#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
-
-#define	SR_IMASKSHIFT	8
-
-#define	SR_IBIT8	0x00008000	/* bit level 8 */
-#define	SR_IBIT7	0x00004000	/* bit level 7 */
-#define	SR_IBIT6	0x00002000	/* bit level 6 */
-#define	SR_IBIT5	0x00001000	/* bit level 5 */
-#define	SR_IBIT4	0x00000800	/* bit level 4 */
-#define	SR_IBIT3	0x00000400	/* bit level 3 */
-#define	SR_IBIT2	0x00000200	/* bit level 2 */
-#define	SR_IBIT1	0x00000100	/* bit level 1 */
-
-#define SR_KSMASK	0x00000018	/* Kernel mode mask */
-#define SR_KSUSER	0x00000010	/* User mode */
-#define SR_KSSUPER	0x00000008	/* Supervisor mode */
-#define SR_KSKERNEL	0x00000000	/* Kernel mode */
-#define SR_ERL		0x00000004	/* Error level */
-#define SR_EXL		0x00000002	/* Exception level */
-#define SR_IE		0x00000001	/* Interrupts enabled */
-#endif
-
-
-
-/*
- * Cause Register
- */
-#define	CAUSE_BD	0x80000000	/* Branch delay slot */
-#define	CAUSE_CEMASK	0x30000000	/* coprocessor error */
-#define	CAUSE_CESHIFT	28
-
-
-#define	CAUSE_IPMASK	0x0000FF00	/* Pending interrupt mask */
-#define	CAUSE_IPSHIFT	8
-
-#define	CAUSE_EXCMASK	0x0000003C	/* Cause code bits */
-#define	CAUSE_EXCSHIFT	2
-
-#ifndef XDS
-/*
-**  Coprocessor 0 registers
-*/
-#define	C0_INX		$0		/* tlb index */
-#define	C0_RAND		$1		/* tlb random */
-#if defined(CPU_R3000)
-#define	C0_TLBLO	$2		/* tlb entry low */
-#endif
-#if defined(CPU_R4000)
-#define	C0_TLBLO0	$2		/* tlb entry low 0 */
-#define	C0_TLBLO1	$3		/* tlb entry low 1 */
-#endif
-
-#define	C0_CTXT		$4		/* tlb context */
-
-#if defined(CPU_R4000)
-#define C0_PAGEMASK	$5		/* tlb page mask */
-#define C0_WIRED	$6		/* number of wired tlb entries */
-#endif
-
-#define	C0_BADVADDR	$8		/* bad virtual address */
-
-#if defined(CPU_R4000)
-#define C0_COUNT	$9		/* cycle count */
-#endif
-
-#define	C0_TLBHI	$10		/* tlb entry hi */
-
-#if defined(CPU_R4000)
-#define C0_COMPARE	$11		/* cyccle count comparator  */
-#endif
-
-#define	C0_SR		$12		/* status register */
-#define	C0_CAUSE	$13		/* exception cause */
-#define	C0_EPC		$14		/* exception pc */
-#define	C0_PRID		$15		/* revision identifier */
-
-#if defined(CPU_R3000)
-#define C0_CONFIG   $3     /* configuration register R3081*/
-#endif
-
-#if defined(CPU_R4000)
-#define C0_CONFIG	$16		/* configuration register */
-#define C0_LLADDR	$17		/* linked load address */
-#define C0_WATCHLO	$18		/* watchpoint trap register */
-#define C0_WATCHHI	$19		/* watchpoint trap register */
-#define C0_XCTXT    $20     /* extended tlb context */
-#define C0_ECC		$26		/* secondary cache ECC control */
-#define C0_CACHEERR	$27		/* cache error status */
-#define C0_TAGLO	$28		/* cache tag lo */
-#define C0_TAGHI	$29		/* cache tag hi */
-#define C0_ERRPC	$30		/* cache error pc */
-#endif
-
-#endif XDS
-
-#ifdef R4650
-#define IWATCH $18
-#define DWATCH $19
-#define IBASE  $0
-#define IBOUND $1
-#define DBASE  $2
-#define DBOUND $3
-#define CALG	$17
-#endif
-
-#endif /* _IDTCPU_H__ */
-
diff --git a/c/src/exec/score/cpu/mips64orion/idtmon.h b/c/src/exec/score/cpu/mips64orion/idtmon.h
deleted file mode 100644
index 2dacfe052e..0000000000
--- a/c/src/exec/score/cpu/mips64orion/idtmon.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
-
-Based upon IDT provided code with the following release:
-
-This source code has been made available to you by IDT on an AS-IS
-basis. Anyone receiving this source is licensed under IDT copyrights
-to use it in any way he or she deems fit, including copying it,
-modifying it, compiling it, and redistributing it either with or
-without modifications.  No license under IDT patents or patent
-applications is to be implied by the copyright license.
-
-Any user of this software should understand that IDT cannot provide
-technical support for this software and will not be responsible for
-any consequences resulting from the use of this software.
-
-Any person who transfers this source code or any derivative work must
-include the IDT copyright notice, this paragraph, and the preceeding
-two paragraphs in the transferred software.
-
-COPYRIGHT IDT CORPORATION 1996
-LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
-
-  $Id$
-*/ 
-
-/*
-**	idtmon.h - General header file for the IDT Prom Monitor
-**
-**	Copyright 1989  Integrated Device Technology, Inc.
-**	All Rights Reserved.
-**
-**	June 1989 - D.Cahoon
-*/
-#ifndef __IDTMON_H__
-#define __IDTMON_H__
-
-/*
-** P_STACKSIZE is the size of the Prom Stack. 
-** the prom stack grows downward 
-*/
-#define	P_STACKSIZE	0x2000   /* sets stack size to 8k */
-
-/*
-** M_BUSWIDTH
-** Memory bus width (including bank interleaving) in bytes
-** used when doing memory sizing to prevent bus capacitance
-** reporting ghost memory locations
-*/
-#if defined(CPU_R3000)
-#define M_BUSWIDTH	8	/* 32bit memory bank interleaved */
-#endif
-#if defined(CPU_R4000)
-#define M_BUSWIDTH	16	/* 64 bit memory bank interleaved */
-#endif
-
-/*
-** this is the default value for the number of bytes to add in calculating
-** the checksums in the checksum command
-*/
-#define CHK_SUM_CNT	0x20000	     /* number of bytes to calc chksum for */
-
-/*
-** Monitor modes
-*/
-#define	MODE_MONITOR	5	/* IDT Prom Monitor is executing */
-#define	MODE_USER	0xa	/* USER is executing */
-
-/*
-** memory reference widths
-*/
-#define	SW_BYTE		1
-#define	SW_HALFWORD	2
-#define	SW_WORD		4
-#define SW_TRIBYTEL	12
-#define SW_TRIBYTER	20
-
-#ifdef CPU_R4000
-/*
-** definitions for select_cache call
-*/
-#define DCACHE		0
-#define ICACHE		1
-#define SCACHE		2
-
-#endif
-
-#ifndef ASM
-typedef struct {
-	unsigned int	mem_size;
-	unsigned int	icache_size;
-	unsigned int	dcache_size;
-#ifdef CPU_R4000
-    unsigned int    scache_size;
-#endif
-
-	} mem_config;
-
-#endif
-
-/*
-** general equates for diagnostics and boolean functions
-*/
-#define	PASS			0
-#define	FAIL			1
-
-#ifndef	TRUE
-#define	TRUE			1
-#endif	TRUE
-#ifndef	NULL
-#define	NULL			0
-#endif	NULL
-
-#ifndef	FALSE
-#define	FALSE			0
-#endif	FALSE
-
-
-/*
-**	portablility equates
-*/
-
-#ifndef	BOOL
-#define BOOL	unsigned int
-#endif	BOOL
-
-#ifndef GLOBAL
-#define GLOBAL	/**/
-#endif  GLOBAL
-
-#ifndef MLOCAL
-#define MLOCAL	static
-#endif  MLOCAL
-
-
-#ifdef XDS
-#define CONST const
-#else
-#define CONST
-#endif XDS 
-
-#define u_char	unsigned char
-#define u_short unsigned short
-#define u_int	unsigned int
-/*
-** assembly instructions for compatability between xds and mips
-*/
-#ifndef XDS
-#define sllv sll
-#define srlv srl
-#endif XDS
-/*
-**	debugger macros for assembly language routines. Allows the 
-**	programmer to set up the necessary stack frame info
-**	required by debuggers to do stack traces.
-*/
-
-#ifndef XDS 
-#define	FRAME(name,frm_reg,offset,ret_reg)	\
-	.globl	name;				\
-	.ent	name;				\
-name:;						\
-	.frame	frm_reg,offset,ret_reg
-#define ENDFRAME(name) 				\
-	.end name
-#else
-#define	FRAME(name,frm_reg,offset,ret_reg)	\
-	.globl	_##name;\
-_##name:
-#define ENDFRAME(name)
-#endif  XDS
-#endif /* __IDTMON_H__ */
diff --git a/c/src/exec/score/cpu/mips64orion/iregdef.h b/c/src/exec/score/cpu/mips64orion/iregdef.h
deleted file mode 100644
index f0953da852..0000000000
--- a/c/src/exec/score/cpu/mips64orion/iregdef.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/*
-
-Based upon IDT provided code with the following release:
-
-This source code has been made available to you by IDT on an AS-IS
-basis. Anyone receiving this source is licensed under IDT copyrights
-to use it in any way he or she deems fit, including copying it,
-modifying it, compiling it, and redistributing it either with or
-without modifications.  No license under IDT patents or patent
-applications is to be implied by the copyright license.
-
-Any user of this software should understand that IDT cannot provide
-technical support for this software and will not be responsible for
-any consequences resulting from the use of this software.
-
-Any person who transfers this source code or any derivative work must
-include the IDT copyright notice, this paragraph, and the preceeding
-two paragraphs in the transferred software.
-
-COPYRIGHT IDT CORPORATION 1996
-LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
-
-  $Id$
-*/ 
-
-/*
-**	iregdef.h - IDT R3000 register structure header file
-**
-**	Copyright 1989 Integrated Device Technology, Inc
-**	All Rights Reserved
-**
-*/
-#ifndef __IREGDEF_H__
-#define __IREGDEF_H__
-
-/*
- * 950313: Ketan added sreg/lreg and R_SZ for 64-bit saves
- *         added Register definition for XContext reg.
- *         Look towards end of this file.
- */
-/*
-** register names 
-*/
-#define r0	$0
-#define r1	$1
-#define r2	$2
-#define r3	$3
-#define r4	$4
-#define r5	$5
-#define r6	$6
-#define r7	$7
-#define r8	$8
-#define r9	$9
-#define r10	$10
-#define r11	$11
-#define r12	$12
-#define r13	$13
-
-#define r14	$14
-#define r15	$15
-#define r16	$16
-#define r17	$17
-#define r18	$18
-#define r19	$19
-#define r20	$20
-#define r21	$21
-#define r22	$22
-#define r23	$23
-#define r24	$24
-#define r25	$25
-#define r26	$26
-#define r27	$27
-#define r28	$28
-#define r29	$29
-#define r30	$30
-#define r31	$31
-
-#define fp0	$f0
-#define fp1	$f1
-#define fp2	$f2
-#define fp3	$f3
-#define fp4	$f4
-#define fp5	$f5
-#define fp6	$f6
-#define fp7	$f7
-#define fp8	$f8
-#define fp9	$f9
-#define fp10	$f10
-#define fp11	$f11
-#define fp12	$f12
-#define fp13	$f13
-#define fp14	$f14
-#define fp15	$f15
-#define fp16	$f16
-#define fp17	$f17
-#define fp18	$f18
-#define fp19	$f19
-#define fp20	$f20
-#define fp21	$f21
-#define fp22	$f22
-#define fp23	$f23
-#define fp24	$f24
-#define fp25	$f25
-#define fp26	$f26
-#define fp27	$f27
-#define fp28	$f28
-#define fp29	$f29
-#define fp30	$f30
-#define fp31	$f31
-
-#define fcr0	$0
-#define fcr30	$30
-#define fcr31	$31
-
-#define zero	$0	/* wired zero */
-#define AT	$at	/* assembler temp */
-#define v0	$2	/* return value */
-#define v1	$3
-#define a0	$4	/* argument registers a0-a3 */
-#define a1	$5
-#define a2	$6
-#define a3	$7
-#define t0	$8	/* caller saved  t0-t9 */
-#define t1	$9
-#define t2	$10
-#define t3	$11
-#define t4	$12
-#define t5	$13
-#define t6	$14
-#define t7	$15
-#define s0	$16	/* callee saved s0-s8 */
-#define s1	$17
-#define s2	$18
-#define s3	$19
-#define s4	$20
-#define s5	$21
-#define s6	$22
-#define s7	$23
-#define t8	$24
-#define t9	$25
-#define k0	$26	/* kernel usage */
-#define k1	$27	/* kernel usage */
-#define gp	$28	/* sdata pointer */
-#define sp	$29	/* stack pointer */
-#define s8	$30	/* yet another saved reg for the callee */
-#define fp	$30	/* frame pointer - this is being phased out by MIPS */
-#define ra	$31	/* return address */
-
-
-/*
-** relative position of registers in save reg area
-*/
-#define	R_R0		0
-#define	R_R1		1
-#define	R_R2		2
-#define	R_R3		3
-#define	R_R4		4
-#define	R_R5		5
-#define	R_R6		6
-#define	R_R7		7
-#define	R_R8		8
-#define	R_R9		9
-#define	R_R10		10
-#define	R_R11		11
-#define	R_R12		12
-#define	R_R13		13
-#define	R_R14		14
-#define	R_R15		15
-#define	R_R16		16
-#define	R_R17		17
-#define	R_R18		18
-#define	R_R19		19
-#define	R_R20		20
-#define	R_R21		21
-#define	R_R22		22
-#define	R_R23		23
-#define	R_R24		24
-#define	R_R25		25
-#define	R_R26		26
-#define	R_R27		27
-#define	R_R28		28
-#define	R_R29		29
-#define	R_R30		30
-#define	R_R31		31
-#define	R_F0		32
-#define	R_F1		33
-#define	R_F2		34
-#define	R_F3		35
-#define	R_F4		36
-#define	R_F5		37
-#define	R_F6		38
-#define	R_F7		39
-#define	R_F8		40
-#define	R_F9		41
-#define	R_F10		42
-#define	R_F11		43
-#define	R_F12		44
-#define	R_F13		45
-#define	R_F14		46
-#define	R_F15		47
-#define	R_F16		48
-#define	R_F17		49
-#define	R_F18		50
-#define	R_F19		51
-#define	R_F20		52
-#define	R_F21		53
-#define	R_F22		54
-#define	R_F23		55
-#define	R_F24		56
-#define	R_F25		57
-#define	R_F26		58
-#define	R_F27		59
-#define	R_F28		60
-#define	R_F29		61
-#define	R_F30		62
-#define	R_F31		63
-#define NCLIENTREGS	64
-#define	R_EPC		64
-#define	R_MDHI		65
-#define	R_MDLO		66
-#define	R_SR		67
-#define	R_CAUSE		68
-#define	R_TLBHI		69
-#if defined(CPU_R3000)
-#define	R_TLBLO		70
-#endif
-#if defined(CPU_R4000)
-#define	R_TLBLO0	70
-#endif
-#define	R_BADVADDR	71
-#define	R_INX		72
-#define	R_RAND		73
-#define	R_CTXT		74
-#define	R_EXCTYPE	75
-#define R_MODE		76
-#define	R_PRID		77
-#define R_FCSR		78
-#define R_FEIR		79
-#if defined(CPU_R3000)
-#define NREGS		80
-#endif
-#if defined(CPU_R4000)
-#define	R_TLBLO1	80
-#define R_PAGEMASK	81
-#define R_WIRED		82
-#define R_COUNT		83
-#define R_COMPARE	84
-#define R_CONFIG	85
-#define R_LLADDR	86
-#define R_WATCHLO	87
-#define R_WATCHHI	88
-#define R_ECC		89
-#define R_CACHEERR	90
-#define R_TAGLO		91
-#define R_TAGHI		92
-#define R_ERRPC		93
-#define R_XCTXT     94  /* Ketan added from SIM64bit */
-
-#define	NREGS		95
-#endif
-
-/*
-** For those who like to think in terms of the compiler names for the regs
-*/
-#define	R_ZERO		R_R0
-#define	R_AT		R_R1
-#define	R_V0		R_R2
-#define	R_V1		R_R3
-#define	R_A0		R_R4
-#define	R_A1		R_R5
-#define	R_A2		R_R6
-#define	R_A3		R_R7
-#define	R_T0		R_R8
-#define	R_T1		R_R9
-#define	R_T2		R_R10
-#define	R_T3		R_R11
-#define	R_T4		R_R12
-#define	R_T5		R_R13
-#define	R_T6		R_R14
-#define	R_T7		R_R15
-#define	R_S0		R_R16
-#define	R_S1		R_R17
-#define	R_S2		R_R18
-#define	R_S3		R_R19
-#define	R_S4		R_R20
-#define	R_S5		R_R21
-#define	R_S6		R_R22
-#define	R_S7		R_R23
-#define	R_T8		R_R24
-#define	R_T9		R_R25
-#define	R_K0		R_R26
-#define	R_K1		R_R27
-#define	R_GP		R_R28
-#define	R_SP		R_R29
-#define	R_FP		R_R30
-#define	R_RA		R_R31
-
-/* Ketan added the following */
-#ifdef CPU_R3000
-#define sreg	sw
-#define lreg	lw
-#define rmfc0	mfc0
-#define rmtc0	mtc0
-#define R_SZ	4
-#endif CPU_R3000
-
-#ifdef CPU_R4000
-#if __mips < 3
-#define sreg	sw
-#define lreg	lw
-#define rmfc0	mfc0
-#define rmtc0	mtc0
-#define R_SZ	4
-#else
-#define sreg	sd
-#define lreg	ld
-#define rmfc0	dmfc0
-#define rmtc0	dmtc0
-#define R_SZ	8
-#endif
-#endif CPU_R4000
-/* Ketan till here */
-
-#endif /* __IREGDEF_H__ */
-
diff --git a/c/src/exec/score/cpu/mips64orion/mipstypes.h b/c/src/exec/score/cpu/mips64orion/mipstypes.h
deleted file mode 100644
index 50f28ccf9b..0000000000
--- a/c/src/exec/score/cpu/mips64orion/mipstypes.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*  mipstypes.h
- *
- *  This include file contains type definitions pertaining to the IDT 4650
- *  processor family.
- *
- *  Author:     Craig Lebakken <craigl@transition.com>
- *
- *  COPYRIGHT (c) 1996 by Transition Networks Inc.
- *
- *  To anyone who acknowledges that this file is provided "AS IS"
- *  without any express or implied warranty:
- *      permission to use, copy, modify, and distribute this file
- *      for any purpose is hereby granted without fee, provided that
- *      the above copyright notice and this notice appears in all
- *      copies, and that the name of Transition Networks not be used in
- *      advertising or publicity pertaining to distribution of the
- *      software without specific, written prior permission.
- *      Transition Networks makes no representations about the suitability
- *      of this software for any purpose.
- *
- *  COPYRIGHT (c) 1989-1998.
- *  On-Line Applications Research Corporation (OAR).
- *  Copyright assigned to U.S. Government, 1994.
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.OARcorp.com/rtems/license.html.
- *
- *  $Id$
- */
-/* @(#)mipstypes.h       08/20/96     1.4 */
-
-#ifndef __MIPS_TYPES_h
-#define __MIPS_TYPES_h
-
-#ifndef ASM
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- *  This section defines the basic types for this processor.
- */
-
-typedef unsigned char      unsigned8;  /* unsigned 8-bit  integer */
-typedef unsigned short     unsigned16; /* unsigned 16-bit integer */
-typedef unsigned int       unsigned32; /* unsigned 32-bit integer */
-typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
-
-typedef unsigned16     Priority_Bit_map_control;
-
-typedef signed char      signed8;      /* 8-bit  signed integer */
-typedef signed short     signed16;     /* 16-bit signed integer */
-typedef signed int       signed32;     /* 32-bit signed integer */
-typedef signed long long signed64;     /* 64 bit signed integer */
-
-typedef unsigned32 boolean;     /* Boolean value   */
-
-typedef float          single_precision;     /* single precision float */
-typedef double         double_precision;     /* double precision float */
-
-typedef void mips_isr;
-typedef void ( *mips_isr_entry )( void );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* !ASM */
-
-#endif
-/* end of include file */