diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-05-11 06:54:59 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-28 15:02:12 +0200 |
| commit | 2086948a7b06ac238c4ff0c9263c1e578e900fdd (patch) | |
| tree | 8d80d467e4636af6ac211406557f6d8e4be0f0ae /bsps | |
| parent | build: Enable RISC-V SMP build (diff) | |
| download | rtems-2086948a7b06ac238c4ff0c9263c1e578e900fdd.tar.bz2 | |
riscv: Add dummy SMP support
Update #3433.
Diffstat (limited to 'bsps')
| -rw-r--r-- | bsps/riscv/riscv/start/start.S | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/bsps/riscv/riscv/start/start.S b/bsps/riscv/riscv/start/start.S index 58bc57dc12..1d0bde164b 100644 --- a/bsps/riscv/riscv/start/start.S +++ b/bsps/riscv/riscv/start/start.S @@ -52,6 +52,11 @@ SYM(_start): la gp, __global_pointer$ .option pop +#ifdef RTEMS_SMP + csrr s0, mhartid + bnez s0, .Lloop_forever +#endif + la t0, ISR_Handler csrw mtvec, t0 @@ -70,6 +75,11 @@ SYM(_start): j boot_card +#ifdef RTEMS_SMP +.Lloop_forever: + j .Lloop_forever +#endif + .align 4 bsp_start_vector_table_begin: .word _RISCV_Exception_default /* User int */ |